BENGAL COLLEGE OF ENGINEERING

AND TECHNOLOGY, DURGAPUR

A
Project Report
on
“Cyclic Redundancy Checks”
Submitted in the Partial Fulfilment of the Requirement for the
Award of the Degree of
BACHELOR OF TECHNOLOGY
In
COMPUTER SCIENCE AND ENGINEERING
Submitted by
SAJAN SUMAN, SNEH NAYAN, ANIMESH PRASAD
College roll no. :- 162095459, 162109525,162126648
University roll no. :-12500116031, 12500116017,12500116113
Subject :- Computer Networks (CS-602)
 ABSTRACT
Cyclic redundancy codes (CRCs) provide a first line of defence against data
corruption in many networks. Unfortunately, many commonly used CRC
polynomials provide significantly less error detection capability than they might.
An exhaustive exploration reveals that most previously published CRC
polynomials are either inferior to alternatives or are only good choices for
particular message lengths. Unfortunately these shortcomings and limitations often
seem to be overlooked. This paper describes a polynomial selection process for
embedded network applications and proposes a set of good general-purpose
polynomials. 

The cyclic redundancy check (CRC) is a technique used to detect errors in digital
data. CRC is a hash function that detects accidental changes to raw computer data
commonly used in digital telecommunications networks and storage devices such
as hard disk drives. Cyclic redundancy checks are quite simple to implement in
hardware and can be easily analysed mathematically. It is one of the better
techniques in detecting common transmission errors.
ACKNOWLEDGEMENT
TABLE OF CONTENTS
 1. INTRODUCTION
Environmental interference and physical defects in the communication medium
can cause random bit errors during data transmission. Error coding is a method of
detecting and correcting these errors to ensure information is transferred intact
from its source to its destination. Error coding uses mathematical formulas to
encode data bits at the source into longer bit words for transmission. The "code
word" can then be decoded at the destination to retrieve the information. The extra
bits in the code word provide redundancy that, according to the coding scheme
used, will allow the destination to use the decoding process to determine if the
communication medium introduced errors and in some cases correct them so that
the data need not be retransmitted. Different error coding schemes are chosen
depending on the types of errors expected, the communication medium's expected
error rate, and whether or not data retransmission is possible. Faster processors and
better communications technology make more complex coding schemes, with
better error detecting and correcting capabilities, possible for smaller embedded
systems, allowing for more robust communications. However, trade between
bandwidth and coding overhead, coding complexity and allowable coding delay
between transmissions, must be considered for each application.

We know what type of errors can occur, we can’t simple recognize them. We can
do this simply by comparing this copy received with another copy of intended
transmission. In this mechanism the source data block is send twice. The receiver
compares them with the help of a comparator and if those two blocks differ, a
request for re-transmission is made. To achieve forward error correction, three sets
of the same data block are sent and majority decision selects the correct block.
These methods are very inefficient and increase the traffic two or three times.
Fortunately there are more efficient error detection and correction codes. There are
two basic strategies for dealing with errors. One way is to include enough
redundant information (extra bits are introduced into the data stream at the
transmitter on a regular and logical basis) along with each block of data sent to
enable the receiver to deduce what the transmitted character must have been. The
other way is to include only enough redundancy to allow the receiver to deduce
that error has occurred, but not which error has occurred and the receiver asks for a
retransmission.
 2. THEORY
2.1 CYCLIC REDUNDANCY CHECKS (CRC)
This Cyclic Redundancy Check is the most powerful and easy to implement
technique. Unlike checksum scheme, which is based on addition, CRC is based
on binary division. In CRC, a sequence of redundant bits, called cyclic
redundancy check bits, are appended to the end of data unit so that the resulting
data unit becomes exactly divisible by a second, predetermined binary number.
At the destination, the incoming data unit is divided by the same number. If at
this step there is no remainder, the data unit is assumed to be correct and is
therefore accepted. A remainder indicates that the data unit has been damaged
in transit and therefore must be rejected. The generalized technique can be
explained as follows.

If a k bit message is to be transmitted, the transmitter generates an r-bit

sequence, known as Frame Check Sequence (FCS) so that the (k+r) bits are
actually being transmitted. Now this r-bit FCS is generated by dividing the
original number, appended by r zeros, by a predetermined number. This
number, which is (r+1) bit in length, can also be considered as the coefficients
of a polynomial, called Generator Polynomial. The remainder of this division
process generates the r-bit FCS. On receiving the packet, the receiver divides
the (k+r) bit frame by the same predetermined number and if it produces no
remainder, it can be assumed that no error has occurred during the transmission.
Operations at both the sender and receiver end are shown in Fig. 01.

Fig 2.1 : Basic scheme for Cyclic Redundancy Checking

This mathematical operation performed is illustrated in Fig. 02 by dividing a
sample 4-bit number by the coefficient of the generator polynomial x 3+x+1,
which is 1011, using the modulo -2 arithmetic. Modulo-2 arithmetic is a binary
addition process without any carry over, which is just the Exclusive-OR
operation. Consider the case where k=1101. Hence we have to divide 1101000
(i.e. k appended by 3 zeros) by 1011, which produces the remainder r=001, so
that the bit frame (k+r) =1101001 is actually being transmitted through the
communication channel. At the receiving end, if the received number, i.e.,
1101001 is divided by the same generator polynomial 1011 to get the remainder
as 000, it can be assumed that the data is free of errors.

Figure 2.2 : Cyclic Redundancy Checks (CRC)

The transmitter can generate the CRC by using a feedback shift register
circuit. The same circuit can also be used at the receiving end to check
whether any error has occurred. All the values can be expressed as
polynomials of a dummy variable X. For example, for P = 11001 the
corresponding polynomial is X4+X3+1. A polynomial is selected to have at
least the following properties :-
 It should not be divisible by X.
 It should not be divisible by (X+1).

The first condition guarantees that all burst errors of a length equal to the
degree of polynomial are detected. The second condition guarantees that all
burst errors affecting an odd number of bits are detected.

2.2 Performance
CRC (CYCLIC REDUNDANCY CHECKS) is a very effective error
detection technique. If the divisor is chosen according to the previously
mentioned rules, its performance can be summarized as follows:

 CRC can detect all single-bit errors

 CRC can detect all double-bit errors (three 1’s)
 CRC can detect any odd number of errors (X+1)
 CRC can detect all burst errors of less than the degree of the
polynomial.
 CRC detects most of the larger burst errors with a high probability.
The CRC polynomials can show that they give performance of up to several
orders of magnitude better than standard CRC polynomials on short
messages subject to independent bit errors without compromising
performance on burst error detection. The optimal polynomials can be
directly substituted for standard polynomials with no change in algorithm,
computation speed, or network bandwidth requirements to attain better error
detection performance (assuming, of course, that both transmitting and
receiving nodes use the same polynomial for their CRC calculations).

3. IMPLEMENTATION OF CRC
#include<stdio.h>
#include<conio.h>
int gen[4],genl,frl,rem[4];
void main()
{
int i,j,fr[8],dupfr[11],recfr[11],tlen,flag;
clrscr();
frl=8; genl=4;
printf(“enter frame:”);
for(i=0;i<frl;i++)
{
Scanf(“%d”,&fr[i]);
Dupfr[i]=fr[i];
}
Printf(“Enter generator:”);
For(i=0;i<gen1;i++)
Scanf(“%d”,&gen[i]);
tlen=fr1+gen1-1;
for(i=fr1;i<tlen;i++)
{
Dupfr[i]=0;
}
Remainder1(dupfr);
For(i=0;t<fr1;i++)
{
Recfr[i]=fr[i];
}
For(i=fr1j=1;j<gen1;i++j++)
{
recfr[i]=rem[j];
}
Remainder1(recfr);
Flag=0;
For(i=0;i<4;i++)
{
If(rem[i]!=0)
Flag++;
}
 CONCLUSION
After working on this project we conclude that, there are various methods
available to detect and check errors like parity check, check sum, cyclic
redundancy check, hamming code which are capable of detecting and
correcting the errors, the errors can be a single error or burst error type. All
these techniques are not capable of handling burst error (the error in which
more than 1 bits are damaged), but cyclic redundancy check is capable of
handling both types of errors with very high accuracy due to its unique
working strategy which is that it generates unique extra data bits for the
original data and new data is created to send to receiver by adding unique
extra bits generated to original data, now on the receiver site the data is
checked and if the check algorithm returns 0, the data is accepted , otherwise
rejected. Although there is one major drawback that both sender's and
receiver's site must be synchronized means they use the same divisor,
otherwise this technique is not applicable.
 REFERENCES
[1]
[2] nptel/computer networks and internet protocol.
[3] www.geeksforgeeks.com
[4] www.techopedia.com
[5] www.sciencedirect.com
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