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Vlsi Cad:: Logic To Layout

This document provides an introduction to a class on VLSI CAD tools. It outlines the course logistics, including assignments, grading tracks and timelines. It also defines key terms related to VLSI design automation and semi-custom ASIC design. The document introduces the overall CAD flow from high-level design entry to final layout.

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Himanshu
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0% found this document useful (0 votes)
199 views13 pages

Vlsi Cad:: Logic To Layout

This document provides an introduction to a class on VLSI CAD tools. It outlines the course logistics, including assignments, grading tracks and timelines. It also defines key terms related to VLSI design automation and semi-custom ASIC design. The document introduces the overall CAD flow from high-level design entry to final layout.

Uploaded by

Himanshu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 13

VLSI CAD: Lecture 1

Logic to Layout Welcome & Introduction

Rob A. Rutenbar
University of Illinois
Welcome!
•  What we are about in this class…

VLSI CAD
Tools

Slide 2 © 2013, R.A. Rutenbar


Class Logistics
•  10 weeks = 8 weeks of lectures + 1 free week + final exam
•  Videos every week
•  2-3 hours in total

•  8 Problem Sets (i.e., homework assignments)


•  8 weeks of video material ! 8 assignments
•  Leave Week-9 open for you to finish stuff

•  4 Programming Assignments (i.e., you write some code/scripts)


•  Some conventional coding
•  Some ‘scripts’ run thru CAD-centric tools running on our servers

Slide 3 © 2013, R.A. Rutenbar


Class Grading: Two Tracks
•  Basic Track •  Advanced Track
•  8 Problem Sets = 75% •  8 Problem Sets = 40%
•  Same single submit policy
•  Single submission; late
submission allowed after •  4 Program Assignments = 40%
deadline for 50% of credit •  Multiple submissions ok; late
submission allowed after
•  1 Final exam = 25% deadline for 50% of credit
•  Single submission. •  1 Final exam = 20%
•  Same single submission
•  Idea: Do this is you don’t
have time to do the code •  Idea: Do this for deepest
understanding of course
Slide 4 © 2013, R.A. Rutenbar
Other Important Stuff
•  Honor code
•  OK to talk with and work with other people in the class
•  BUT – what you submit must be your own work, for homework and for any code
•  AND – please do NOT post solutions to any assignments on Coursera site, or share
these solutions face to face, in email, via the web, with others in this course

•  Use Coursera interaction mechanisms


•  Coursera supports discussion forums to ask questions, etc.
•  We will make use of these to help connect you to us (and to each other)

Slide 5 © 2013, R.A. Rutenbar


What Background Do You Need?
•  Computer science •  Mathematics
•  Basic programming skills •  Discrete: Basic sets,
functions, careful notation
•  Data structures
•  Exposure to graph theory is
•  Computer engineering
nice but not essential
•  Basic digital design (gates, flip
•  Continuous: Basic calculus,
flops, Boolean algebra, Kmaps)
derivatives, integrals, matrices
•  Combinational and sequential
•  Basic VLSI knowledge
design (finite state machines)
•  Some chip layout exposure is
nice, but not essential
Slide 6 © 2013, R.A. Rutenbar
So What is the Course All About...?
•  CAD for semi-custom ASICs
•  ASIC = application-specific integrated circuit
•  Semi-custom = try to design reusing some already designed parts
•  CAD = flow through a sequence of design steps and software tools

HDL Gates + Mask


Digital
code wires shapes
High-Level Logic Layout
Description Synthesis Synthesis
Language

Library Support
(cells, memories, cores, etc)
Slide 7 © 2013, R.A. Rutenbar
Some Useful Acronyms
•  Semi-custom ASIC
•  Application-specific IC - design a chip for a specific task, using mostly semi-
custom techniques
•  Do not expect to make a zillion of them, so cannot afford full custom
•  Not quite as dense (transistors / area) or as fast (GHz) as full custom

•  Semi-custom vs. full-custom


•  Semi-custom: designs mostly from pre-existing parts (gates, memories)
•  Full-custom: designs right down at the individual transistor level
•  Today, only things like microprocessors are full custom
•  And in fact, even these chips have huge semi-custom parts on them

Slide 8 © 2013, R.A. Rutenbar


One More: CAD vs. EDA
•  CAD: Computer-Aided Design
•  What we all used to call this world of tools for chip design
•  Problem: other people do “CAD” too, like mechanical engineers, architects, etc.

•  EDA: Electronic Design Automation


•  What most “insider” chip folks call it. More accurate, more descriptive name
•  Problem: people outside the business not always clear what it means.

•  So, I called this class “VLSI CAD,” but it’s really “VLSI EDA”

Slide 9 © 2013, R.A. Rutenbar


More Acronyms: System-on-a-Chip ASIC
•  SOC: Integrates many blocks of function on one big chip
•  Most common: row-based standard cells = gates + flops in rows; and big SRAM
memories; and perhaps pre-designed blocks like CPUs

Random
CPU Logic Memory
Core

Datapath (arithmetic)
Cells

Wiring

Slide 10 © 2013, R.A. Rutenbar


Example: Small SOC Controller Design
•  Look at blocks
Memories

Random
control
logic

CPU core

Analog interface
to external world
Slide 11 © 2013, R.A. Rutenbar
Another Important Term: CAD Flow
•  How to attack big designs like these?
Step 1
•  Big idea: Levels of abstraction
•  Break problem down into smaller steps Step 2
•  Each step renders design a little more real
Step 3
•  Synthesis steps:

•••
•  Go forward in design: Make new stuff
•  Verification steps:
•  Look backward: Check that it worked
Step N

•  Complete set of steps called: A Flow


Slide 12 © 2013, R.A. Rutenbar
Our Class CAD Tool Flow
•  Start with some Boolean / logic
Logic Synthesis design description…
Logic Verification •  …end with gates+wires, located at
(x,y) coordinates on chip
Layout Synthesis

Timing Verification •  Note: very over-simplified


•  Big goal(s) for class
•  Explain the critical algorithms, data
structures & modeling assumptions
used in each of these big steps
Slide 13 © 2013, R.A. Rutenbar

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