Synplify Synthesis Faq PDF
Synplify Synthesis Faq PDF
Synplify Synthesis Faq PDF
Version 1.0
Table of Contents
Introduction to Synopsys Synplify .............................................................................. 4
1. What does Synplify do? ............................................................................................................4
2. Which HDL language does Synplify support? ........................................................................4
3. Will Synplify accept manual instantiations of Actel macros?...............................................4
4. How does Synplify work with Actel tools?..............................................................................4
Licensing Download Installation ................................................................................. 5
5. Where can I download the latest Synplify release? ...............................................................5
6. Which version of Synplify is released with the latest Libero IDE? .......................................5
7. How do I upgrade to the latest version of Synplify and use it in the Libero IDE Project
Manager? ................................................................................................................................................5
8. Do I need a separate license to run Synplify in Libero IDE? .................................................5
9. Where and how do I get the license for Synplify? ..................................................................5
10. Why can’t I run Synplify in batch mode? What license does it require? .............................5
11. Why is my Synplify license not working? ...............................................................................6
12. Can I use the Synplify license obtained from Actel to run any version of Synplify? .........6
Warnings/Error Messages............................................................................................ 7
13. Warning: Top entity isn't set yet! .............................................................................................7
14. Warnings on Register Pruning. ................................................................................................7
15. @W: FP101 |The design has 8 instantiated global buffers but allowed is only 6 ...............8
16. Error: The profile for tool Synplify is interactive and you are running in batch mode: this
tool cannot be invoked ..........................................................................................................................8
17. @E: CG103 :"C:\PATH\code.vhd":12:13:12:13|Expecting expression .................................9
18. @E:Internal Error in m_proasic.exe .........................................................................................9
19. @W: CD639 :"C:\Program
Files\2PAC3MSE\PAC3_j\viewdraw\PAC_3.vhd":306:11:306:17|Bit <0> of signal s15_cnt is
undriven ..................................................................................................................................................9
20. @W: BN269 |Library ARC Pruning: Multiple bidi in cell BIBUF_LVDS. Pruning
abandoned. .............................................................................................................................................9
21. Why has my logic block disappeared after synthesis? .........................................................9
Attributes/Directives ................................................................................................... 10
22. How do I turn off automatic clock buffer usage in Synplify? ..............................................10
23. Which attribute is used for preserving registers?................................................................10
24. Does syn_radhardlevel attribute support IGLOO and Fusion families? ............................10
25. How do I “Disable serial optimization” in Synplify? ............................................................10
26. How can I add an attribute in Synplify?.................................................................................10
27. How do I insert a clock buffer in my design?........................................................................11
28. How do I increase the number of global clock buffers used in my design? .....................11
29. Is there any way to preserve my logic if the output ports are not used in my design? ...12
30. Why is synthesis optimizing my high fanout net to buffered clock? .................................12
31. How do I use the syn_encoding attribute for an FSM design? ...........................................12
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