DRONE TECHNOLOGY

A SEMINAR REPORT
SUBMITTED TO
Jawaharlal Nehru Technological University, Anantapur.
In partial fulfillment of the requirement for the
Award of degree of
Bachelor of Technology
In
ELECTRONICS & COMMUNICATION ENGINEERING
During the year 2015-2019
V.JYOTHI 15F81A0415
UNDER THE ESTEEMED GUIDANCE OF
Mrs.K.S.GOMATHI, M.Tech.,
Assistant professor in Electronics and Communication
Engineering

GOKULA KRISHNA COLLEGE OF ENGINEERING

(Affiliated to JNTU, Ananthapur)
Sullurpet-524121 , S.P.S.R. Nellore(DT.)
 ABSTRACT

High speed smart pixel arrays (SPAs) hold great promise as an enabling technology

for board-to-board interconnections in digital systems. SPAs may be considered an

extension of a class of optoelectronic components that have existed for over a decade,

that of optoelectronic integrated circuits (OEICs). The vast majority of development

in OEICs has involved the integration of electronic receivers with optical detectors

and electronic drivers with optical sources or modulators. In addition, very little of

this development has involved more than a single optical channel. But OEICs have

underpinned much of the advancement in serial fiber links. SPAs encompass an

extension of these optoelectronic components into arrays in which each element of the

array has a signal processing capability. Thus, a SPA may be described as an array of

optoelectronic circuits for which each circuit possesses the property of signal

processing and, at a minimum, optical input or optical output (most SPAs will have

both optical input and output). The name smart pixel is combination of two ideas,

"pixel" is an image processing term denoting a small part, or quantized fragment of an

image, the word "smart" is coined from standard electronics and reflects the presence

of logic circuits. Together they describe a myriad of devices. These smart pixels can

be almost entirely optical in nature, perhaps using the non-linear optical properties of

a material to manipulate optical data, or they can be mainly electronic, for instance a

photoreceiver coupled with some electronic switching.

 CONTENTS
Introduction
Smart pixel definition
a.connection density
b.complexity
c.aggregate capacity
smart pixel partitioning
a.uniformly disrtibuted
b.centralized
c.clusteri
smart pixel technology
a.modulation-based smart pixels
(1)fet-seed smart pixe
Hybrid cmos-seed smar
b. source –based smart pixels
(1) hybrid MSMA’CSEL smart pixels
(2) ELO-based smart pixels
(3) MONOLITHI MSM/MESFETNCEL
Smart pixel
(4) fip-chip boned VCSSEUMSM smart
Pixels
a. Spa aggregate capacity
b. Spa complexity
c. Spa demonstrator performance
advantages
disadvantages
applications
conclusion
 INTRODUCTION

A smart pixel is an optoelectronic structure composed of A electronic processing

circuitry (CMOS, BiCMOS, bipolar, etc.) enhanced with optical inputs and/or outputs
. The optical signals entering and/or leaving the smart pixels are typically arranged
into two-dimensional (2-D) arrays that can be supported by the free-space optical
interconnection of different smart pixel arrays (SPA’s). In the simplest case, a SPA is
formed by creating a 2-D array of similar smart pixels (uniformly distributed) as
shown in Fig. 1. The input optical signals to these smart pixels are detected by
optoelectronic devices such as p-i-n or metalsemiconductor-metal (MSM)
photodetectors. These detected signals are then amplified to the required (digital)
electrical levels by analog electrical amplifiers . Once the signals have been amplified
to the appropriate electrical level they can be processed by the specific electrical
circuitry of the smart pixel. The functionality of the smart pixels can range from one
or two transistors providing some type of nonlinear gain to a smart pixel composed of
several thousand transistors processing an ATM packet header. For this uniformly
distributed type of SPA, the electronics in each smart pixel arc localized to the area of
the smart pixel preventing long, across-chip lines that can lead to reduced electrical
performance because of skew, crosstalk, and the special drivers required to drive the
longer electrical interconnects Finally, after the input signals, both optical and
electrical, have been processed, they can be directed to the optoelectronic outputs.
These can be either sources, such as LED’s or VCSEL’s, or modulators such as MQW
p-i-n diodes.
 Fig. 1. Smart pixel array.

SMART PIXEL DEFINITIONS

As the smart pixel technology continues to evolve, there needs to be a basic

understanding and acceptance of key performance metrics including connection
density, complexity, and aggregate capacity

A. Connection Density
Since optical interconnection is the prime advantage of SPA’s , the number of
optical inputs and outputs of a SPA becomes an important parameter. The
connection density refers to the number of optical connections per cm2 (input
+ output) supported by a SPA and its associated optical interconnect. As an
example, if there are 1000 smart pixels in a 1-cm2 SPA and each smart pixel
requires two signal inputs and two signal outputs, then the connection density
that would need to be supported by the interconnect optics would be 4000
connectionslcm2. If the signals are differential, then the connection density
would need to be 8000 connections/cm2.
B. Complexity
The second major advantage of SPA’s is the intelligence provided through the
electronic processing circuitry. It is this intelligence that allows the smart
pixels to perform complex operations on the data enteringlexiting the SPA. It
is this intelligence that separates SPA’s from photonic integrated circuits
(PIC’S) where PIC’s refer to monolithically integrated optical and
 optoelectronic devices (lasers, detectors, optical waveguides, gratings,
couplers, etc.) but do not include electronic structures. The complexity of the
SPA’s will be defined as the average number of transistors per optical YO. It
will be calculated by dividing the total number of transistors in the SPA by the
total number of optical VO.
C. Aggregate Capacity
To exploit the connectivity advantage of free-space optics, each SPA should
have an aggregate optical throughput or capacity that is much larger than the
electrical aggregate capacity. The aggregate optical capacity refers to the sum
of all the optical inputs and/or outputs multiplied by their associated bit rates.
On the other hand, the aggregate electrical capacity refers to the sum of all the
electrical inputs and outputs multiplied by their associated bit rates.

SMART PIXEL PARTITIONING

The physical architecture or partitioning of the optical I/Os in SPA’s is

constrained by the type of optical interconnect employed in the system. There
are three basic partitioning approaches, including: 1) uniformly distributed
smart pixels, 2) concentrated UOs, and 3) clustered smart pixels. Each is
described below.
A. Uniformly Distributed
For the case of uniformly distributed smart pixels (Fig. 1), there are two
major interconnection methodologies. The first is to use a large, complex,
and bulky multi-element imaging system that will support a large field of
view to cover the entire SPA and at the same time have a low enough f/#
to collect the light emitted from the SPA sources and also image the
received input information onto the SPA photodetectors. Despite the
tremendous amount of progress in developing these systems, they tend to
be both bulky and expensive. Examples of this approach include both
AT&T System4 architecture, which imaged 32 x 32 optical channels
between six uniformly distributed SPA chips , and Systemb, which
provides the interconnection of - 10 000 optical channels on/off a single
uniformly distributed SPA . A second approach is to provide each optical
 input and/or output with its own pchannel through the use of lenslet arrays
as illustrated in Fig. 2. These lenslet arrays have the potential of being
mass produced and inexpensive. In this particular configuration, the
separation between the optical U0 is equal to the size of the lenslet arrays.
Thus, the total number of optical connections that can be supported by the
pchannel approach is relatively small. Despite this limitation, this type of
optical interconnect could be effective for complex SPA’s that require a
large area per smart pixel (a large number of transistors per optical UO).
Fig. 2. Fig. 3. Microchannel interconnected SPA’s Lenslet Clus Arrays er
SpA SPA clustered interconnects
B. Centralized
I/O To reduce the field of view required by the interconnection optics, the
SPA’s can be partitioned such that the optical 110 for all the smart pixels
is concentrated together in the center of the SPA. The advantage of this
partitioning is that the optical VO can be tightly packed, thus reducing the
field of view of the interconnection optics, which reduces the complexity
and cost of the optics. The disadvantage is that the centralization of the
optical I/O creates an electrical interconnection bottleneck in routing the
electrical signals from the surrounding SPA electronics to the tightly
packed optoelectronic U0 devices. This electrical connectivity issue is the
same problem faced by large spatial light modulators.
C. Clustering
Clustering is a combination of both of the previous partitioning methods .
In this approach, the optical VO for a small group of the smart pixels is
clustered together as shown in Fig. 3. The size of the cluster is linked to
the size of the lenslet that will support each cluster. In this case, the lenslet
will support multiple channels instead of the single channel per lenslet
supported in the pchannel approach. This approach can provide a
significant connection density when the distance between the SPA’s is
small . It also builds on the inexpensive lenslet technologies and avoids the
use of expensive bulk lenses. This approach has been recently used in
McGill’s Phase I1 Hybrid CMOS-SEED system demonstrator.
Fig. 2. Microchannel interconnected SPA’s

Fig. 3. clustered interconnects

SMART PIXEL TECHNOLOGIES

There are several rapidly evolving SPA technologies approaching the point
where they can be used in full-scale optoelectronic systems. These SPA
technologies can be categorized as either modulator-based or source-based
smart pixels. The modulator-based SPA’s were the first to be developed
and have been included in several demonstration systems. The source-
based SPA’s are rapidly evolving as the characteristics of VCSEL’s are
improving. Both of these categories of SPA’s will be discussed in the
section below.
A. Modulator-Based Smart Pixels
The first SPA technologies to be developed were based on the
monolithic integration of photodetectors, electronics, and modulators
into a single functional device. There are two major advantages of
modulator-based SPAS: 1) they are simple devices and should be
reliable, manufacturable, and uniform, and 2) the input light (power
supply) can be centrally controlled, thus simplifying system
 synchronization. The major disadvantage is that the required
interconnect optics are significantly more difficult. The three major
SPA technologies discussed in this section are the FET-SEED Hybrid
CMOSSEED and liquid-crystal-on-silicon technologies.
1) FET-SEED Smart Pixels:
The ET-SEED technology was the first smart pixel technology to
monolithically integrate:
1) multiple-quantum-well (MQW) reflection modulators based on a
GaAs-Al,Gal-,As stack,
2) p-i-n photodetectors using the same MQW stack as the modulators,
3) dopedchannel MIS-like field effect transistors (DMT), and
4) optional integrated resistors . The cross section of the FET-SEED
technology is shown in Fig. 4. A single molecular-beam epitaxial
(MBE) growth sequence is used to provide the DMT channel, the
quantum well absorbing region for both the modulators and
photodetectors, the doped n- and p-type contact layers, and the
dielectric mirrors required by the reflection modulators. Reflection
modulators were used to provide both a structure suitable for batch
fabrication and to enable heat sinlung on the back side of the chip.
Heat sinking is necessary in order to insure a stable excitonic
absorption wavelength. These basic circuit elements were then stitched
together using the buffered FET logic (BFL) to form larger and more
complicated functional circuits. As an example of the general
functionality of this technology, below is a list of the circuits that were
designed at the AT&T/ARPA FET-SEED workshop [lo].
 Time-integrating correlator
 Transceiver arrays
 Crossbar switch array
 Address decoders
 Smart spatial light modulator arrays
 Shift registers
 Wavelet transformer self-routing switching nodes
 Serial-to-parallel converters
  Exchangehypass switching nodes
 Pulse-arithmetic neural network
 Test circuits

Fig. 5 is a photograph of one of the smart pixels in the 4 x 4 FET-

SEED SPA used in the AT&T Systems photonic switching system
demonstrator . Each smart pixel included 24 FET’s, 17 diodes,
four MQW photodetectors, and four MQW modulators and was
able to operate at 400 Mb/s. The FET-SEED technology has also
been employed in demonstration systems at McGill University (1
6-channel optical backplane) [ 121, Optivision (16-channel optical
interconnect) , and the University of Southern California (network
application circuits) .

Fig. 4. Cross section of the AT&T ET-SEED technology.

Hybrid CMOS-SEED Smart Pixels:

The Hybrid CMOSSEED technologies were pursued based on
the philosophy that individual optical logic gates will not be able to
compete with the existing or future silicon electronics technology
platforms
 Fig. 5. AT&T System5smart pixel.
with respect to power consumption, device size, and system
complexity. It has also become obvious that silicon electronics is going
to continue to increase in both performance and complexity while its
cost will continue to decrease. Rather than compete with this rapidly
growing technology, the objective of the smart pixel technology is to
complement it. Since the added value of optics in the digital electronic
domain is interconnection, providing optical inputs and outputs for the
existing electronic integrated circuit platforms became the
technologies' driving force. The first approach at integrating
modulators/photodetectors onto silicon circuits was to put InGaAs
modulators on silicon CMOS chips.
This use of GaAs-A1,Gal -,As modulators/photodetectors on
silicon CMOS was then pursued by AT&T. In this process, MQW
modulators/photodetectors are grown on GaAs chips such that the n
and p contacts are coplanar (see Fig. 6). A Ti-Au pad is then deposited
at the location of the optical windows of the MQW
modulators/photodetectors to act as a 40% reflector. A lead-tin alloy is
then deposited on the electrical contacts of the
modulators/photodetectors to be used for the flip-chip bonding
between the two substrates. The silicon CMOS chips have been
obtained from the MOSIS foundry (both 1.2-pm and 0.8-pm line rules
have been used). The aluminum bonding pads on the CMOS chip are
then coated with a thin Ti-Pt-Au to provide a solder-wetable surface
for the solder bump bonding later in the process. The two chips are
then flip-chip solder-bonded together. Prior to removing the GaAs
substrate, a silica-filled epoxy is wicked between the chips to protect
both the GaAs and silicon chips.
The GaAs substrate is then etched off, leaving only the small
MQW modulators/photodetectors in the desired locations on the chip.
An antireflection coating is then applied across the chip. A close-up of
a CMOS-SEED SPA is shown in Fig. 7. It should be pointed out that
this technique is not limited exclusively to silicon CMOS but could be
used with other silicon circuit families such as ECL, bipolar, BiCMOS,
etc. As an example of the general functionality of this technology,
below is a list of the circuits that were designed at the

Fig. 6. Hybrid CMOS-SEED process

AT&T/ARPA Hybrid-SEED Workshop .
  Half-tone imaging

 Shared memory processor interconnect

 Multi-access interconnect architecture

 Digital cellular

 Imaging processor

 Optical A/D converter

 Optical permutation network

 Programmable logic smart pixel devices

 Crossbar switch Sorting switching nodes

 ATM switching nodes

 ATM-based optical backplane

 Focal plane processor

 Field programmable smart pixel arrays

 High-performance bus interface

 Linear fringe detector FFT nodes

 Wavelength meter

 Position-tolerant array sensor

 Cellular neural network

 Detector arrays

 Multidimensional interchanger

An example of a complete CMOS-SEED SPA is shown in Fig. 8. It is a 4 x 9 SPA for a

buffered HyperPlane ATM backplane-based switching fabric. It includes -60 transistors per
smart pixel with a total of -20 600 transistors in a 4-mm2 area. It also includes 144 optical
inputs and outputs and can store up to three concurrent ATM cells . This technology has
operated at bit rates greater than 1 Gb/s .

3) Liquid Crystal on Silicon:

Finally, the liquid-crystal-onsilicon (LCOS) smart pixel technology provides optical out
 Fig. 7. Close-up of a CMOS-SEED smart pixel

Fig. 8. Buffered HyperPlaneSPA

puts for any standardized electronic platform through the use of integrated arrays of
liquid-crystal modulators 1201. The majority of this effort has focused on the
integration of the high-birefringence and low-voltage operation of ferroelectric liquid-
crystal (FLC) modulators on preprocessed silicon CMOS circuits. The cross section of
an experimental LCOS device is shown in Fig. 9 1211. The construction of this device
begins with a silicon substrate that provides both the mechanical support for the
assembly as well as the general electrical interconnect for the electrical signals
entering and leaving the SPA. The silicon CMOS integrated circuit is first solder
bonded to the silicon substrate and then the electrical connections between the CMOS
chip and the substrate are made using standard wire-bonding techniques. The next
step is to mount the SPA cover glass, which is composed of:

1) optically flat glass,

2) IT0 coating,

3) FLC alignment layer,

4) mechanical polyimide spacers,

5) solder pads, and

a foursided trench with a hole drilled through the front surface. This is
accomplished with a solder reflow process that allows the solder joints to self-align
and provide the necessary force to

Fig 9 Liquid-crystal-on-silicon.

maintain the desired spacing for the FLC. An FLC paste is the place in the
hole where it will become a liquid when the structure is heated in a vacuum chamber.
The liquid FLC will then fill the gap between the cover glass and the silicon CMOS
integrated circuit by capillary action. Although this technology is limited to modulator
response times in the microseconds regime, it has found many applications that
require massive optical interconnection. Examples include spatial light modulators,
displays, and optical neural networks .

B. Source-Based Smart Pixels

An alternate to the modulator-based SPA'S described above is a smart pixel

technology based on the use of optical sources for the SPA outputs instead of
modulators. The simplest, and most near-term, approach is to bring together, in a
hybrid package, an electronic processing platform such as CMOS, an array of optical
detectors, an electronic processing platform such as CMOS, andor an array of optical
sources such as VCSEL's. A second approach is to place the optoelectronic
components on the electronic platform via thin-film integration techniques. A third
approach is to flip-chip bond the detector and VCSEL arrays directly onto the
electronic platform. Finally, the fourth approach is to monolithically integrate the
detectors, electronics, and sources all onto a single substrate. Each of these
approaches is described below.

1) Hybrid MSMA'CSEL Smart Pixels:

The VCSELMSM hybrid technology is based on the hybrid
integration of VCSEL's, MSM photodetectors, and a standard electronic
integrated circuit platform such as ECL, bipolar, CMOS, BiCMOS, etc.
into a common electronic package [221. An example of this approach is
shown in Fig. 10 where a 4 x 4 VCSEL array, a 0.8-pm CMOS chip
fabricated through the MOSIS process, and a 4 x 4 array of MSM detectors
were packaged together in the same PGA package . Due to manufacturing
costs, this is a short-term solution and will eventually be replaced by one
of the other source-based approaches.
2) ELO-Based Smart Pixels:
Using a technique referred to as epitaxial lift off (ELO) 1241, high-
quality, single-crystal thin-film materials and devices can be separated
from a latticematched growth substrate using selective etching and then
 aligned and bonded to a host substrate such as preprocessed

Fig. 10. Hybrid MSM/CMOS/VCSEL smart pixel array.

silicon CMOS substrates. The devices to be bonded to the host substrate are removed
from the growth substrate through stop-etch layers. These epitaxial thin-film devices
are then handled manually using a thick (100 pm) wax handling layer. Using this
handling layer, the devices are then attached to a transparent transfer diaphragm
constructed of either polyimide or mylar and supported by a ring of silicon on the
outer edge. The diaphragm is then inverted with the thin-film devices facing the host
substrate. The optoelectronic devices are then visually aligned and bonded to the host
substrate using a pressure probe . The performance of these devices has been shown
to be comparable to that of devices that have not been separated from the growth
substrate . This technology has been able to demonstrate the placement of 64 AlGaAs
detectors on a single silicon substrate (see Fig. 1 l), thin-film LED-based transmitters
that operate at 155 Mb/s and receivers that operate at 250 Mb/s . It has also become
driving SPA technology in a through-wafer systems effort. This technology is not
limited to source-based outputs but could also be applied to modulatorbased SPA’s.

3) Monolithic MSM/MESFETNCSEL Smart Pixels:

 The GaAs MSMIMESFETNCSEL smart pixel is based on the monolithic
integration of VCSEL’s, MSM detectors, and MESFET transistors. This smart pixel
technology, pioneered by NTT, uses optical sources instead of modulators as the
output device in each smart pixel. Smart pixels based on this technology have
demonstrated 3-dB bandwidths of 220 MHz. Fig. 12 is a picture of a simple
monolithically integrated MSMMESFETNCSEL smart pixel.

4) Flip-Chip Bonded VCSEUMSM Smart Pixels:

A natural extension of the Hybrid-SEED technology is to flip-chip bond

VCSEL’s to an electronic platform instead of modulators.

Fig. 11. circuitry. EL0 ALCaAs-based p-i-n detectors on silicon neural network

Fig. 12. NTT monolithic GaAs MSMIMESFETNCSEL smart pixel.

A. SPA Aggregate Capacity:

Fig. 13 illustrates the progress in aggregate capacity of single SPA’s as a

function of connectivity (pin-outs per chip) and per channel data rate (bits per
second). The upper right corner of the figure (shaded) is the desired high-performance
region supporting greater than a terabit aggregate capacity. The performance of
several of the SPA device demonstrators representing the different SPA technologies
have been mapped onto the figure. In this figure, the S-SEED devices represent the
progress associated with simple optical logic gates. Despite the progress in developing
optical logic gates, it became obvious that more speed and intelligence was needed.
The first generation of these high-performance SPA’s (HP-SPA) were primarily 4 x 4
arrays with bit rates ranging from 10-500 Mb/s. The next generation will be targeting
8 x 8 SPA’s (or larger) as the device demonstrators for the 1996-1997 timeframe.

Another class of SPA’S, the high-density SPA’s (HD-SPA), targeting the

high-connection density applications such as

Fig 13 The smart pixel array conneclivily versus the individual optical channel
bit rate.

smart spatial light modulators has also made significant progress. This
progress is illustrated in the lower right corner of the figure. The target devices for
this type of smart pixel include large arrays greater than 512 x 512 with modulator
switching speeds in the 100-ps range.

B. SPA Complexity

Fig. 14 shows the trends in SPA intelligence. Since SPA’S are based on the
electronic integrated circuit technologies, they will be directly linked to the evolution
of the semiconductor industry. The Semiconductor Industry Association’s
semiconductor roadmap, partially listed in Table I, illustrates the projected evolution
of both the semiconductor electronic and the smart pixel technologies to the year 2010
[46]. Based on these SIA projections, it is conceivable that by the year 1998, 32 x 32
SPA’s will be using 0.25-pm CMOS with each smart pixel containing up to 4000
transistors and operating in excess of 450 Mbls per channel. This would provide
greater than 450 Gbls aggregate capacity per SPA! Further extrapolation leads to the
year 2007 when 32 x 32 SPA’s will be using 0.1-pm CMOS with each smart pixel
containing up to 12 000 transistors and operating in excess of 1 Gb/s per channel. This
would realize the technology design objective of 1 Tb/s aggregate capacity per SPA.

C. SPA Demonstrator Performance

There have been several SPA-based systems that have been successfully
constructed and demonstrated within the past few years. These demonstrators include
photonic switching

systems, optical computing systems, and free-space optical backplanes. The

performance of these systems is shown in Fig. 15. The total systems connections is
the sum of the individual SPA connectivities. As an example, the 1993 AT&T System
included five 4 x 4 FET-SEED SPA’s. Each SPA had 32 optical inputs (32 optical
channels comprised of 64 differential optical signals) and 32 optical outputs (64
differential optical signals) for a total of 640 system optical connections (this does not
include the optical power supply inputs, 64 per SPA, required for this type of
modulator-based
 Fig 14 The smart pixel array complexity versus the individual optical channel
bit rate

Fig. 15. SPA system connectivity versus the individual optical channel bit rate

ADVANTAGES

 Smart pixel arrays provide high data –transmission rates through high-
speed switching
 Decreased cross-talk
 Smart pixel interconnects are lighter are they are made of feather-light
fiber ribbons
 High processing speeds by consuming significantly less optical power
 DISADVANTAGES

 The greatest challenge being faced by smart pixel technology is

economic.
 There exists potential problems in getting the electrical design to
interact with the optics.
 The low efficiency of photodectors result in reduced switching speed
thus decreasing the data transfer rate.
 Non-uniformity may result due to fabrication imperfections.

APPLICATIONS

There are two main classes of applications that match the capabilities of the
smart pixel technologies: high-performance intelligent interconnects and high-density
interconnects. Highperformance intelligent interconnects refer to applications that
require a modest number (10-10 000) of high-performance interconnects (> 100 Mb/s)
supported by a significant amount of intelligence (>50 transistors per optical UO).
This application class includes optical backplanes, switching networks, and high-
performance computers. The second class of applications, high-density interconnects,
focuses more on connectivity (1000-100 000) than performance (< 100 Mb/s) and/or
intelligence

Fig 16 Smart pixel array application

into the existing digital electronic infrastructure, it is necessary that a compact and
durable optical system be designed and developed that is compatible with current
computer packaging. This implies the following OHM requirements.

1) Support a smart pixel density of 1000 smart pixels/cm2

2) Fit in a standard electrical rack: - 1” spacing between SPA’s and a 1-in3

optomechanical volume per SPA pair.

3) Support a SPA size of 1 cm x 1 cm.

4) For modulator-based systems, keep the loss between the optical power supply and
the detector less than 10 dB, and for the source-based systems, keep the loss between
the VCSEL’s and the detector less than 3 dB. Smart pixel application space.

5) Use only elements which are potentially cost-effective

6) Minimize the number of critical alignments.

7) Maintain optomechanical stability over a 100’ temper

8) Modular OHM’S that can operate in a “plug and play”

 The push to decrease optical system size has dramatically changed the
methods for system packaging. Previous freespace digital optics systems typically
used nearly all 32 ft2 of an optical table [4]. The large system size was due to the
large size of the off-the-shelf optical components and their mounting mechanisms.
With the shrinking of optical components and the availability of high-power laser
diodes, new optical system packaging methods are evolving which are compatible
with the physical conventions of current electronic systems. The current
optomechanical approaches include: slotted baseplates [4], barrels , glued optics , and,
finally, active alignment.

CONCLUSION

This paper has described the major SPA technologies that are currently
evolving toward manufacturable device two-beam transimpedance smart-pixel the
modulator-based FET-SEED, Hybrid CMOS-SEED, and LCOS smart pixels and the
source-based Hybrid optical receivers made from hybrid GaAs MQW modulators
bonded to VCSEL/MSM, ELO, flip-chip-bonded VCSELIMSM, and monolithic
MSMNESFETNCSEL smart pixels.