How to write FSM is verilog?

there r mainly 4 ways 2 write fsm code

1) using 1 process where all input decoder, present state, and output decoder r
combine in one process.
2) using 2 process where all comb ckt and sequential ckt separated in different process
3) using 2 process where input decoder and persent state r combine and output
decoder seperated in other process
4) using 3 process where all three, input decoder, present state and output decoder r
separated in 3 process. 

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(Also refer to Tutorial section for more)

Verilog interview Questions

21)What is difference between freeze deposit and force? 

$deposit(variable, value);
This system task sets a Verilog register or net to the specified value. variable is the
register or net to be changed; value is the new value for the register or net. The value
remains until there is a subsequent driver transaction or another $deposit task for the
same register or net. This system task operates identically to the ModelSim
force -deposit command.

The force command has -freeze, -drive, and -deposit options. When none of these is
specified, then -freeze is assumed for unresolved signals and -drive is assumed for
resolved
signals. This is designed to provide compatibility with force files. But if you prefer
-freeze
as the default for both resolved and unresolved signals. 

Verilog interview Questions

22)Will case infer priority register if yes how give an example? 

 
yes case can infer priority register depending on coding style
reg r; 
// Priority encoded mux, 
always @ (a or b or c or select2) 
begin 
r = c; 
case (select2) 
2'b00: r = a; 
2'b01: r = b; 
endcase 
end 

Verilog interview Questions

23)Casex,z difference,which is preferable,why? 

CASEZ : 
Special version of the case statement which uses a Z logic value to represent don't-
care bits. CASEX : 
Special version of the case statement which uses Z or X logic values to represent
don't-care bits. 

CASEZ should be used for case statements with wildcard don’t cares, otherwise use
of CASE is required; CASEX should never be used. 
This is because: 
Don’t cares are not allowed in the "case" statement. Therefore casex or casez are
required. Casex will automatically match any x or z with anything in the case
statement. Casez will only match z’s -- x’s require an absolute match. 

Verilog interview Questions

24)Given the following Verilog code, what value of "a" is displayed? 

always @(clk) begin

a = 0;
a <= 1;
$display(a);
end

This is a tricky one! Verilog scheduling semantics basically imply a

four-level deep queue for the current simulation time:
1: Active Events (blocking statements)
2: Inactive Events (#0 delays, etc)
3: Non-Blocking Assign Updates (non-blocking statements)
4: Monitor Events ($display, $monitor, etc).
Since the "a = 0" is an active event, it is scheduled into the 1st "queue".
The "a <= 1" is a non-blocking event, so it's placed into the 3rd queue.
Finally, the display statement is placed into the 4th queue. Only events in the active
queue are completed this sim cycle, so the "a = 0" happens, and then the display
shows a = 0. If we were to look at the value of a in the next sim cycle, it would show
1. 

25) What is the difference between the following two lines of Verilog code?
#5 a = b;
a = #5 b;

#5 a = b; Wait five time units before doing the action for "a = b;". 
a = #5 b; The value of b is calculated and stored in an internal temp register,After five
time units, assign this stored value to a. 

26)What is the difference between: 

c = foo ? a : b;
and
if (foo) c = a;
else c = b;

The ? merges answers if the condition is "x", so for instance if foo = 1'bx, a = 'b10,
and b = 'b11, you'd get c = 'b1x. On the other hand, if treats Xs or Zs as FALSE, so
you'd always get c = b. 

27)What are Intertial and Transport Delays ?? 

28)What does `timescale 1 ns/ 1 ps signify in a verilog code? 

'timescale directive is a compiler directive.It is used to measure simulation time or

delay time. Usage : `timescale / reference_time_unit : Specifies the unit of
measurement for times and delays. time_precision: specifies the precision to which
the delays are rounded off. 

29) What is the difference between === and == ? 

output of "==" can be 1, 0 or X.

output of "===" can only be 0 or 1.
When you are comparing 2 nos using "==" and if one/both the numbers have one or
more bits as "x" then the output would be "X" . But if use "===" outpout would be 0
or 1.
e.g A = 3'b1x0
B = 3'b10x
A == B will give X as output.
A === B will give 0 as output.
"==" is used for comparison of only 1's and 0's .It can't compare Xs. If any bit of the
input is X output will be X
"===" is used for comparison of X also.

30)How to generate sine wav using verilog coding style? 

A: The easiest and efficient way to generate sine wave is using CORDIC Algorithm. 

31) What is the difference between wire and reg? 

Net types: (wire,tri)Physical connection between structural elements. Value assigned

by a continuous assignment or a gate output. Register type: (reg, integer, time, real,
real time) represents abstract data storage element. Assigned values only within an
always statement or an initial statement. The main difference between wire and reg is
wire cannot hold (store) the value when there no connection between a and b like a-
>b, if there is no connection in a and b, wire loose value. But reg can hold the value
even if there in no connection. Default values:wire is Z,reg is x. 
32 )How do you implement the bi-directional ports in Verilog HDL?

module bidirec (oe, clk, inp, outp, bidir);

// Port Declaration
input oe;
input clk;
input [7:0] inp;
output [7:0] outp;
inout [7:0] bidir; 
reg [7:0] a;
reg [7:0] b;
assign bidir = oe ? a : 8'bZ ;
assign outp = b;
// Always Construct
always @ (posedge clk)
begin
b <= bidir;
a <= inp;
end
endmodule

34)what is verilog case (1) ? 

wire [3:0] x;
always @(...) begin
case (1'b1)
x[0]: SOMETHING1;
x[1]: SOMETHING2;
x[2]: SOMETHING3;
x[3]: SOMETHING4;
endcase
end
The case statement walks down the list of cases and executes the first one that
matches. So here, if the lowest 1-bit of x is bit 2, then something3 is the statement that
will get executed (or selected by the logic). 

35) Why is it that "if (2'b01 & 2'b10)..." doesn't run the true case? 

This is a popular coding error. You used the bit wise AND operator (&) where you
meant to use the logical AND operator (&&). 

36)What are Different types of Verilog Simulators ?

There are mainly two types of simulators available. 

Event Driven 
Cycle Based 

Event-based Simulator: 

This Digital Logic Simulation method sacrifices performance for rich functionality:
every active signal is calculated for every device it propagates through during a clock
cycle. Full Event-based simulators support 4-28 states; simulation of Behavioral HDL,
RTL HDL, gate, and transistor representations; full timing calculations for all devices;
and the full HDL standard. Event-based simulators are like a Swiss Army knife with
many different features but none are particularly fast. 

Cycle Based Simulator: 

This is a Digital Logic Simulation method that eliminates unnecessary calculations to

achieve huge performance gains in verifying Boolean logic: 

1.) Results are only examined at the end of every clock cycle; and 
2.) The digital logic is the only part of the design simulated (no timing calculations).
By limiting the calculations, Cycle based Simulators can provide huge increases in
performance over conventional Event-based simulators. 
Cycle based simulators are more like a high speed electric carving knife in
comparison because they focus on a subset of the biggest problem: logic verification. 
Cycle based simulators are almost invariably used along with Static Timing verifier to
compensate for the lost timing information coverage. 

37)What is Constrained-Random Verification ? 

Introduction

As ASIC and system-on-chip (SoC) designs continue to increase in size and

complexity, there is an equal or greater increase in the size of the verification effort
required to achieve functional coverage goals. This has created a trend in RTL
verification techniques to employ constrained-random verification, which shifts the
emphasis from hand-authored tests to utilization of compute resources. With the
corresponding emergence of faster, more complex bus standards to handle the massive
volume of data traffic there has also been a renewed significance for verification IP to
speed the time taken to develop advanced testbench environments that include
randomization of bus traffic.

Directed-Test Methodology

Building a directed verification environment with a comprehensive set of directed

tests is extremely time-consuming and difficult. Since directed tests only cover
conditions that have been anticipated by the verification team, they do a poor job of
covering corner cases. This can lead to costly re-spins or, worse still, missed market
windows.

Traditionally verification IP works in a directed-test environment by acting on

specific testbench commands such as read, write or burst to generate transactions for
whichever protocol is being tested. This directed traffic is used to verify that an
interface behaves as expected in response to valid transactions and error conditions.
The drawback is that, in this directed methodology, the task of writing the command
code and checking the responses across the full breadth of a protocol is an
overwhelming task. The verification team frequently runs out of time before a
mandated tape-out date, leading to poorly tested interfaces. However, the bigger issue
is that directed tests only test for predicted behavior and it is typically the unforeseen
that trips up design teams and leads to extremely costly bugs found in silicon.

Constrained-Random Verification Methodology

The advent of constrained-random verification gives verification engineers an
effective method to achieve coverage goals faster and also help find corner-case
problems. It shifts the emphasis from writing an enormous number of directed tests to
writing a smaller set of constrained-random scenarios that let the compute resources
do the work. Coverage goals are achieved not by the sheer weight of manual labor
required to hand-write directed tests but by the number of processors that can be
utilized to run random seeds. This significantly reduces the time required to achieve
the coverage goals.

Scoreboards are used to verify that data has successfully reached its destination, while
monitors snoop the interfaces to provide coverage information. New or revised
constraints focus verification on the uncovered parts of the design under test. As
verification progresses, the simulation tool identifies the best seeds, which are then
retained as regression tests to create a set of scenarios, constraints, and seeds that
provide high coverage of the design.