Piranti Terprogram - FSM

Created by AI
EEPIS
Piranti Terprogram
Perancangan Finite State Machine
(Pertemuan ke- 7)
1
Created by AI
EEPIS
Perancangan Finite State Machine (FSM)

1. Tujuan
• Mampu merancang dan mendemonstrasikan rangkaian digital elektronik dengan

menggunakan metode Finite State Machine pada FPGA serta melaporkan hasil
percobaannya
2. Peralatan yang dibutuhkan

• Komputer yang sudah terinstall software XILINX ISE Design Suite 14.7 dan
Adept Digilent
• BASYS 2 FPGA board
•
3. Langkah percobaan
1. Buka software ISE Design Suite 14.7
2. Klik pada tombol “New Project” untuk membuat project baru.
2
Created by AI
EEPIS
3. Beri nama project dan letakkan project pada folder yang ditentukan serta Top-level
source type adalah HDL
4. Setting jenis FPGA dan konfigurasi lainnya sesuai gambar dibawah, dimana
Family: Spartan-3E
Device: XC3S100E atau XC3S250E, tergantung jenis chip board anda
Package: CP132
Speed: -4
Preferred Language: VHDL
3
Created by AI
EEPIS
5. Klik Next dan anda akan mendapat konfirmasi konfigurasi yang telah dilakukan.
Selanjutnya klik Finish
6. Selanjutnya buat file VHDL dengan cara klik kanan pada nama project, selanjutnya
pilih New Source
7. Implementasikan rancangan dan VHDL berikut, buat VHDL yang lengkap

selanjutnya simulasikan.
8. VHDL FSM
-----------------------------------------------------
-- VHDL FSM (Finite State Machine) modeling
-- by WZ
--
-- FSM model consists of two concurrent processes
-- state_reg and comb_logic
-- we use case statement to describe the state
4
Created by AI
EEPIS
-- transistion. All the inputs and signals are

-- put into the process sensitive list.
-----------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
-----------------------------------------------------
entity seq_design is
port( a: in std_logic;
clock: in std_logic;
reset: in std_logic;
x: out std_logic
);
end seq_design;
-----------------------------------------------------
architecture FSM of seq_design is
-- define the states of FSM model
type state_type is (S0, S1, S2, S3);

signal next_state, current_state: state_type;
begin
-- cocurrent process#1: state registers

state_reg: process(clock, reset)
begin
if (reset='1') then
current_state <= S0;
elsif (clock'event and clock='1') then
current_state <= next_state;
end if;
end process;
-- cocurrent process#2: combinational logic

comb_logic: process(current_state, a)
begin
-- use case statement to show the

-- state transistion
case current_state is
when S0 => x <= '0';

if a='0' then
next_state <= S0;
elsif a ='1' then
next_state <= S1;
end if;
when S1 => x <= '0';

if a='0' then
next_state <= S1;
elsif a='1' then
next_state <= S2;
5
Created by AI
EEPIS
end if;
when S2 => x <= '0';

if a='0' then
next_state <= S2;
elsif a='1' then
next_state <= S3;
end if;
when S3 => x <= '1';

if a='0' then
next_state <= S3;
elsif a='1' then
next_state <= S0;
end if;
when others =>

x <= '0';
next_state <= S0;
end case;
end process;
end FSM;
-----------------------------------------------------
9. VHDL FSM Test Bench
-----------------------------------------------------------------
-- test bench for FSM (ESD book figure 2.7)
-- by WZ
-----------------------------------------------------------------
library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
entity fsm_tb is -- entity declaration

end fsm_tb;
-----------------------------------------------------------------
architecture TB of fsm_tb is
signal T_a: std_logic;

signal T_clock: std_logic;
signal T_reset: std_logic;
signal T_x: std_logic;
component seq_design
port( a: in std_logic;
clock: in std_logic;
reset: in std_logic;
x: out std_logic
);
6
Created by AI
EEPIS
end component;
begin
U_fsm: seq_design port map(T_a, T_clock, T_reset, T_x);
process
begin
T_clock <= '1'; -- clock cycle 10 ns
wait for 5 ns;
T_clock <= '0';
wait for 5 ns;
end process;
process
variable err_cnt: integer :=0;
begin
-- case 1
T_reset <= '1';
wait for 20 ns;
assert (T_x='0') report "Failed Case 1" severity error;
if (T_x/='0') then
err_cnt:=err_cnt+1;
end if;
-- case 2
T_reset <= '0';
T_a <= '0';
wait for 20 ns;
if (T_x/='0') then
err_cnt:=err_cnt+1;
end if;
-- case 3
wait for 30 ns;
T_a <= '1';
wait for 35 ns;
if (T_x/='1') then
err_cnt:=err_cnt+1;
end if;
-- case 4
wait for 70 ns;
T_reset <= '1';
wait for 10 ns;
if (T_x/='0') then
err_cnt:=err_cnt+1;
end if;
-- summary of all the tests

if (err_cnt=0) then
assert false
report "Testbench of FSM completely successfully!"
severity note;
else
7
Created by AI
EEPIS
assert true
report "Something wrong, Check again pls!"
severity error;
end if;
wait;
end process;
end TB;
----------------------------------------------------------------------
configuration CFG_TB of fsm_TB is
for TB
end for;
end CFG_TB;
-----------------------------------------------------------------------
10. Simulasikan dan Implementasikan pada module FPGA board

Piranti Terprogram - FSM

Uploaded by

Copyright:

Available Formats

Piranti Terprogram - FSM

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Piranti Terprogram - FSM

Uploaded by

Copyright:

Available Formats

Created by AI

Perancangan Finite State Machine (FSM)

• Mampu merancang dan mendemonstrasikan rangkaian digital elektronik dengan

2. Peralatan yang dibutuhkan

1. Buka software ISE Design Suite 14.7

2. Klik pada tombol “New Project” untuk membuat project baru.

Device: XC3S100E atau XC3S250E, tergantung jenis chip board anda

Preferred Language: VHDL

7. Implementasikan rancangan dan VHDL berikut, buat VHDL yang lengkap

-- transistion. All the inputs and signals are

architecture FSM of seq_design is

-- define the states of FSM model

type state_type is (S0, S1, S2, S3);

-- cocurrent process#1: state registers

-- cocurrent process#2: combinational logic

-- use case statement to show the

when S0 => x <= '0';

when S1 => x <= '0';

when S2 => x <= '0';

when S3 => x <= '1';

when others =>

9. VHDL FSM Test Bench

entity fsm_tb is -- entity declaration

signal T_a: std_logic;

U_fsm: seq_design port map(T_a, T_clock, T_reset, T_x);

variable err_cnt: integer :=0;

-- summary of all the tests

10. Simulasikan dan Implementasikan pada module FPGA board

You might also like