VLSI Design and Testing
VLSI Design and Testing
2. To expose the students, the basics of testing techniques for VLSI circuits and Test
Economics.
Course Content:
Unit - I (9 hours)
Introduction, Overview of VLSI Design Flow,High Level Synthesis (HLS) Overview
,Scheduling in High Level Synthesis (HLS),Resource Sharing and Binding in HLS
Unit - II (9 hours)
Logic Synthesis, Physical Design, Intoduction to formal methods for design verification,
Temporal Logic: Introduction and Basic Operations on Temporal Logic
Unit - IV (9 hours)
Binary Decision Diagram: Introduction and Construction, Ordered Binary Decision
Diagram (OBDD), Operation on OBDD, OBDD for state Transition systems
Unit - V (9 hours)
Symbolic model checking, Introduction to Digital VLSI Testing, Functional and
Structural Testing, Fault Equivalence, Fault Simulation
Unit – VI (9 hours)
Testability Measures (SCOAP) , Introduction to Automatic Test Pattern
generation(ATPG) and ATPG Algebras, D-Algorithm, ATPG for synchronous sequential
circuits, Scan Chain based Sequential circuit testing, Built in Self Test (BIST)
1
Rajiv Gandhi University of Knowledge Technologies, NUZVID
Department of Electronics & Communications Engineering
TEXT BOOKS:
Assessment Method
Assessment Weekly tests Monthly tests End Semester Test Total
Tool
Weightage (%) 10% 30% 60% 100%