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T 1/8 0.125ms, 4+2+2+4 12 12 0.125 1.5ms

The document discusses interrupt handling on an 8086-based microcomputer. It includes questions about interrupt acknowledge cycle times, interrupt vector tables, reset subroutines, and initializing memory blocks.

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omar taradeh
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65 views1 page

T 1/8 0.125ms, 4+2+2+4 12 12 0.125 1.5ms

The document discusses interrupt handling on an 8086-based microcomputer. It includes questions about interrupt acknowledge cycle times, interrupt vector tables, reset subroutines, and initializing memory blocks.

Uploaded by

omar taradeh
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Omar Taradeh 161022

1) If an 8086-based microcomputer is running at 8MHz with two wait states, how long does it take to
perform the interrupt-acknowledge bus cycle sequence?

T = 1/8 = 0.125ms ,4+2+2+4=12


12 *0.125 = 1.5ms
2)  If the instruction INT 60H is to pass control to a subroutine address FF400H in the code segment
starting at address FF000H, what vector should be loaded into the interrupt vector table? 

Cs =0FF00H

and IP = 0400H

3) At what address would the vector for the instruction INT 60H be stored in memory? 

CS60H :Location 182H ,IP60H : Location 180H.

4)  What is the address from where the first instruction is fetched by the microprocessor after reset has
been applied?

the address: FFFF0H

5) Write a reset subroutine that initializes the block of memory locations from address 0F000H to
0F0AAH  to 00H. The initialization routine is at address 01000H.  

RESET: MOV AX,0

MOV DS,AX

MOV CX, ABH

MOV DI, 0F00H

NXT: MOV[DI], 0

INC DI

DEC CX

JNZ NXT

RET

Q6)

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