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Daoud 2006

1) The document describes the design and optimization of a folded cascode operational transconductance amplifier (OTA) for wideband applications. 2) A folded cascode OTA topology is introduced that increases load resistance and gain over traditional designs through cascoding. 3) The design of the folded cascode OTA is presented, along with transistor sizing methodology, to achieve high gain and bandwidth for baseband RF circuit applications. Simulation results show the OTA achieves 85dB gain and 332MHz gain bandwidth product.

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0% found this document useful (0 votes)
40 views4 pages

Daoud 2006

1) The document describes the design and optimization of a folded cascode operational transconductance amplifier (OTA) for wideband applications. 2) A folded cascode OTA topology is introduced that increases load resistance and gain over traditional designs through cascoding. 3) The design of the folded cascode OTA is presented, along with transistor sizing methodology, to achieve high gain and bandwidth for baseband RF circuit applications. Simulation results show the OTA achieves 85dB gain and 332MHz gain bandwidth product.

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© © All Rights Reserved
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Folded Cascode OTA Design for Wide Band

Applications
Houda Daoud, Samir Ben Salem, Sonia Zouari, Mourad Loulou

Information technologies and electronic laboratory, LETI


National engineers school of Sfax, Tunisia
[email protected], [email protected], [email protected], [email protected]

Abstract—This paper deals with design and optimization of a In order to achieve high gain, the differential telescopic
folded cascode operational transconductance amplifier. First, a topologies can be used. This topology cascodes both the
detailed description of an optimum OTA topology is done in differential pair transistors and current mirror to increase
order to optimize MOS transistor sizing. Second, the design of load resistance (Fig. 1) [1].
folded cascode OTA, which works for frequencies that lead to
The telescopic architecture is a better candidate for a low
a base band circuit design for RF application, is based on
transistor sizing methodology. Third, folded cascode OTAs power consumption and low noise OTA.
generally find several applications that are well developed. V dd
Simulation results are performed using SPICE software and
BSIM3V3 model for CMOS 0.35µm process, show that the
M M8
designed folded cascode OTA has a 85dB DC gain and 7

provides a gain bandwidth product of around 332MHz.


I bias
Keywords—CMOS IC design, optimization, folded M M
cascode OTA, gm/ID methodology, base band RF application. 5 6
Vout
CL
I. INTRODUCTION
M
Microelectronic development since these 30 last years is 3 M 4
V1
truly spectacular. This success results mainly of a
knowledge-make and a technological master of a V+ M1 M 2 V−
fundamental element: the silicon. The MOS transistor is the
principle actor and the vector of this technological
development. It is the base of integrated circuit design with M10 M 9

large scale of integration. With the passing of years, the


complexity of integrated circuit has continuously increased, V ss
mainly thanks to the rising performance of MOS transistors
new generations. The reduction component sizing is the
engine of this race to the performance. Our goal was to Figure 1. Telescopic OTA
design a folded cascode OTA using CMOS process in order Although, telescopic OTA has a limited input and output
to use it in the design of a wide band Sigma Delta analog- swing. In order to alleviate some of the drawbacks of
to-digital converter. Moreover, we validate the design by telescopic operational amplifier, a folded cascode OTA
some applications. based on Wilson mirror can be used.
This paper is organized as follows. An optimum
architecture of the folded cascode OTA was introduced in II.I. Basic configuration CMOS folded cascode OTA
section II and its function was analyzed to extract the circuit The folded cascode OTA is shown in Fig. 2 [2 - 4]. The
performances. Section III describes an approach for name “folded cascode” comes from folding down n-channel
designing this OTA, clarifies specific design issues. Section cascode active loads of a diff-pair and changing the Mosfets
IV presents some applications while section V provides to p-channels. This OTA, like all OTAs, has good PSRR
concluding remarks. compared to the operational amplifier. To understand the
operation of the folded cascode OTA, this last has a
II. OPTIMUM TOPOLOGY OTA ARCHITECTURE differential stage consisting of PMOS transistors M9 and
Several fundamental issues exist when selecting an optimal M10 intend to charge Wilson mirror. Mosfets M11 and M12
architecture for the operational transconductance amplifier. provide the DC bias voltages to M5-M6-M7-M8 transistors.
This choice aimed both at large gain and large bandwidth The open-loop voltage gain is given by:
performances.

  


g m9 g m4 g m6 (1) CMOS technology under consideration (0.35µm of AMS) is
Av = exploited in order to apply the method quoted previously
2 2 2 
 g and compute the design parameters from the specifications
ID m4 λ N + g m6 λ P 
  as a result of top-down synthesis flow.
Where gm9, gm4 and gm6 are respectively the
transconductances of transistors M9, M4 and M6. ID is the g m9 I D
bias current flowing in Mosfets M4, M6, and M9. Like, CL is w u → ↔
I D  W 
the capacitance at the output node.  
 L  9
λN and λP are the parameters related to channel length
modulation respectively for NMOS and PMOS devices. g m4 I D
A v → ↔
Taking the complementarity between the transistors M4 and I D  W 
M6 into account:  
 L  4
gm 4 = gm6 (2)

The gain expression becomes: Figure 3. Design plan


g m9 g m4 1 (3) III.2. OTA design
Av =
ID ID (λ N 2 + λP 2 ) We subjected the circuit of fig 2 to specifications schedule
presented by table 1.
The unity gain frequency of the OTA is given by the After applying the design strategy clarified previously, we
expression: obtained the parameters computed and summarized in table
g m9 I D (4) 2.
wu =
ID C L
Table 1. Specifications
Vdd Specifications Values
Av (dB) 82
M1 M2 fT (MHz) 340
I bias CL (pF) 0.1
I bias M3 M4 ID (µA) 30
C
Vout L ± Vdd (V) ±2
M5 Channel length (µm) 1
M9
M 6
M 10
M 11 Table 2. Design parameters
V +
V − Parameters Values
gm 9,10 /ID (V-1) 8
M7 M8 ID/(W/L)9,10 (µA) 0.86
M 12
-1
gm 4 /ID (V ) 6
Vss ID/(W/L)4 (µA) 1.65

Figure 2. Folded cascode OTA W 9,10 (µm) 35


W 1, 2, 3,4 (µm) 18
III. FOLDED CASCODE OTA DESIGN
W 5, 6, 7, 8, 11,12 (µm) 6
METHODOLOGY
To show folded cascode OTA performances, this paper is
interested in OTA design carrying. This design follows a The designed folded cascode OTA was biased at 2V
synthesis procedure based on the gm/ID methodology [5]. power supply voltage using CMOS technology of 0.35 µm
of AMS with the BSIM3V3 MOSFET model.
III.1. Sizing algorithm The circuit denotes an offset voltage of 1mV, a Slew Rate
We present a top-down synthesis methodology for CMOS of 104V/µs, an input common-mode range of ± 1.9 V and an
OTA architectures illustrated by a design plan (Fig. 3) [6]. output common-mode range between 1.9V and -1.4V.
In fact, this last starts by fixing the specifications to Moreover, our device is able to achieve a higher DC gain of
optimize for example: gain and transition frequency in order 85dB and a wide bandwidth of 332 MHz with phase margin
to determine the unknowns that are MOS devices sizes. of 46 degrees (Fig.4). Its transconductance is about of
The universal gm/ID as a function of I D W L 0.24mS (Fig .5).
characteristic of the NMOS and PMOS transistors of the
Table 3. Folded cascode OTA specifications

Specifications Folded cascode Folded cascode


(CLoad = 0.1pF) OTA OTA improved
Gain DC 85 dB 85 dB
GBW 332 MHz 230 MHz
Phase margin 46 deg 46 deg
CMRR 164 dB 164 dB
PSRR p, n 85 dB 85 dB
Figure 4. Phase/magnitude response of the OTA Offset voltage 1 mV 0.1 mV
Output swing [-1.9 V; 1.4 V] [-1.9 V; 1.85 V]
Input swing ±1.9 V ±1.9 V
Slew Rate ±104 V/µs ±100 V/µs
Supply voltage 2V 2V
Input noise 1.7 µV/ H 1.7 µV/ H
specter density
Output noise 35 mV/ H 35 mV/ H
specter density
Figure 5. Transconductance curve
III.3. Improved OTA design IV. APPLICATIONS
Since the folded cascode OTA based on Wilson mirror has a To demonstrate the feasibility and the performance of
limited output swing, we attempt to solve this problem. So, folded cascode OTA, we simulated several applications. We
we propose to improve the current mirror (Fig.6). For the have treated current mode and voltage mode filters.
folded cascode OTA using a Wilson mirror, the maximum Recently, analog filters design using Gm-C integrators has
output voltage is set lower than: Vdd+VT+2Vds,sat, so, we acquired a great popularity. Tranconductance cells are
use cascode mirror in order to restore this fall to +2Vds,sat. relatively simple circuits which allow to operate for high
The improved circuit yield to specifications schedule frequencies.
presented by table 1 follows the same design strategy The ideal OTA has the properties: the differential input-
explained previously; we obtain the same transistors sizes of voltage is bypassed directly to the conductance gm, where
the last circuit. the output current becomes iout = gm (Vin+-Vin-). Let’s
Vdd consider the OTA-C filter circuit shown in figure 7, which
works in current mode. In figure 8, it is shown the
M1 M2
equivalent circuit of the OTA-C filter.
I bias _

gm _

I bias M3 M4 gm
C
Vout L Iin
+
+ I out
C
Ibias
Ibias
M5
M9
M 6
M 10
M 11
+ −
V V Figure 7. OTA-C filter working in current mode

M7 M8
M 12

Vss I in gm gm I out
C

Figure 6. Folded cascode OTA improved


The simulated circuit has a 85dB DC gain and a transition
frequency of 230MHz. The degradation of the bandwidth Figure 8. Equivalent circuit for the OTA-C
was due to the first pole weakening of the OTA without
increasing the DC gain. The computation of the symbolic transfer function has the
Furthermore, the circuit illustrates an offset voltage of following relation ship:
0.1mV, an output and input common-mode range near of I out 1 (5)
=
±Vdd, and a Slew Rate of 100V/µs. The common-mode and I in  1 
1 + p  C 
the power supply rejections took the same values found for  g m 
the circuit based on Wilson mirror. Folded cascode OTA
specifications are listed in table 3.
From the last equation, we represent the transfer As one sees, both transfer functions in voltage and
characteristic for the filter, using MAPLE tool. current mode are similar, so, MAPLE provides the same
The low pass filter approximated by eq 5 has a cut frequency behavior for each kind of filter.
frequency of around 140MHz; as shown in figure 9. In For the same target mentioned previously, the cut frequency
order to check the filter transfer characteristic, as well as its shown in figure 13 is 130MHz. Simulation results lead us to
cut frequency, we simulate the circuit working in current conclude about the dynamic performances abasement.
mode on PSPICE simulator. This is depicted in figure 10 for
a cut frequency of 110MHz.

Figure 13. Magnitude response of the filter


Figure 9. Characteristic of the filter
V. CONCLUSIONS
This contribution presents an efficient methodology for
OTA design, so, the goal to reach high gain and large
bandwidth has been fulfilled. Therefore, it has been shown
that folded cascode OTA based on Wilson mirror points out
a wide transition frequency escorted of output swing
limitation. We mention here OTA dynamic performances
abasement due to the use of parameters with different
values compared to those forecasted since OTA design.
Future work would involve the search of low-
Figure 10. Magnitude response of the filter consumption and low-supply voltage structure, an update to
nano technology-process and Sigma Delta modulator design
Compared to figure 9, we obtained the same curve; application
nevertheless, the two frequencies are different. Likewise,
the OTA-C filter working in voltage mode (Fig. 11) REFERENCES
presents the circuit equivalent in figure 12.
[1] M. Hershenson, S.Boyd, and T. Lee. "Optimal design of a CMOS op-
amp via geometric programming". Stanford.edu/people/boyd
_
[2] T. C. Choi, R. T. Kaneshiro, R. Broderson, and P.R. Gray, “High-
gm _
Vout
Frequency CMOS Switched Capacitor Filters for Communication
+ gm Applications,” IEEE Journal of Solid State Circuits,” Vol. SC-18, pp.
Vin +
_
+ December 1983.
C
Ibias [3] R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H.Huijsing, “A
Ibias Compact Power efficient 3 V CMOS Rail-to-Rail Input/Output Operational
Amplifier for VLSI cell Libraries,” IEEE Journal of Solid State Circuits,
Vol. 29,pp. December 1988.
Figure 11. OTA-C filter working in voltage mode [4] M. Banu, J. M. Khoury, and Y. Tsividis, “Fully Differential
Operational Amplifier with Accurate Output Balancing,” IEEE Journal of
Solid State circuits, Vol. 23, No. 6, pp. December 1990.
[5] F. Silveira, D. Flandre et P.G.A. Jespers, "A gm/ID based methodology
Vout
for the design of CMOS analog circuits and its application to the synthesis
gm gm
of a SOI micropower OTA", IEEE J. of Solid State Circuits, vol. 31, n. 9,
Vin C sept. 1996.
+ [6] J.-P. Eggermont, et al., "Design of SOI CMOS operational amplifiers

for applications up to 300°C", IEEE Journal of Solid-State Circuits, vol.31,
pp. 179-186, 1996.

Figure 12. Equivalent circuit for the OTA-C


Its transfer function is given by:
V out
=
1 (6)
V in  1 
1 + p  C 
 g m 

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