CHAPTER 11

Exercises

E11.1 (a) vGS  1 V and vDS  5 V: Because we have vGS < Vto, the FET is in
cutoff.

(b) vGS  3 V and vDS  0.5 V: Because vGS > Vto and vGD  vGS  vDS  2.5 >
Vto, the FET is in the triode region.

(c) vGS  3 V and vDS  6 V: Because vGS > Vto and vGD  vGS  vDS  3 V <
Vto, the FET is in the saturation region.

(d) vGS  5 V and vDS  6 V: Because vGS > Vto and vGD  vGS  vDS  1 V
which is less than Vto, the FET is in the saturation region.

E11.2 First we notice that for v GS  0 or 1 V, the transistor is in cutoff, and the
drain current is zero. Next we compute the drain current in the
saturation region for each value of vGS:
K  21 KP (W / L)  21 (50  10 6 )(80 / 2)  1 mA/V 2
iD  K (v GS Vto ) 2
The boundary between the triode and saturation regions occurs at
v DS  v GS Vto
v GS (V) iD (mA) v DS at boundary
2 1 1
3 4 2
4 9 3

In saturation, iD is constant, and in the triode region the characteristics

are parabolas passing through the origin. The apex of the parabolas are
on the boundary between the triode and saturation regions. The plots
are shown in Figure 11.7 in the book.

E11.3 First we notice that for v GS  0 or  1 V, the transistor is in cutoff, and

the drain current is zero. Next we compute the drain current in the
saturation region for each value of vGS:

1
 K  21 KP (W / L)  21 (25  10 6 )(200 / 2)  1.25 mA/V 2
iD  K (v GS Vto ) 2

The boundary between the triode and saturation regions occurs at

v DS  v GS Vto .
v GS (V) iD (mA) v DS at boundary
2 1.25 1
3 5 2
4 11.25 3

In saturation, iD is constant, and in the triode region the characteristics

are parabolas passing through the origin. The apex of the parabolas are
on the boundary between the triode and saturation regions. The plots
are shown in Figure 11.9 in the book.

E11.4 We have

v GS (t )  v in (t ) VGG  sin(2000πt )  3

Thus we have VGS max  4 V, VGSQ  3 V, and VGS min  2 V. The

characteristics and the load line are:

2
 For vin  +1 we have vGS  4 and the instantaneous operating point is A.
Similarly for vin  1 we have vGS  2 V and the instantaneous operating
point is at B. We find VDSQ  11 V, VDS min  6 V, VDS max  14 V.

E11.5 First, we compute

R2
VG  VDD  7V
R1  R2
and K  21 KP (W / L)  21 (50  10 6 )(200 / 10)  0.5 mA/V 2
As in Example 11.2, we need to solve:
 1  V
 2Vto VGSQ  Vto   G  0
2
VGSQ
2
 
 RS K  RS K

Substituting values, we have

VGSQ
2
VGSQ  6  0

The roots are VGSQ  2 V and 3 V. The correct root is VGSQ  3 V which
yields IDQ  K(VGSQ  Vto)2  2 mA. Finally, we have VDSQ  VDD  RSIDQ 
16 V.

E11.6 First, we replace the gate bias circuit with its equivalent circuit:

Then we can write the following equations:

K  21 KP (W / L)  21 (25  10 6 )(400 / 10)  0.5 mA/V 2

VGG  11.5 VGSQ  Rs I DQ  20 (1)

3
 I DQ  K (VGSQ Vto ) 2 (2)

Using Equation (2) to substitute into Equation (1), substituting values, and
rearranging, we have VGSQ
2
 16  0 . The roots of this equation are
VGSQ  4 V. However VGSQ  4 V is the correct root for a PMOS
transistor. Thus we have
I DQ  4.5 mA
and
VDSQ  Rs I DQ  RD I DQ  20  11 V.

E11.7 From Figure 11.21 at an operating point defined by VGSQ  2.5 V and VDSQ
 6 V, we estimate

gm 
iD

4.4  1.1 mA  3.3 mS
v GS 1V

1 rd 
iD

2.9  2.3 mA  0.05  10  3
v GS 14 - 2 V
Taking the reciprocal, we find rd  20 kΩ.

4
 iD
E11.8 gm 
v GS


v GS
K v GS Vto 
2

 2K V GSQ Vto 
Q  po int Q  po int

1
E11.9 RL   RD  4.7 kΩ
1 rd  1 RD  1 RL

Avoc   gm RL  1.77 mS  4.7 k   8.32

E11.10 For simplicity we treat rd as an open circuit and let RL  RD RL.

v in  v gs  Rs gmv gs

v o  RL gmv gs

vo  RL gm
Av  
v in 1  RL gm

E11.11 RL  RD RL  3.197 kΩ

vo  RL gm  3.197 kΩ 1.77 mS

Av     0.979
v in 1  RL gm 1  2.7 kΩ 1.77 mS

E11.12 The equivalent circuit is shown in Figure 11.28 in the book from which we
can write

5
 vx vx v v
v in  0 v gs  v x ix    gmv gs  x  x  gmv x
RS rd RS rd
Solving, we have
vx 1
Ro  
ix 1 1
gm  
RS rd

E11.13 Refer to the small-signal equivalent circuit shown in Figure 11.30 in the
book. Let RL  RD RL .
v in  v gs

v o  RL gmv gs
Av  v o v in  RL gm
iin  v in Rs  gmv gs  v in Rs  gmv in

v in 1
Rin  
iin gm  1 Rs

If we set v (t)  0, then we have vgs  0. Removing the load and looking
back into the amplifier, we see the resistance RD. Thus we have Ro  RD .

E11.14 See Figure 11.34 in the book.

E11.15 See Figure 11.35 in the book.

Problems

P11.3 K  21 KP (W / L)  0.25 mA/V 2

(a) Saturation because we have vGS  Vto and vDS  vGS  Vto.
iD  K(vGS  Vto)2  2.25 mA
(b) Triode because we have vDS < vGS  Vto and vGS  Vto.
iD  K[2(vGS  Vto)vDS  vDS2]  2 mA
(c) Cutoff because we have vGS  Vto. iD  0.

6
P11.4
iD
vGS  4

3V

2V
vDS

P11.11 In the saturation region, we have iD  K(vGS  Vto)2. Substituting values,

we obtain two equations:

0.2 mA  K(2  Vto)2

1.8 mA  K(3  Vto)2

Dividing each side of the second equation by the respective side of the
first, we obtain
3 Vto 2
9
2 Vto 2

Solving we determine that Vto  1.5 V. (We disregard the other root,
which is Vto  2.25 V, because the transistor would then be in cutoff with
vDS  2 V and would not give a current of 0.2 mA as required.) Then, using
either of the two equations, we find K  0.8 mA/V2.

P11.15 We have iD  K (v GS Vto ) 2 . Substituting values and solving, we obtain

v GS  2.5 and v GS  1.5 V. However, if v GS  1.5 , the PMOS transistor is
operating in cutoff. Thus, the correct answer is v GS  2.5 V.

P11.17 The load-line equation is VDD  RDiD + vDS, and the plots are:

7
 Notice that the load line rotates around the point (VDD, 0) as the
resistance changes.

P11.19 For VGG  0, the FET remains in cutoff so VDSmax  VDSQ VDSmin  20 V.
Thus, the output signal is zero, and the gain is zero. For amplification to
take place, the FET must be biased in the saturation or triode regions.

P11.21 For vin  +1 V we have vGS  4 V. For the FET to remain in saturation, we
must have VDSmin  3 V at which point the drain current is 4.5 mA. Thus,
the maximum value of RD is RDmax  (20  3)/4.5 mA  3.778 kΩ.

P11.27 For this circuit, we can write

VGSQ  15  IDQRS

Assuming operation in saturation, we have

IDQ  K(VGSQ  Vto)2

using the first equation to substitute into the second equation, we have
IDQ  K(15  IDQRS  Vto)2  0.25(14  3IDQ)2

where we have assumed that IDQ is in mA. Rearranging and substituting

values, we have
I DQ
2
 9.777IDQ + 21.777  0

8
 The correct root is the smaller one which is IDQ  3.432 mA. Then we
have VDSQ  30  RDIDQ  RSIDQ  16.27 V.

P11.28 We can write VDD  VDSQ  RS I DQ . Substituting values and solving, we

obtain RS  3 kΩ. Next we have K  21 KP (W / L)  2 mA/V 2 . Assuming
that the NMOS operates in saturation, we have
I DQ  K (VGSQ Vto ) 2

Substituting values and solving, we find VGSQ  0 V and VGSQ  2 V. The

correct root is VGSQ  2 V. (As a check we see that the device does
operate in saturation because we have VDSQ greater than VGSQ Vto . ) Then
we have VG  VGSQ  RS I DQ  8 V. However we also have
R2
VG  VDD
R1  R2

Substituting values and solving, we obtain R2  2 M.

P11.29 We can write VDD  20  2I DQ  8  2 in which IDQ is in mA. Solving, we

obtain IDQ  5 mA. Then, we find Rs  2 / I DQ  400 . Next, we have
K  21 KP (W / L)  0.75 mA/V 2 . Assuming that the NMOS operates in
saturation, we have
I DQ  K (VGSQ Vto ) 2
Substituting values and solving we find VGSQ  1.582 V and VGSQ  3.582
V. The correct root is VGSQ  3.582 V. (As a check, we see that the
device does operate in saturation because we have VDSQ  8 V, which is
greater than VGSQ Vto . ) Then, we have VG  VGSQ  2  5.582 V. However,
we also have
R2
VG  VDD
R1  R2
Substituting values and solving, we obtain R1  2.583M.

P11.34 We have VGSQ  VDSQ  VDD  RDIDQ. Then substituting IDQ  K(VGSQ 
Vto)2, we have

VGSQ  VDD  RDK(VGSQ  Vto)2

9
 Substituting values and rearranging, we have

VGSQ2 + 2VGSQ  39  0

Solving we determine that VGSQ  5.325 V and then we have IDQ  K(VGSQ
 Vto)2  4.675 mA.

P11.40 In the triode region, we have

iD  K[2(vGS  Vto)vDS  vDS2]

iD
gm   2Kv DS  2KVDSQ
v GS Q  point
Q  point

P11.41 In the triode region, we have

iD  K[2(vGS  Vto)vDS  vDS2]

iD
1 rd   2K v GS Vto  v DS  Q  point
v DS Q  point

1
rd 
2K (VGSQ Vto VDSQ )

R2 0. 3
P11.50 (a) VG  VDD  20  3V
R1  R2 1.7  0.3
VGSQ  VG  3 V
K  21 KP (W / L)  2.5 mA/V 2
IDQ  K (VGSQ Vto )2  10 mA
VDSQ  VDD  RD I DSQ  10 V
gm  2 KI DQ  0.01 S

1
(b) RL   500 Ω
1 / RD  1 / RL
Av   gm RL  5

10
 1
Rin   255 kΩ
1 / R1  1 / R2
Ro  RD  1 kΩ

P11.53 Referring to the circuit shown in Figure P11.53, we have

VGSQ  VDSQ IDQ  K(VGSQ  Vto)2 IDQ  (VDD  VDSQ)/RD

From the previous three equations we obtain:

1.1VDSQ
2
 5.6VDSQ  10.1  0

VDSQ  6.50 V and IDQ  6.135 mA

iD
gm 
v GS
 
 2K VGSQ Vto  3.5 mS
Q  point

vx vx 1
Ro     253 Ω
i x v x RD  gmv x 1 RD  gm

P11.56 We have
W  KP
K    400 μA/V2
L
  2
Assuming operation in saturation, we have
IDQ  K(VGSQ  Vto)2
Solving for VGSQ and evaluating we have
VGSQ  Vto + I DQ /K  3.236 V
R2
VG  VDD  10 V
R1  R2
VG  VGSQ + RSIDQ
Solving for RS and substituting values we have

11
 RS  (VG  VGSQ)/IDQ  3.382 kΩ

We have gm  2 KI DQ  1.789 mS

1
RL   1.257 kΩ
1 / RL  1 / RS  1 / rd

vo gm RL
Av    0.6922
v in 1  gm RL
v in
Rin   RG  R1 R2  666.7 k
iin
1
Ro   386.9 
1 1
gm  
Rs rd

Practice Test

T11.1 Drain characteristics are plots of iD versus vDS for various values of vGS.

First, we notice that for v GS  0.5 V, the transistor is in cutoff, and the
drain current is zero, because vGS is less than the threshold voltage Vto.
Thus, the drain characteristic for v GS  0.5 V lies on the horizontal axis.

Next, we compute the drain current in the saturation region for

v GS  4 V.
K  21 KP (W / L)  21 (80  10 6 )(100 / 4)  1 mA/V 2
iD  K (v GS Vto ) 2  K (4  1) 2  9 mA for v DS  v GS Vto  3 V
Thus, the characteristic is constant at 9 mA in the saturation region.

The transistor is in the triode region for v DS  v GS Vto  3 V, and the

drain current (in mA) is given by
iD  K[2(vGS  Vto)vDS  vDS2] = 6vDS  vDS2
with vDS in volts. This plots as a parabola that passes through the origin
and reaches its apex at iD  9 mA and v DS  3 V.

The drain characteristic for vGS  4 V is identical to that of Figure 11.11

in the book.

12
T11.2 We have v GS (t )  v in (t ) VGG  sin(2000t )  3 V. Thus, we have VGS max  4
V, VGSQ  3 V, and VGS min  2 V. Writing KVL around the drain circuit, we
have
VDD  RD iD  v DS
With voltages in volts, currents in mA, and resistances in k, this
becomes
10  2iD  v DS
which is the equation for the load line.

The characteristics and the load line are:

The results of the load-line analysis are VDSmin  1.0 V, VDSQ  2.05 V, and
VDSmax  8.2 V.

13
T11.3 Because the gate current is zero, we can apply the voltage division
principle to determine the voltage at the gate with respect to ground.
10 k
VG   12  3 V
(10  30) k
For the transistor, we have
K  21 KP (W / L)  21 (80  10 6 )(100 / 4)  1 mA/V 2
Because the drain voltage is 12 V, which is higher than the gate voltage,
we conclude that the transistor is operating in the saturation region.
Thus, we have
I DQ  K (VGSQ Vto ) 2
I DQ  (VGSQ  1) 2  0.5 mA
Solving, we have VGSQ  1.707 V or VGSQ  0.293 V. However, VGSQ must be
larger than Vto for current to flow, so the second root is extraneous.
Then, the voltage across Rs is VS  VG VGSQ  1.293 V. The current
through RS is IDQ. Thus, the required value is RS  1.293 / 0.5  2.586 k.

T11.4 This transistor is operating with constant vDS. Thus, we can determine gm
by dividing the peak ac drain current by the peak ac gate-to-source
voltage.
iD 0.05 mA
gm    2.5 mS
v GS v V 0.02 V
DS DSQ

The Q-point is VDSQ  5 V, VGSQ  2 V, and I DQ  0.5 mA.

T11.5 (a) A dc voltage source is replaced with a short circuit in the small-signal
equivalent. (b) A coupling capacitor becomes a short circuit. (c) A dc
current source is replaced with an open circuit, because even if an ac
voltage appears across it, the current through it is constant (i.e., zero ac
current flows through a dc current source).

14
T11.6 See Figure 11.31(b) and (c) in the text.

15