CSE 332L

Computer Organization and

Architecture Lab
MIPS ISA, Single Cycle &
Pipelined Datapath

Sajid Ahmed
MIPS INTRUCTIONS & DATAPATH
Instruction Set Architecture

3
MIPS ARCHITECTURE [Block-Diagram]
MIPS ARCHITECTURE [Datapath]
RISC vs. CISC
MULT 2:3, 5:2

CISC

vs.

RISC
LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
7
Different instructions types in MIPS

8
MIPS Instruction Formats

R-Type

I-Type

J-Type

9
Addressing Modes

10
Addressing Modes

11
Addressing Modes

12
Addressing Modes

13
Addressing Modes

15
Registers

• The MIPS ISA has 32 registers (x86 has 8 registers) –

Why not more? Why not less?

• Each register is 32-bit wide (modern 64-bit

architectures
have 64-bit wide registers)

• A 32-bit entity (4 bytes) is referred to as a word

• To make the code more readable, registers are

partitioned as $s0-$s7 (C/Java variables), $t0-$t9
(temporary variables)…
16
CSE332L - Computer Organization and Architecture
Target/Ultimate Goal == Datapath Design

Instruction ALU
Register File
Memory Data
Memory
Animating the Datapath

Instruction <- MEM[PC]

PC <- PC + 4
ADD

PC
ADDR
Memory
RD Instruction
 Datapath: R-Type Instruction

ALU control ALU operation

5 Read 3 Read 3
register 1 register 1
Read Read
Register 5 data 1 data 1
Read Read
numbers register 2 Zero Zero
Registers Data ALU Instruction register 2
ALU
5 Write result Registers ALU ALU
register Write result
Read
data 2 register
Write Read
Data data data 2
Write
RegWrite data

RegWrite
a. Registers b. ALU

Two elements used to implement Datapath

R-type instructions
Animating the Datapath

add rd, rs, rt

Instruction
op rs rt rd shamt funct R[rd] <- R[rs] + R[rt];

5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD

RD2
RegWrite
 Animating the Datapath:
R-type Instruction
Instruction add rd,rs,rt
32 16 5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD
M MemWrite
RD2 U ADDR MemtoReg
RegWrite X
Data
E Memory RD M
X U
16 32 ALUSrc X
T WD
N MemRead
D
Datapath: I-Type
Load/Store Instruction

3 ALU operation
Read
MemWrite register 1 MemWrite
Read
data 1
Read
Instruction register 2 Zero
Registers ALU ALU
Address Read Write Read
result Address
data 16 32 register data
Sign Read
Write data 2
extend Data
Write Data data
data memory memory
RegWrite Write
data
16 32
Sign MemRead
MemRead
extend

a. Data memory unit b. Sign-extension unit

Two additional elements used Datapath

To implement load/stores
 Animating the Datapath:
Load Instruction
Instruction lw rt,offset(rs)
32 16 5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD
M MemWrite
RD2 U ADDR MemtoReg
RegWrite X
Data
E Memory RD M
X U
16 32 ALUSrc X
T WD
N MemRead
D
 Animating the Datapath:
Store Instruction
Instruction sw rt,offset(rs)
32 16 5 5 5 Operation
3
RN1 RN2 WN
RD1
Register File ALU Zero
WD
M MemWrite
RD2 U ADDR MemtoReg
RegWrite X
Data
E Memory RD M
X U
16 32 ALUSrc X
T WD
N MemRead
D
 MIPS Datapath II: Single-Cycle
Separate adder as ALU operations and PC
increment occur in the same clock cycle
Add

Read Registers
ALU operation
register 1 3 MemWrite
PC Read
Read Read MemtoReg
address
register 2 data 1 ALUSrc Zero
Instruction ALU ALU
Write Read Address Read
register data 2 M result data
u M
Instruction Write x u
memory Data x
data memory
Write
RegWrite data
16 Sign 32 MemRead
extend
Separate instruction memory
as instruction and data read
occur in the same clock cycle
Adding instruction fetch
27
 PIPELINING
PIPELINE Datapath

28
 Pipelining
⚫ Start work ASAP!! Do not waste time!
6 PM 7 8 9 10 11 12 1 2 AM
Time
Task
order

Not pipelined
A

Assume 30 min. each task – wash, dry, fold, store – and that
separate tasks use separate hardware and so can be overlapped
6 PM 7 8 9 10 11 12 1 2 AM
Time

Task
order

A
Pipelined
B

D
 Review - Single-Cycle Datapath
“Steps”

ADD

4 ADD

PC <<2
Instruction I
ADDR RD
32 16 32
5 5 5
Instruction
Memory RN1 RN2 WN
RD1 Zero
Register File ALU
WD
RD2 M
U ADDR
X
Data
Memory RD M
E U
16 X 32 X
T WD
N
D

IF ID EX MEM WB
Instruction Fetch Instruction Decode Execute/ Address Calc. Memory Access Write Back
Pipelined Datapath – Key Idea
⚫ What happens if we break the execution into multiple cycles, but keep
the extra hardware?
⚫ Answer: We may be able to start executing a new instruction at each
clock cycle - pipelining
⚫ …but we shall need extra registers to hold data between cycles
– pipeline registers
 Pipelined Datapath
Pipeline registers wide enough to hold data coming in
ADD

4 ADD
64 bits 128 bits
PC <<2 97 bits 64 bits
Instruction I
ADDR RD
32 16 32
5 5 5
Instruction
Memory RN1 RN2 WN
RD1
Zero
Register File ALU
WD
RD2 M
U ADDR
X
Data
RD M
E Memory U
16 X 32 X
T WD
N
D

IF/ID ID/EX EX/MEM MEM/WB

 Pipelined Datapath
Pipeline registers wide enough to hold data coming in
ADD

4 ADD
64 bits 128 bits
PC <<2 97 bits 64 bits
Instruction I
ADDR RD
32 16 32
5 5 5
Instruction
Memory RN1 RN2 WN
RD1
Zero
Register File ALU
WD
RD2 M
U ADDR
X
Data
RD M
E Memory U
16 X 32 X
T WD
N
D

IF/ID ID/EX EX/MEM MEM/WB

Only data flowing right to left may cause hazard…, why?
 Bug in the Datapath

IF/ID ID/EX EX/MEM MEM/WB

ADD

4 ADD

PC <<2
Instruction I
ADDR RD
32 16 32
5 5 5
Instruction
Memory RN1 RN2 WN
RD1
Register File ALU
WD
RD2 M
U ADDR
X
Data
RD M
E Memory U
16 X 32 X
T WD
N
D

Write register number comes from another later instruction!

 Corrected Datapath
IF/ID ID/EX EX/MEM MEM/WB

ADD
ADD
4 64 bits 133 bits
102 bits 69 bits
<<2
PC
ADDR RD 5
RN1 RD1
32
ALU Zero
Instruction RN2
5
Memory Register
5
WN File RD2 M
WD U ADDR
X
Data
E Memory RD M
U
16 X 32 X
T WD
N
5 D

Destination register number is also passed through ID/EX, EX/MEM

and MEM/WB registers, which are now wider by 5 bits
Pipelined Example
⚫ Consider the following instruction sequence:
lw $t0, 10($t1)
sw $t3, 20($t4)
add $t5, $t6, $t7
sub $t8, $t9, $t10
Single-Clock-Cycle Diagram:
Clock Cycle 1
LW
Single-Clock-Cycle Diagram:
Clock Cycle 2
SW LW
Single-Clock-Cycle Diagram:
Clock Cycle 3
ADD SW LW
Single-Clock-Cycle Diagram:
Clock Cycle 4
SUB ADD SW LW
Single-Clock-Cycle Diagram:
Clock Cycle 5
SUB ADD SW LW
Single-Clock-Cycle Diagram:
Clock Cycle 6
SUB ADD SW
Single-Clock-Cycle Diagram:
Clock Cycle 7
SUB ADD
Single-Clock-Cycle Diagram:
Clock Cycle 8
SUB