0.

1 – 6 GHz 3 V, 14 dBm Amplifier

Technical Data

MGA-81563

Features Surface Mount Package Description

• +14.8 dBm P1dB at 2.0 GHz SOT-363 (SC-70) Hewlett-Packard’s MGA-81563 is
+17 dBm Psat at 2.0 GHz an economical, easy-to-use GaAs
MMIC amplifier that offers
• Single +3V Supply excellent power and low noise
• 2.8 dB Noise Figure at figure for applications from 0.1 to
2.0␣ GHz 6 GHz. Packaged in an ultra-
• 12.4 dB Gain at 2.0 GHz miniature SOT-363 package, it
requires half the board space of a
• Ultra-miniature Package
SOT-143 package.
• Unconditionally Stable Pin Connections and
Package Marking The output of the amplifier is
matched to 50 Ω (better than
Applications OUTPUT 2.1:1␣ VSWR) across the entire
GND 1 6 and V
• Buffer or Driver Amp for d
81

bandwidth. The input is partially

PCS, PHS, ISM, SATCOM GND 2 5 GND matched to 50 Ω (better than
and WLL Applications 2.5:1␣ VSWR) below 4 GHz and
INPUT 3 4 GND
• High Dynamic Range LNA fully matched to 50 Ω (better than
2:1 VSWR) above. A simple series
Note: Package marking provides inductor can be added to the input
orientation and identification. to improve the input match below
Simplified Schematic
4 GHz. The amplifier allows a
wide dynamic range by offering a
OUTPUT
2.7 dB NF coupled with a +27 dBm
and Vd Output IP3.
6
INPUT The circuit uses state-of-the-art
3 PHEMT technology with proven
reliability. On-chip bias circuitry
allows operation from a single
BIAS
BIAS +3␣ V power supply, while resistive
feedback ensures stability (K>1)
over all frequencies and
GND temperatures.
1, 2, 4, 5

5965-9684E 6-196
MGA-81563 Absolute Maximum Ratings
Absolute Thermal Resistance [2]:
Symbol Parameter Units Maximum[1] θch-c = 220°C/W
Vd Device Voltage, RF Output V 6.0
to Ground Notes:
1. Permanent damage may occur if
Vgd Device Voltage, Gate V -6.0 any of these limits are exceeded.
to Drain 2. TC = 25°C (TC is defined to be the
Vin Range of RF Input Voltage V +0.5 to -1.0 temperature at the package pins
to Ground where contact is made to the
circuit board.)
Pin CW RF Input Power dBm +13
Tch Channel Temperature °C 165
TSTG Storage Temperature °C -65 to 150

MGA-81563 Electrical Specifications, TC = 25°C, ZO = 50 Ω, Vd = 3 V

Symbol Parameters and Test Conditions Units Min. Typ. Max. Std Dev [2]
Gtest Gain in test circuit[1] f = 2.0 GHz 10.5 12.4 0.44
NFtest Noise Figure in test circuit[1] f = 2.0 GHz 2.8 3.8 0.21
NF50 Noise Figure in 50 Ω system f = 0.5 GHz dB 3.1
f = 1.0 GHz 3.0
f = 2.0 GHz 2.7 0.21
f = 3.0 GHz 2.7
f = 4.0 GHz 2.8
f = 6.0 GHz 3.5
|S21|2 Gain in 50 Ω system f = 0.5 GHz dB 12.5
f = 1.0 GHz 12.5
f = 2.0 GHz 12.3 0.44
f = 3.0 GHz 11.8
f = 4.0 GHz 11.4
f = 6.0 GHz 10.2
P1 dB Output Power at 1 dB Gain Compression f = 0.5 GHz dBm 15.1
f = 1.0 GHz 14.8
f = 2.0 GHz 14.8 0.86
f = 3.0 GHz 14.8
f = 4.0 GHz 14.8
f = 6.0 GHz 14.7
IP3 Output Third Order Intercept Point f = 2.0 GHz dBm +27 1.0
VSWRin Input VSWR f = 2.0 GHz 2.7:1
VSWRout Output VSWR f = 2.0 GHz 2.0:1
Id Device Current mA 31 42 51
Notes:
1. Guaranteed specifications are 100% tested in the circuit in Figure 10 in the Applications Information section.
2. Standard deviation number is based on measurement of at least 500 parts from three non-consecutive wafer lots during
the initial characterization of this product, and is intended to be used as an estimate for distribution of the typical
specification.

6-197
MGA-81563 Typical Performance, TC = 25° C, Vd = 3 V
16 5 16

14
4 15
12

NOISE FIGURE (dB)

P1 dB (dBm)
10
GAIN (dB)

3 14
8

6 2 13

4 TA = +85°C TA = +85°C TA = +85°C

1 12
TA = +25°C TA = +25°C TA = +25°C
2
TA = –40°C TA = –40°C TA = –40°C
0 0 11
0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6
FREQUENCY (GHz) FREQUENCY (GHz) FREQUENCY (GHz)
Figure 1. 50 Ω Power Gain vs. Figure 2. Noise Figure (into 50 Ω) Figure 3. Output Power @ 1 dB Gain
Frequency and Temperature. vs. Frequency and Temperature. Compression vs. Frequency and
Temperature.

16 5 16

14
4 15
12
NOISE FIGURE (dB)

P1 dB (dBm)
10
GAIN (dB)

3 14
8

6 2 13

4 Vd = 3.3V Vd = 3.3V
Vd = 3.3V
Vd = 3.0V 1 Vd = 3.0V 12
Vd = 3.0V
2 Vd = 2.7V Vd = 2.7V
Vd = 2.7V
0 0 11
0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6
FREQUENCY (GHz) FREQUENCY (GHz) FREQUENCY (GHz)

Figure 4. 50 Ω Power Gain vs. Figure 5. Noise Figure (into 50 Ω) vs. Figure 6. Output Power @ 1 dB Gain
Frequency and Voltage. Frequency and Voltage. Compression) vs. Frequency and
Voltage.

4 60 16

14
3.5 50 Gain
DEVICE CURRENT (mA)

Input 12
GAIN and NF (dB)

3 40
VSWR (n:1)

10

2.5 30 8
Output
TA = +85°C 6
2 20
TA = +25°C
4
TA = -40°C NF
1.5 10
2

1 0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 0 1 2 3 4 5 6
FREQUENCY (GHz) DEVICE VOLTAGE (V) FREQUENCY (GHz)

Figure 7. Input and Output VSWR Figure 8. Device Current vs. Voltage Figure 9. Minimum Noise Figure and
into 50 Ω vs. Frequency. and Temperature. Associated Gain vs. Frequency.

6-198
MGA-81563 Typical Scattering Parameters[1], TC = 25°C, Z O = 50 Ω, Vd = 3 V
Freq. S11 S21 S12 S22
K
GHz Mag Ang dB Mag Ang dB Mag Ang Mag Ang Factor
0.1 0.57 -16 13.02 4.48 172 -25 0.051 312 0.43 -14 1.47
0.2 0.52 -13 12.58 4.258 171 -25 0.057 17 0.38 -13 1.58
0.5 0.49 -16 12.35 4.15 164 -25 0.059 8 0.35 -9 1.64
1.0 0.48 -28 12.18 4.06 152 -25 0.061 5 0.35 -15 1.65
1.5 0.47 -40 12.00 3.98 140 -25 0.063 5 0.34 -22 1.65
2.0 0.45 -52 11.82 3.90 128 -24 0.067 4 0.34 -30 1.65
2.5 0.43 -63 11.63 3.81 116 -24 0.070 2 0.32 -39 1.66
3.0 0.39 -75 11.37 3.70 104 -24 0.074 -1 0.31 -46 1.69
3.5 0.35 -87 11.11 3.59 93 -22 0.077 -4 0.29 -53 1.73
4.0 0.32 -100 10.85 3.49 81 -22 0.081 -7 0.27 -60 1.77
4.5 0.28 -114 10.58 3.38 70 -22 0.083 -11 0.25 -67 1.82
5.0 0.25 -130 10.30 3.27 59 -21 0.087 -15 0.23 -74 1.85
5.5 0.22 -146 10.02 3.17 49 -21 0.09 -20 0.21 -81 1.91
6.0 0.20 -166 9.75 3.07 38 -21 0.091 -25 0.19 -90 1.93
6.5 0.18 174 9.46 2.97 27 -21 0.093 -30 0.17 -96 1.98
7.0 0.17 150 9.12 2.86 16 -21 0.094 -36 0.14 -100 2.05

MGA-81563 Typical Noise Parameters[1]

TC = 25°C, ZO = 50 Ω, Vd = 3 V
Frequency NFO Γopt Rn / 50 Ω
GHz dB Mag. Ang. —
0.5 2.90 0.16 1 1.57
1.0 2.80 0.15 17 0.96
1.5 2.70 0.14 28 0.75
2.0 2.69 0.14 37 0.41
2.5 2.68 0.13 44 0.39
3.0 2.68 0.11 50 0.38
3.5 2.68 0.09 56 0.36
4.0 2.69 0.06 65 0.34
4.5 2.69 0.03 76 0.33
5.0 2.68 0.01 137 0.32
5.5 2.67 0.02 -135 0.32
6.0 2.67 0.05 -109 0.32
6.5 2.71 0.07 -95 0.33
7.0 2.77 0.09 -78 0.36
Note:
1. Reference plane per Figure 11 in Applications Information section.

6-199
MGA-81563 Applications The 14.8 dBm output power (P1dB) Specifications and Statistical
Information also makes the MGA-81563 Parameters
extremely useful for pre-driver, Several categories of parameters
driver and buffer stages. For appear within this data sheet.
Introduction
transmitter gain stage applications Parameters may be described with
This high performance GaAs
that require higher output power, values that are either “minimum
MMIC amplifier was developed for
the MGA-81563 can provide or maximum,” “typical,” or
commercial wireless applications
50␣ mW (17 dBm) of saturated “standard deviations.”
from 100 MHz to 6 GHz.
output power with a high power
added efficiency of 45%. The values for parameters are
The MGA-81563 runs on only
based on comprehensive product
3␣ volts and typically requires only
Test Circuit characterization data, in which
42 mA to deliver 14.8 dBm of
The circuit shown in Figure 10 is automated measurements are
output power at 1 dB gain
used for 100% RF testing of Noise made on of a minimum of
compression.
Figure and Gain. The 3.9 nH 500␣ parts taken from 3 non-
inductor at the input fix-tunes the consecutive process lots of
An innovative internal bias circuit
circuit to 2 GHz. The only purpose semiconductor wafers. The data
regulates the device’s internal
of the RFC at the output is to derived from product character-
current to enable the MGA-81563
apply DC bias to the device under ization tends to be normally
to operate over a wide tempera-
test. Tests in this circuit are used distributed, e.g., fits the standard
ture range with a single, positive
to guarantee the NFtest and Gtest “bell curve.”
power supply of 3 volts.
The MGA-81563 will operate with parameters shown in the table of
Electrical Specifications. Parameters considered to be the
reduced performance with
most important to system perfor-
voltages as low as 1.5 volts. 100 pF
RF
RF mance are bounded by minimum
OUTPUT
81

INPUT 22 nH or maximum values. For the

The MGA-81563 uses resistive RFC
3.9 nH MGA-81563, these parameters are:
feedback to simultaneously Vd
Gain (Gtest), Noise Figure (NFtest),
achieve flat gain over a wide 100 pF
and Device Current (Id). Each of
bandwidth and match the input
these guaranteed parameters is
and output impedances to 50 Ω. Figure 10. Test Circuit.
100% tested.
The MGA-81563 is unconditionally
Phase Reference Planes
stable (K>1) over its entire
The positions of the reference Values for most of the parameters
frequency range, making it both
planes used to specify the S- in the table of Electrical Specifica-
very easy to use and yielding
Parameters and Noise Parameters tions that are described by typical
consistent performance in the
for this device are shown in data are the mathematical mean
manufacture of high volume
Figure 11. As seen in the illustra- (µ), of the normal distribution
wireless products.
tion, the reference planes are taken from the characterization
located at the point where the data. For parameters where
With a combination of high
package leads contact the test measurements or mathematical
linearity (+27 dBm output IP3) and
circuit. averaging may not be practical,
low noise figure (3 dB), the
such as the Noise and S-parameter
MGA-81563 offers outstanding REFERENCE
PLANES tables or performance curves, the
performance for applications
data represents a nominal part
requiring a high dynamic range,
taken from the “center” of the
such as receivers operating in
characterization distribution.
dense signal environments. A wide
TEST CIRCUIT
Typical values are intended to be
dynamic range amplifier such as
used as a basis for electrical
the MGA-81563 can often be used
Figure 11. Phase Reference Planes. design.
to relieve the requirements of
bulky, lossy filters at a receiver’s
input.

6-200
To assist designers in optimizing through holes (vias) that are Biasing
not only the immediate circuit placed near the package termi- The MGA-81563 is a voltage-
using the MGA-81563, but to also nals. As a minimum, one via biased device and is designed to
optimize and evaluate trade-offs should be located next to each operate from a single, +3 volt
that affect a complete wireless ground pin to ensure good RF power supply with a typical
system, the standard grounding. It is a good practice to current drain of 42 mA. The
deviation␣ ( σ) is provided for use multiple vias to further internal current regulation circuit
many of the Electrical Specifica- minimize ground path inductance. allows the amplifier to be oper-
tions parameters (at 25°) in ated with voltages as high +5 volts
addition to the mean. The stan- or as low as +1.5 volt. Refer to the
dard deviation is a measure of the 50 Ω section titled “Operation at Bias
81 RF Output
variability about the mean. It will RF Input and Vd Voltages Other than 3 Volts” for
be recalled that a normal distribu- information on performance and
50 Ω
tion is completely described by precautions when using other
the mean and standard deviation. voltages.
Figure13. RFLayout.
Standard statistics tables or Typical Application Example
calculations provide the probabil- It is recommended that the PCB The printed circuit layout in
ity of a parameter falling between pads for the ground pins not be Figure 14 can serve as a design
any two values, usually symmetri- connected together underneath guide. This layout is a
cally located about the mean. the body of the package. PCB microstripline design (solid
Referring to Figure 12 for ex- traces hidden under the package groundplane on the backside of
ample, the probability of a param- cannot be adequately inspected the circuit board) with a 50 Ω
eter being between ± 1σ is 68.3%; for SMT solder quality. input and output. The circuit is
between ± 2σ is 95.4%; and be- fabricated on 0.031-inch thick
tween ± 3σ is 99.7%. PCB Material FR-4 dielectric material. Plated
FR-4 or G-10 printed circuit board through holes (vias) are used to
materials are a good choice for bring the ground to the top side of
68% most low cost wireless applica- the circuit where needed. Multiple
tions. Typical board thickness is vias are used to reduce the
95% 0.020 to 0.031 inches. The width of inductance of the paths to ground.
the 50 Ω microstriplines on PC
99% boards in this thickness range is H
-3σ -2σ -1σ Mean (µ) +1σ +2σ +3σ also very convenient for mounting
(typical)
chip components such as the OUT
Parameter Value
series inductor at the input or DC
Figure12. NormalDistribution. blocking and bypass capacitors. IN

RF Layout For higher frequencies or for +V

The RF layout in Figure 13 is noise figure critical applications,
suggested as a starting point for the additional cost of PTFE/glass MGA-8-A
microstripline designs using the dielectric materials may be
MGA-81563 amplifier. Adequate warranted to minimize transmis- Figure14. PCBLayout.
grounding is needed to obtain sion line loss at the amplifier’s
optimum performance and to input. A 0.5 inch length of 50 Ω A schematic diagram of the
maintain stability. All of the microstripline on FR-4, for application circuit is shown in
ground pins of the MMIC should example, has approximately Figure 15. DC blocking capacitors
be connected to the RF 0.3␣ dB loss at 4 GHz. This loss will (C1 and C2) are used at the input
groundplane on the backside of add directly to the noise figure of and output of the MMIC to isolate
the PCB by means of plated the MGA-81563. the device from adjacent circuits.

6-201
Although the input terminal of the bias lines that could cause oscilla- The input of the MGA-81563 is
MGA-81563 is at ground potential, tion. C4 will not normally be partially matched internally to
it is not a current sink. If the input needed unless several stages are 50␣ Ω. Without external matching
is connected to a preceding stage cascaded using a common power elements, the input VSWR of the
that has a voltage present, the use supply. MGA-81563 is 3.0:1 at 300 MHz
of the DC blocking capacitor (C1) and decreases to 1.5:1 at 6 GHz.
is required. When multiple bypass capacitors This will be adequate for many
are used, consideration should be applications. If a better input
C2 Vd
given to potential resonances. It is VSWR is required, the use of a
C4 important to ensure that the series inductor, L1 in the applica-
RFC capacitors when combined with tions example, (or, alternatively a
RF RF
Input C1 L1 C2 Output additional parasitic L’s and C’s on length of high impedance trans-
the circuit board do not form mission line) is all that is needed
resonant circuits. The addition of to improve the match. The table in
a small value resistor in the bias Figure 16 shows suggested values
Figure15. SchematicDiagram.
supply line between bypass for L1 for various wireless fre-
DC bias is applied to the MGA- capacitors will often “de-Q” the quency bands.
81563 through the RF Output pin. bias circuit and eliminate the
An inductor (RFC), or length of effect of a resonance. Frequency Inductor, L1
high impedance transmission line (GHz) (nH)
(preferably λ/4 at the band The value of the DC blocking and 0.9 10
center), is used to isolate the RF RF bypass capacitors (C1 – C3) 1.5 6.8
from the DC supply. should be chosen to provide a 1.9 3.9
small reactance (typically 2.4 2.7
The power supply is bypassed to <␣ 5␣ ohms) at the lowest operating 4.0 0.5
ground with capacitor C3 to keep frequency. The reactance of the 5.8 0
RF off of the DC lines and to RF choke (RFC) should be high Figure16. ValuesforL1.
prevent gain dips or peaks in the (e.g., several hundred ohms) at
the lowest frequency of operation. These values for L1 take into
response of the amplifier.
account the short length of 50 Ω
The MGA-81563’s response at low transmission line between the
An additional bypass capacitor,
frequencies is limited to approxi- inductor and the input pin of the
C4, may be added to the bias line
mately 100 MHz by the size of device.
near the Vd connection to elimi-
nate unwanted feedback through capacitors integrated on the
For applications requiring mini-
MMIC chip.
mum noise figure (NFo), some
improvement over a 50 Ω match is
H possible by matching the signal
input to the optimum noise match
impedance, Γo, as specified in the
“Typical Noise Parameters” table.
C1 L1 OUT
For most applications, as shown
C2
in the example circuit, the output
of the MGA-81563 is already
IN RFC sufficiently well matched to 50 Ω
C3 and no additional matching is
needed. The nominal device
+V output VSWR is ≤ 2.2:1 from
300␣ MHz through 6 GHz.
C4
MGA-8-A The completed application
amplifier with all components and
SMA connectors is shown in
Figure 17. Complete Application Circuit. Figure 17.
6-202
Operation in Saturation for 50
PAE
Like other active devices, the
Higher Output Power intermodulation products of the

Pout and IP3 (dBm), PAE (%)

40
For applications such as pre- MGA-81563 increase as the device
driver and driver stages in trans- 30 IP3 is driven further into nonlinear
mitters, the MGA-81563 can be operation. The 3rd, 5th, and 7th
operated in saturation to deliver 20 order intermodulation products of
up to 50 mW (17 dBm) of output Power the MGA-81563 are shown in
10
power. The power added effi- Figure 19 along with the funda-
ciency increases to 45% at these 0 mental response. This data was
power levels. measured in the test circuit in
-10 Figure 10.
-20 -15 -10 -5 0 5 10
There are several design consider- POWER IN (dBm)
ations related to reliability and Figure18.OutputPower,IP 3,and 30

Pout, 3rd, 5th, 7th HARMONICS (dBm)

performance that should be taken Power-Added-Efficiencyvs.Input 20
into account when operating the Power. (V d =3.0V)
10
amplifier in saturation. Pout
As the input power is increased 0

First of all, it is important that the beyond the linear range of the -10
3rd
stage preceding the MGA-81563 amplifier, the gain becomes more -20

not overdrive the device. Refer- compressed. Gain as a function of -30

ring to the “Absolute Maximum either input or output power may -40
Ratings” table, the maximum be derived from Figure 18. Gain -50
5th 7th

allowable input power is compression renders the amplifier

-60
+13␣ dBm. This should be regarded less sensitive to variations in the -30 -15 -10 -5 0 5 10 15

as the input power level above power level from the preceding FREQUENCY (GHz)

which the device could be perma- stage. This can be a benefit in Figure19.IntermodulationProducts
nently damaged. systems requiring fairly constant vs.InputPower.(V d =3.0V)
output power levels from the
Driving the amplifier into satura- MGA-81563. Operation at Bias Voltages
tion will also affect electrical Other than 3 Volts
performance. Figure 18 presents Increased efficiency (45% at full While the MGA-81563 is designed
the Output Power, Third Order output power) is another benefit primarily for use in +3 volt
Intercept Point (Output IP3), and of saturated operation. At high applications, the internal bias
Power Added Efficiency (PAE) as output power levels, the bias regulation circuitry allows it to be
a function of Input Power. This supply current drops by about operated with any power supply
data represents performance into 15%. This is normal and is taken voltage from +1.5 to +5 volts.
a 50 Ω load. Since the output into account for the PAE data in Performance of Gain, Noise
impedance of the device changes Figure 18. Figure, and Output Power over a
when driven into saturation, it is wide range of bias voltage is
possible to obtain even more Noise figure and input impedance shown in Figure 20. As can be
output power with a “power are also affected by saturated seen, the gain and NF are fairly
match.” The optimum impedance power operation. As a guideline, flat, but an increase in output
match for maximum output power the input impedance is lowered, power is possible by using higher
is dependent on frequency and resulting in an improvement in voltages. The use of +5 volts
actual output power level and can input VSWR of approximately 20%. increases the P1dB by 2 dBm.
be arrived at empirically.

6-203
 18 +5 V +5 V +5 V shown in Figure 22 (dimensions
16 Power are in inches). This layout pro-
14 47 Ω Zener vides ample allowance for pack-
NF, GAIN, P1 dB (dB)

Silicon Diode
12 Gain
Diodes age placement by automated
10 assembly equipment without
8
adding parasitics that could
impair the high frequency RF
6
performance of the MGA-81563.
4 NF (a) (b) (c)
The layout is shown with a
2
nominal SOT-363 package foot-
Figure21. BiasingFromHigher
0 print superimposed on the PCB
0 1 2 3 4 5 SupplyVoltages.
SUPPLY VOLTAGE (V) pads.
Figure20. Gain,NoiseFigure,and A second method illustrated in
OutputPowervs.SupplyVoltage. Figure 21b, is to use forward- 0.026
biased diodes in series with the
Some thermal precautions must power supply. For example, three
be observed for operation at silicon diodes connected in series
higher bias voltages. For reliable will drop a 5-volt supply to 0.075
operation, the channel tempera- approximately 3 volts.
ture should be kept within the 0.035
165° C indicated in the “Absolute The use of the series diode
Maximum Ratings” table. As a approach has the advantage of 0.016
guideline, operating life tests have less dependency on current
established a MTTF in excess of variation in the amplifiers since Figure22. PCBPadLayout
106 hours for channel tempera- (dimensionsininches).
the forward voltage drop of a
tures up to 150° C. diode is somewhat current
SMT Assembly
independent.
There are several means of biasing Reliable assembly of surface
the MGA-81563 at 3 volts in mount components is a complex
Reverse breakdown diodes (e.g.,
systems that use higher power process that involves many
Zener diodes) could also be used
supply voltages. The simplest material, process, and equipment
as in Figure 21c. However, care
method, shown in Figure 21a, is to factors, including: method of
should be taken to ensure that the
use a series resistor to drop the heating (e.g., IR or vapor phase
noise generated by diodes in
device voltage to 3 volts. For reflow, wave soldering, etc.)
either Zener or reverse break-
example, a 47 Ω resistor will drop circuit board material, conductor
down is adequately filtered (e.g.,
a 5-volt supply to 3 volts at the thickness and pattern, type of
bypassed to ground) such that the
nominal current of 42 mA. Some solder alloy, and the thermal
diode’s noise is not added to the
variation in performance could be conductivity and thermal mass of
amplifier’s signal.
expected for this method due to components. Components with a
variations in current within the low mass, such as the SOT-363
SOT-363 PCB Footprint
specified 31 to 51 mA min/max package, will reach solder reflow
A recommended PCB pad layout
range. temperatures faster than those
for the miniature SOT-363 (SC-70)
with a greater mass.
package used by the MGA-81563 is

6-204
 250
TMAX

200
TEMPERATURE (°C)

150
Reflow
Zone
100
Preheat Cool Down
Zone Zone
50

0
0 60 120 180 240 300
TIME (seconds)

Figure 23. Surface Mount Assembly Profile.

The MGA-81563 is has been These parameters are typical for a

qualified to the time-temperature surface mount assembly process
profile shown in Figure 23. This for the MGA-81563. As a general
profile is representative of an IR guideline, the circuit board and
reflow type of surface mount components should be exposed
assembly process. only to the minimum tempera-
tures and times necessary to
After ramping up from room achieve a uniform reflow of
temperature, the circuit board solder.
with components attached to it
(held in place with solder paste) Electrostatic Sensitivity
passes through one or more GaAs MMICs are
preheat zones. The preheat zones electrostatic discharge
increase the temperature of the (ESD) sensitive
board and components to prevent devices. Although the
thermal shock and begin evaporat- MGA-81563 is robust in design,
ing solvents from the solder paste. permanent damage may occur to
The reflow zone briefly elevates these devices if they are subjected
the temperature sufficiently to to high energy electrostatic
produce a reflow of the solder. discharges. Electrostatic charges
as high as several thousand volts
The rates of change of tempera- (which readily accumulate on the
ture for the ramp-up and cool- human body and on test equip-
down zones are chosen to be low ment) can discharge without
enough to not cause deformation detection and may result in
of the board or damage to compo- degradation in performance or
nents due to thermal shock. The failure. The MGA-81563 is an ESD
maximum temperature in the Class 1 device. Therefore, proper
reflow zone (TMAX) should not ESD precautions are recom-
exceed 235 °C. mended when handling, inspect-
ing, and assembling these devices
to avoid damage.

6-205
Package Dimensions
Outline 63 (SOT-363/SC-70)

1.30 (0.051)
REF.

2.20 (0.087) 1.35 (0.053)

2.00 (0.079) 1.15 (0.045)

0.650 BSC (0.025)

2.20 (0.087) 0.425 (0.017)
1.80 (0.071) TYP.

0.10 (0.004)
0.00 (0.00) 0.30 REF.

1.00 (0.039) 0.20 (0.008)

0.80 (0.031) 0.10 (0.004)
0.25 (0.010) 10° 0.30 (0.012)
0.15 (0.006) 0.10 (0.004)

DIMENSIONS ARE IN MILLIMETERS (INCHES)

MGA-81563 Part Number Ordering Information

Part Number No. of Devices Container
MGA-81563-TR1 3000 7" Reel
MGA-81563-BLK 100 antistatic bag

6-206
Device Orientation
REEL
TOP VIEW END VIEW
4 mm

8 mm
CARRIER 81 81 81 81
TAPE

USER
FEED
DIRECTION
COVER TAPE

Tape Dimensions and Product Orientation

For Outline 63
P D P2

P0

F
W
C

D1
t1 (CARRIER TAPE THICKNESS) Tt (COVER TAPE THICKNESS)

8° MAX. K0 5° MAX.

A0 B0

DESCRIPTION SYMBOL SIZE (mm) SIZE (INCHES)

CAVITY LENGTH A0 2.24 ± 0.10 0.088 ± 0.004
WIDTH B0 2.34 ± 0.10 0.092 ± 0.004
DEPTH K0 1.22 ± 0.10 0.048 ± 0.004
PITCH P 4.00 ± 0.10 0.157 ± 0.004
BOTTOM HOLE DIAMETER D1 1.00 + 0.25 0.039 + 0.010
PERFORATION DIAMETER D 1.55 ± 0.05 0.061 ± 0.002
PITCH P0 4.00 ± 0.10 0.157 ± 0.004
POSITION E 1.75 ± 0.10 0.069 ± 0.004

CARRIER TAPE WIDTH W 8.00 ± 0.30 0.315 ± 0.012

THICKNESS t1 0.255 ± 0.013 0.010 ± 0.0005
COVER TAPE WIDTH C 5.4 ± 0.10 0.205 ± 0.004
TAPE THICKNESS Tt 0.062 ± 0.001 0.0025 ± 0.00004
DISTANCE CAVITY TO PERFORATION F 3.50 ± 0.05 0.138 ± 0.002
(WIDTH DIRECTION)
CAVITY TO PERFORATION P2 2.00 ± 0.05 0.079 ± 0.002
(LENGTH DIRECTION)

6-207