International Conference on Computing, Communication and Automation (ICCCA2015)

Crosstalk Noise and Delay Analysis for High

Speed On-Chip Global RLC VLSI Interconnects
with Mutual Inductance using 90nm Process
Technology
Apoorva Gupta VikasMaheshwari Shalini Sharma RajibKar
3
Deptt. Of ECE, Hindustan Deptt. Of ECE, ASET, Amity Deptt. Of Mathematics Deptt. of ECE, National
College of Science and University Madhya-Pradesh, Institute of Engineering & Institute of Technology,
Technology, Mathura, Gwalior, M.P., INDIA Technology, Khandari, Durgapur, West-Bengal,
Uttar Pradesh, INDIA maheshwarivikas1982@gmail. Agra, U.P., INDIA INDIA
[email protected] com [email protected] [email protected]

Abstract: With continuous scaling of VLSI technology, proposed model [3-10] for network interconnects. In
coupling capacitance between interconnects lines need this paper closed loop L type RLC interconnect is
more accurate transmission line modelling, requiring the proposed. There are two RLC circuits adjacent to each
introduction of self and mutual inductances. Self and other with mutual inductance. An aggressor line is
mutual inductances can cause for crosstalk noise and
parallel to the victim line. There ismutual inductance
delay between high speeds VLSI interconnects. This
paper presents an mathematical computation of crosstalk induced between these two lines. This paper analyzes
noise of ‘L’ Type RLC global interconnects in the mathematical computation of crosstalk noise of high
presence of self and mutual inductances. This crosstalk speed VLSI RLC interconnectswhen mutual inductance
noise analysis is carried out for the case when two L type is present. This paper also gives expression for peak
RLC networks are parallel to each other but are not noise voltage and delay between adjacent RLC
connected, and Step input is applied to the aggressor line networks using L type network model.
which is adjacent to the victim line. This paper also
presents to analyze L type interconnect models in deriving
Remaining part of the paper is synchronized as
mathematical expressions for Peak noise voltage and
Delay between adjacent RLC networks with mutual
follows: section 2 describe the basic theory related to
inductance. cross talk noise, RLC interconnect model and mutual
inductance. Proposed models and derived equations is
Keywords: Crosstalk Noise, Delay, Mutual inductance, described in section 3. Section 4 illustrates the
RLC interconnect, VLSI. simulation result and final result and error in proposed
model. And finally section 5 concludes this paper.
I. INTRODUCTION
II. BASIC THEORY
The evolution of integrated circuit technology took
monstrous efforts, but it appears now as a simple and There are basically two types of RLC circuits: series
usual task to us to integrate a vital number of RLC interconnection and parallel RLC interconnection.
components on a chip. Moore’s [1] predictions are In this paper we use ‘L’ type RLC interconnection in
very exact up to now, as, we have moved from a single which R and L are connected in series with parallel
transistor to a System on Chipconsisting multibillion connected with capacitor. Generalize RLC network is
transistors. The shrinking of process technology [2] in shown in Fig.1.
Deep Sub Micron region has made it very possible to
place an enormous amount of components on a single Here two L type RLC interconnects are considered
chip.The process of fabrication of integrated circuits by which are parallel to each other. Input is given only to
combining hundreds of thousands of transistors into a one RLC circuit that is known as ‘aggressor line’ and
single chip is usually referred to very-large-scale- remaining second RLC interconnect is named as
integration (VLSI).Modern ICs are now composed ‘victim line’. Since both RLC connection are parallel to
millions of transistors switching simultaneously within each other so there is a capacitor generated between
a fraction of a second. There are several approaches them that is known as ‘coupling capacitor’. Due to
ISBN:978-1-4799-8890-7/15/$31.00 ©2015 IEEE 1215
 International Conferencce on Computing, Communication and Automation (ICCC
CA2015)

inductance, mutual inductance also occcurs.

R = Series resistance per unit length Where,
L = Series inductance per unit length = the voltage across the inductor of interest
C = Shunt capacitance per unit length = the inductance of the inducttor of interest
= the derivative w.r.t time, of the current through
the inductor of interest
= the derivative w.r.t time, of the current through
he first inductor
the inductor that is coupled to th
M = mutual inductance
III. D MODEL
PROPOSED

Fig. 1: ‘L’ Type RLC Interconnecction In this section we compute the value of crosstalk
noise and peak noise voltage and
a delay when victim
In this paper we are using the value oof parameters R, line is quite and aggressor lin
ne is switching. Fig. 2
L and C using 90 nm technologies. So the exact values shows the L type RLC intercon nnection between driver
of the parameter R, L and C using 90 nnm technologies and load. For our computatio on we take step input
[1] are given in Table 1. voltage as input voltage when computing closed loop
expression.
TABLE 1:RLC Parameters of a Minimum Sizeed Wire in a 90 nm
Technology

Parameter(s) V
Value/mm
Resistance(R) 13Ω/mm
Inductance(L) 00.16nH/mm
Capacitance(C) 00.45pF/mm
Coupling Capacitance (Cc) 6442.49pF/mm
Mutual Inductance (m) 0.028nH/mm

Mutual Inductance
Mutual inductance occurs when the chhange in current
in one inductor induces a voltage in another nearby
Fig.3: Equivalent RLC Circuit using L model for Interconnect with
inductor. The mutual inductance, M, iss also a measure
Mutual Inductan nce m
of the coupling between two inductors.
In the circuit shown in Fig. 2, we derive
he voltage at node C on
themathematical equation for th
victim line.
Applying KVL in first mesh:
(1)
On taking Laplace,
(2)
(3))
Where,
(4)
Fig. 2: The Circuit Diagram Representation of Mutually Coupled
Similarly applying KVL in mesh h second,
1 1 1
Inductors ′

The mutual inductance also has the relaationship: ′ ′ 0(5)

M k Similarly applying KVL in third

d mesh,
1
Where, 0 ′ ′
′

k = coupling coefficient and 0 ≤ k ≤ 1, ′ ′

1 0(6)
= inductance of the first coil, Where
= inductance of the second coil. ′ ′

Mutual inductance can be used to prediict the behaviour From equations (3), (5) and (6), we get a matrix:
of a circuit:
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 International Conference on Computing, Communication and Automation (ICCCA2015)

1 1 ′

1 1 1 1 1 0
′ 0 ′
′ ′
1 1
Let,
1 1 1
1 , ′
,
′
1 If,
Then required matrix is, On taking Inverse Laplace transform:
1 ′
cos sin
1 1 0
0 sin ′
cos (14)
′
1 On differentiating with respect to t and taking
After solving by Cramer’s rule [11], this first derivative equal to zero for calculating peak
′
′ ′ ′ (7) time value, :
′ 0
′ ′ ′ (8)
′
′ ′ sin cos 0
(9)
′ ′ ′
After simplification we get
Now, at node ‘C’: ′

′ (10) tan ′ (15)

So,
On putting t= in equation (14) so that,
′ ′
1
′ ′ ′ ′
2
′
(11) ′
sin cos (16)
Where, Now calculate the value of :
′ ′ ′
2 1
On putting the values of A, B and C:
′ ′
P sC C ′ M sC 1 sM C ′ 1 2s mC C ′ 1
sC C ′ CC ′ ′ ′
2
s m C C′ M sC 1 C
sC C ′ CC For unit step input, :
sM C ′ 1 C ′ ′
′ ′ ′ ′
1 1
Where, ′

′
′ ′ ′

Where,
′ ′
On putting the value of P from equation (12) and get,
Now,
1 ′
1 2 ′ ′
1 ′ ′ ′ ′
′
′ ′
1 ′ ′ ′
2
Now neglecting high power terms ′ ′ ′ ′
′
2 ′
(12) ′ ′

Now putting the value of (for unit step) & P in ′ ⁄ ′ ′ ′ ⁄

equation (11), we get (17)

1 2 3

′ Where,
′
′ ′ ′ ′ ′ 1 1 1 1 1
2
Now, let us assume: ′
′
2
′ ′ ′ ′ ⁄
′ ′

(13)
′
Substituting the value of P in the expression of
′
VB1from equation (13)

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 International Conference on Computing, Communication and Automation (ICCCA2015)

′
After substituting the expressions for mathematical
functions inequation (19)and ignoring higher order
terms, we get
(20)
On neglecting the higher order terms of s & then,
′
1 1
Where,
2
Similarity substituting the value of P in the expressions 2
of VB2 and VB3from equation (13), we get Now putting the values of in equation, so now
′ ′ ′ ′
′
1 . cos
,
′ ′
. sin (21)
Where,
Equations (15), (16), (20) and (21) are the expressions
for the estimation of peak delay time and peak voltages
4 at node C and B respectively.The expression given in
Substitutingthe values of , , in equation (17) equations (14) and (16) are the required crosstalk
′
1 1 1
′
voltage and peak crosstalk noise voltage respectively at
node C.
′ ′
IV. SIMULATION RESULT AND DISCUSSION

Consider two parallel RLC mutually

On taking inverse Laplace Transform of the above coupledinterconnect lines shown in Fig.-3, in 90 nm
equation technology. All wires are 1000 μm long. Such bus
′ ′ ′ ′
cos sin (18) structures are typical in high performance CPU
On differentiating with respect to t designs. The extracted values [1] for the parameters R,
′
L, C, M and Cc for the 90 nm process technologies are
given in Table I. Aggressor line is excited by a step
′
cos input signal with finite rise time and fall time of 10 ps.
2 It is assumed that identical interconnects are driven by
sin identical inverters of size, and also assume that the
′ ′
sin
loads at the end of the lines are identically sized
2 inverters. We simulate the mutually coupled
cos interconnects by using different input slew times
Taking first derivative and keeping it equal to zero for ranging from 0ps to 200ps for the driving inverters.
calculating peak time after simplification: Our results for the L-interconnect model are discussed
′ in Table 2 for the peak crosstalk noise voltage
expressed by equation (16) for node C for different
cos ′ slew times of the input signal. These results are within
2
′ ′ 10 % of the values derived by SPICE.

sin ′ ′ Table 3 discuss the comparative result for aggressor

2 line voltage expressed by equation (21) with SPICE
′
0 valuesfor the different input slew values. All the
Let us assume for simplicity, aggressor line voltages are measured in volts (V).
′
Table 4 and Table 5 give the comparative result of the
peak times tpc and tpb for the victim line and aggressor
′ ′
′ line peak voltages expressed by equations (15) and
2 (20) respectively for the different slew times of the
′ ′ ′ input signal. All the time values are measured in
2
nanoseconds (ns).
After simplification above equation becomes,
. cos . sin . 0
TABLE 2:COMPARATIVE RESULT FOR PEAK CROSSTALK NOISE
. . cos . sin 0(19) OBTAINED FROMPROPOSED MODEL AND SPICE
RD1 RD2 CL Ts=0 Ts=100 Ts=200
(Ω) (Ω) (fF) SPICE Proposed SPICE Proposed SPICE Our
Values Model Values Model Values Model

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 International Conference on Computing, Communication and Automation (ICCCA2015)

(mV) Values (mV) Values (mV) Values RLCmutually coupled network. Simulation results
(mV) (mV) (mV)
10 10 1.2 98 101 143 147 163 181 demonstrate the validity and correctness of our
10 15 1.2 110 118 159 167 179 197 methods. This work can be used in much other
15 20 1.2 135 143 174 189 203 231 application at various levels to guide noise aware DSM
15 25 2.4 158 167 196 216 248 268 circuit for the estimation of crosstalk noise and delay
15 50 2.4 187 192 203 243 276 294 models. The proposed model results in an error of less
than 10% when compared to that of the SPICE
TABLE 3:COMPARATIVE RESULT FOR AGGRESSOR LINE VOLTAGE
OBTAINED FROM PROPOSED MODEL AND SPICE
simulation.
RD1 RD2 CL Ts=0 Ts=100 Ts=200
(Ω) (Ω) (pF SPICE Proposed SPICE Proposed SPICE Our REFERENCES
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