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Vector (Array) Processing and Superscalar Processors

Vector processors can process multiple data items simultaneously using a single instruction, improving efficiency over scalar processors which operate on single data items sequentially. Superscalar processors can execute multiple instructions simultaneously by utilizing multiple functional pipelines within the CPU, improving performance over scalar processors. Both approaches aim to increase parallelism and throughput compared to traditional scalar processors.

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265 views

Vector (Array) Processing and Superscalar Processors

Vector processors can process multiple data items simultaneously using a single instruction, improving efficiency over scalar processors which operate on single data items sequentially. Superscalar processors can execute multiple instructions simultaneously by utilizing multiple functional pipelines within the CPU, improving performance over scalar processors. Both approaches aim to increase parallelism and throughput compared to traditional scalar processors.

Uploaded by

karunakar
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Vector(Array) Processing and

Superscalar Processors
A Scalar processor is a normal processor, which works on simple instruction at a time,
which operates on single data items. But in today's world, this technique will prove to be
highly inefficient, as the overall processing of instructions will be very slow.

What is Vector(Array) Processing?


There is a class of computational problems that are beyond the capabilities of a
conventional computer. These problems require vast number of computations on
multiple data items, that will take a conventional computer(with scalar processor) days
or even weeks to complete.
Such complex instructions, which operates on multiple data at the same time, requires a
better way of instruction execution, which was achieved by Vector processors.
Scalar CPUs can manipulate one or two data items at a time, which is not very efficient.
Also, simple instructions like ADD A to B, and store into C are not practically efficient.
Addresses are used to point to the memory location where the data to be operated will
be found, which leads to added overhead of data lookup. So until the data is found, the
CPU would be sitting ideal, which is a big performance issue.
Hence, the concept of Instruction Pipeline comes into picture, in which the instruction
passes through several sub-units in turn. These sub-units perform various independent
functions, for example: the first one decodes the instruction, the second sub-unit
fetches the data and the third sub-unit performs the math itself. Therefore, while the
data is fetched for one instruction, CPU does not sit idle, it rather works on decoding the
next instruction set, ending up working like an assembly line.
Vector processor, not only use Instruction pipeline, but it also pipelines the data,
working on multiple data at the same time.
A normal scalar processor instruction would be ADD A, B, which leads to addition of two
operands, but what if we can instruct the processor to ADD a group of
numbers(from 0 to n memory location) to another group of numbers(lets
say, n to k memory location). This can be achieved by vector processors.
In vector processor a single instruction, can ask for multiple data operations, which
saves time, as instruction is decoded once, and then it keeps on operating on different
data items.
Applications of Vector Processors
Computer with vector processing capabilities are in demand in specialized applications.
The following are some areas where vector processing is used:

1. Petroleum exploration.
2. Medical diagnosis.
3. Data analysis.
4. Weather forecasting.
5. Aerodynamics and space flight simulations.
6. Image processing.
7. Artificial intelligence.

Superscalar Processors
It was first invented in 1987. It is a machine which is designed to improve the
performance of the scalar processor. In most applications, most of the operations are on
scalar quantities. Superscalar approach produces the high performance general
purpose processors.
The main principle of superscalar approach is that it executes instructions
independently in different pipelines. As we already know, that Instruction pipelining
leads to parallel processing thereby speeding up the processing of instructions. In
Superscalar processor, multiple such pipelines are introduced for different operations,
which further improves parallel processing.
There are multiple functional units each of which is implemented as a pipeline. Each
pipeline consists of multiple stages to handle multiple instructions at a time which
support parallel execution of instructions.
It increases the throughput because the CPU can execute multiple instructions per clock
cycle. Thus, superscalar processors are much faster than scalar processors.
A scalar processor works on one or two data items, while the vector processor works
with multiple data items. A superscalar processor is a combination of both. Each
instruction processes one data item, but there are multiple execution units within each
CPU thus multiple instructions can be processing separate data items concurrently.
While a superscalar CPU is also pipelined, there are two different performance
enhancement techniques. It is possible to have a non-pipelined superscalar CPU or
pipelined non-superscalar CPU. The superscalar technique is associated with some
characteristics, these are:

1. Instructions are issued from a sequential instruction stream.


2. CPU must dynamically check for data dependencies.
3. Should accept multiple instructions per clock cycle.

ector(Array) Processor and


its Types
Array processors are also known as multiprocessors or vector processors. They perform
computations on large arrays of data. Thus, they are used to improve the performance of the
computer.

Types of Array Processors


There are basically two types of array processors:

1. Attached Array Processors


2. SIMD Array Processors

Attached Array Processors


An attached array processor is a processor which is attached to a general purpose computer and
its purpose is to enhance and improve the performance of that computer in numerical
computational tasks. It achieves high performance by means of parallel processing with multiple
functional units.
SIMD Array Processors
SIMD is the organization of a single computer containing multiple processors operating in
parallel. The processing units are made to operate under the control of a common control unit,
thus providing a single instruction stream and multiple data streams.
A general block diagram of an array processor is shown below. It contains a set of identical
processing elements (PE's), each of which is having a local memory M. Each processor element
includes an ALU and registers. The master control unit controls all the operations of the
processor elements. It also decodes the instructions and determines how the instruction is to be
executed.
The main memory is used for storing the program. The control unit is responsible for fetching
the instructions. Vector instructions are send to all PE's simultaneously and results are returned
to the memory.
The best known SIMD array processor is the ILLIAC IV computer developed by
the Burroughs corps. SIMD processors are highly specialized computers. They are only suitable
for numerical problems that can be expressed in vector or matrix form and they are not suitable
for other types of computations.
Why use the Array Processor

 Array processors increases the overall instruction processing speed.


 As most of the Array processors operates asynchronously from the host CPU, hence it
improves the overall capacity of the system.
 Array Processors has its own local memory, hence providing extra memory for systems
with low memory.

ARCHIVED: What is
superscalar architecture?
This content has been archived, and is no longer maintained by Indiana
University. Information here may no longer be accurate, and links may
no longer be available or reliable.
Superscalar architecture is a method of parallel computing used in many processors. In a
superscalar computer, the central processing unit (CPU) manages multiple instruction pipelines
to execute several instructions concurrently during a clock cycle. This is achieved by feeding the
different pipelines through a number of execution units within the processor. To successfully
implement a superscalar architecture, the CPU's instruction fetching mechanism must
intelligently retrieve and delegate instructions. Otherwise, pipeline stalls may occur, resulting in
execution units that are often idle.

To visualize how this works, consider a hospital surgical unit that consists of areas for
admittance, surgery, and recovery. Patients can move in only one direction, from admittance to
recovery, and it takes the same amount of time to go through each of the areas. Assume the
admitting area can handle three patients at a time and there are three surgical teams, each of
which can work on a single patient. Also assume the recovery area has an indeterminate number
of beds, but can accommodate only one person per bed. When the unit is working correctly, the
admitting area processes three patients at a time, sends one to each of the teams, and immediately
processes another three patients. Even though the surgical teams can handle only one patient at a
time, because there are three of them, they will have passed their charges on by the time the new
ones arrive. The paths the three patients take are analogous to instructions flowing through three
pipelines in a CPU clock cycle. The admitting area is like a fetching mechanism, the surgery
teams are like execution units, and the recovery room is like the registers or cache to which the
units write their results.

To illustrate the kind of problems that can occur in superscalar architectures, consider what
would happen if the staff of the admitting area in the example were not very competent. For
example, if they passed a patient in need of a kidney transplant to a surgical team before the
donor kidney was available, the team wouldn't be able to go to work. Suddenly, there would be a
bottleneck at the admitting area because only two surgical teams would be available for new
patients. Another bottleneck could occur if a surgical team tried to assign a patient to an already
occupied bed in the recovery area. Again, a bottleneck would appear because the team would not
be available until the bed was emptied and the team could move the current patient into it. Stalls
like this happen in processors when an execution unit tries to perform a task that is dependent on
the results of as yet uncalculated instructions. This is why it is important that CPUs carefully
manage the order in which they process instructions.
This is document aett in the Knowledge Base.

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