MAX86140/ Best-in-Class Optical Pulse Oximeter and

MAX86141 Heart-Rate Sensor for Wearable Health

General Description Benefits and Features

The MAX86140/MAX86141 are ultra-low-power, com- ●● Complete Single and Dual-Channel Optical Data
pletely integrated, optical data acquisition systems. On Acquisition System
the transmitter side, the MAX86140/MAX86141 have
●● Built-in Algorithm Further Enhances Rejection of Fast
three programmable high-current LED drivers that
Ambient Transients
can be configured to drive up to six LEDs. With two
MAX86140/MAX86141 devices working in master-slave ●● Optimized Architecture for Transmissive and
mode, the LED drivers can drive up to twelve LEDs. Reflective Heart Rate or SpO2 Monitoring
On the receiver side, MAX86140 consists of a single ●● Low Dark Current Noise of < 50pA RMS (Sample to
optical readout channels, while the MAX86141 has two opti- Sample Variance)
cal readout channels that can operate simultaneously. The ●● Lower Effective Dark Current Noise Achievable Through
devices have low-noise signal conditioning analog front- Multiple Sample Modes and On-Chip Averaging
end (AFE) including 19-bit ADC, an industry-lead ambient
light cancellation (ALC) circuit, and a picket fence detect ●● High-Resolution, 19-Bit Charge Integrating ADC
and replace algorithm. Due to the low power consumption, ●● Three Low-Noise, 8-Bit LED Current DACs
compact size, easy/flexible-to-use and industry-lead ambient ●● Excellent Dynamic Range > 90dB in White Card
light rejection capability of MAX86140/MAX86141, the Loop-Back Test (Sample-to-Sample Variance)
devices are ideal for a wide variety of optical-sensing
applications, such as pulse oximetry and heart rate detection. ●● Dynamic Range Extendable to > 104dB for SpO2
and > 110dB for HRM with Multiple Sample Modes
The MAX86140/MAX86141 operate on a 1.8V main and On-Chip Averaging
supply voltage and a 3.1~5.5V LED driver supply voltage.
Both devices support a standard SPI compatible interface ●● Excellent Ambient Range and Rejection Capability
and fully autonomous operation. Each device has a large • > 100μA Ambient Photodetector Current
128-word built-in FIFO. The MAX86140/MAX86141 is • > 70dB Ambient Rejection at 120Hz
available in compact wafer-level package (WLP) (2.048 x ●● Ultra-Low-Power Operation for Body Wearable Devices
1.848mm) with 0.4mm ball pitch. • Low-Power Operation, Optical Readout Channel
< 10μA (typ) at 25sps
Applications • Short Exposure Integration Period of 14.8μs,
●● Wearable Devices for Fitness, Wellness and Medical 29.4μs, 58.7μs, 117.3μs
Applications • Low Shutdown Current = 20μW (typ)
●● Optimized for Wrist, Finger, Ear, and Other Locations ●● Built-in Algorithm Further Enhances Rejection of Fast
Ambient Transients
●● Optimized Performance to Detect
●● Miniature 2.048 x 1.848mm, 5 x 4 0.4mm Ball Pitch WLP
• Optical Heart Rate
• Oxygen Saturation (SpO2) ●● -40°C to +85°C Operating Temperature Range
• Muscle Oxygen Saturation (SmO2 and StO2)

Ordering Information appears at end of data sheet.

19-100051; Rev 1; 8/17

MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Simplified Block Diagram

VREF VDD_ANA VDD_DIG

DIE TEMP
REFERENCE
12-BIT ADC INT
SCLK
DIGITAL NOISE SDI
AMBIENT CANCELLATION
CANCELLATION SDO
CSB

SPI
PD1_IN 19-BIT CURRENT ADC
INTERFACE
128- WORD
PD_GND
FIFO
19-BIT CURRENT ADC
PD2_IN
(MAX86141 ONLY)
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VLED
CONTROLLER
LED1_DRV
LED DRIVERS
LED2_DRV
LED3_DRV
MAX86140/MAX86141

PGND GND_ANA GND_DIG

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Absolute Maximum Ratings

VDD_ANA to GND_ANA.......................................-0.3V to +2.2V PD1_IN to GND_ANA...........................................-0.3V to +2.2V
VDD_DIG to GND_ANA........................................-0.3V to +2.2V PD2_IN to GND_ANA .......................................... -0.3V to +2.2V
VDD_ANA to VDD_ANA........................................-0.3V to +0.3V PD_GND to GND_ANA.........................................-0.3V to +0.3V
PGND to GND_ANA..............................................-0.3V to +0.3V All other pins to GND_ANA...................................-0.3V to +2.2V
SCLK, SDO, SDI, CSB, INT to GND_ANA...........-0.3V to +6.0V Output Short-Circuit Duration.....................................Continuous
GND_DIG to GND_ANA........................................-0.3V to +0.3V Continuous Input Current Into Any Pin
VLED to PGND.....................................................-0.3V to +6.0V (except LED_DRVx Pins)..............................................±20mA
LED_DRV1 to PGND................................. -0.3V to VLED + 0.3V Continuous Power Dissipation (WLP
LED_DRV2 to PGND................................. -0.3V to VLED + 0.3V (derate 5.5mW/°C above +70°C))............................... 440mW
LED_DRV3 to PGND................................. -0.3V to VLED + 0.3V Operating Temperature Range............................ -40°C to +85°C
Storage Temperature Range............................. -40°C to +105°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Package Information
5 x 4 WLP
PACKAGE CODE N201A2+1
Outline Number 21-100134
Land Pattern Number Refer to Application Note 1891
Thermal Resistance, Four-Layer Board:
Junction to Ambient (θJA) 55.49°C/W
Junction to Case (θJC) N/A

For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.

www.maximintegrated.com Maxim Integrated │  3

MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Electrical Characteristics
(VDDANA = 1.8V, VDDDIG = 1.8V, VLED = 5.0V, ADC_RGE = 16μA, PPG_SR = 1024sps, PPG_TINT = 14.8μs, LED_SETLNG = 6μs,
LEDx_RGE = 31mA, CPD = 65pF, PD_BIAS = 0x1, Iexposure = 1μA, TA = 25°C, min/max are from TA = -40°C to +85°C, unless other-
wise noted. (Note 1) )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Readout Channel
ADC Resolution 19 bits
ADC_RGE = 0x0 4.0
ADC_RGE = 0x1 8.0
ADC Full Scale Input Current μA
ADC_RGE = 0x2 16.0
ADC_RGE = 0x3 32.0
PPG_TINT = 0x0 14.8
PPG_TINT = 0x1 29.4
ADC Integration Time tINT μs
PPG_TINT = 0x2 58.7
PPG_TINT = 0x3 117.3
Minimum PPG Sample Rate PPG_SR = 0x0A 8 sps
Maximum PPG Sample Rate PPG_SR = 0x13 4096 sps
From nominal as indicated in the PPG_SR
Sample Rate Error -2 +2 %
table
DC Ambient Light Input Range ALR ALC = on, ALC_OVF = 1 100 μA
ALC = on, Iambient = 1μA DC with
AC Ambient Light Rejection AC_ALRR 70 dB
±0.4μA pk-pk 120Hz Sinwave
ALC = on, Iambient modulated between 0μA
DC Ambient Light Rejection and 30μA, LED_SETLNG = 12μs, 0.5 nA
PPG_TINT = 117.3μs
Dark Current Offset DC_O ALC = ON, PD_BIAS = 0x0, ADD_OFFSET = 1 ±1 Counts
PPG_TINT = 14.8μs 262
Dark Current Input Referred PPG_TINT = 29.4μs 128 pArms
Noise PPG_TINT = 58.7μs 83
PPG_TINT = 117.3μs 56 pArms
PD_BIAS = 0x1 65
Maximum Photodiode Input Iambient = 0μA, less PD_BIAS = 0x5 130
Cpd pF
Capacitance than 1nA of code shift PD_BIAS = 0x6 260
PD_BIAS = 0x7 520
VDD DC PSR Iambient = 0μA, VDD = 1.7V to 2.0V -560 -330 +560 LSB/V
LED Driver
LED Current Resolution 8 Bits
Driver DNL LEDx_RGE = 124mA -1 1 LSB
Driver INL LEDx_RGE = 124mA 0.6 LSB

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Electrical Characteristics (continued)

(VDDANA = 1.8V, VDDDIG = 1.8V, VLED = 5.0V, ADC_RGE = 16μA, PPG_SR = 1024sps, PPG_TINT = 14.8μs, LED_SETLNG = 6μs,
LEDx_RGE = 31mA, CPD = 65pF, PD_BIAS = 0x1, Iexposure = 1μA, TA = 25°C, min/max are from TA = -40°C to +85°C, unless otherwise
noted. (Note 1) )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

LEDx_RGE = 0x0 31
LEDx_RGE = 0x1 62
Full Scale LED Current (Note 3) ILED LEDx_PA = 0xFF mA
LEDx_RGE = 0x2 93
LEDx_RGE = 0x3 117 124 129
LEDx_RGE = 0x0 160 253
LEDx_PA = 0xFF, LEDx_RGE = 0x1 317
Minimum output voltage VOL 95% of the desired LED mV
current LEDx_RGE = 0x2 495
LEDx_RGE = 0x3 700
VDD = 1.8V, VLEDx_DRV = 0.9V,
LEDx_PA = 0xFF, VLED = 3.1 to -1 +400
LED Driver DC PSR 5.5V, LEDx_RGE = 124mA μA/V
VDD = 1.7 to 2.0V, TA = +25°C, LEDx_PA
110 1410
= 0xFF
LED1 Driver Compliance Interrupt LED1COMP 180 mV
Internal Die Temperature Sensor
Temperature Sensor Accuracy TA = 25°C 1 °C
Temperature Sensor Minimum
Temperature error < 5°C -40 °C
Range
Temperature Sensor Maximum
Temperature error < 5°C 85 °C
Range
Temperature ADC Acquisition
29 ms
Time
Power Supply
Power Supply Voltage VDD Verified during PSRR Test 1.7 1.8 2.0 V
LED Supply Voltage VLED Verified during PSRR Test 3.1 5.5 V

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Electrical Characteristics (continued)

(VDDANA = 1.8V, VDDDIG = 1.8V, VLED = 5.0V, ADC_RGE = 16μA, PPG_SR = 1024sps, PPG_TINT = 14.8μs, LED_SETLNG = 6μs,
LEDx_RGE = 31mA, CPD = 65pF, PD_BIAS = 0x1, Iexposure = 1μA, TA = 25°C, min/max are from TA = -40°C to +85°C, unless otherwise
noted. (Note 1) )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

MAX86140, Single LED Exposure/Sample.
PPG_SR = 4096sps, LP_MODE = 0x0, 660 780
LEDxPA = 0mA
PPG_SR = 256sps 80 μA
MAX86140, Single LED
Exposure/Sample, PPG_SR = 100sps 32
PW = 14.8µs, LP_MODE PPG_SR = 50sps 16
= 0x1, LEDx_PA = 0mA
PPG_SR = 25sps 8.5
MAX86140, Double LED Single pulse 42 μA
Exposure/Sample,
PPG_SR = 84sps, PW =
14.8μs, LP_MODE = 0x1, Double pulse 89 μA
LEDx_PA = 0mA
VDD Supply Current IDD MAX86141, Single LED Exposure/Sample.
PPG_SR = 4096sps, LP_MODE = 0x0, 978 1170
LEDxPA = 0mA
PPG_SR = 256sps 115.5 μA
MAX86141, Single LED
Exposure/Sample, PPG_SR = 100sps 46
LP_BOOST = 1, PPG_SR = 50sps 23
LEDx_PA = 0mA
PPG_SR = 25sps 11
MAX86141, Two LED Single pulse 60 μA
Exposure/Sample, PPG_SR
= 84sps, LP_BOOST = 1, Double pulse 130 μA
LEDx_PA = 0mA
Die Temperature mode, SPS = 1, Optical
8 μA
channel(s) disabled
Single LED exposure per Sample, PPG_
TINT = 117.3μs, Single-Pulse, 0.22
PPG_SR = 256sps, LEDx_PA = 0mA
PPG_SR = 256sps 1880 μA
Single LED exposure
per Sample, PPG_TINT PPG_SR = 100sps 735
VLED Supply Current ILED = 117.3μs, Single-Pulse, PPG_SR = 50sps 370
LEDx_PA = 62mA
PPG_SR=25sps 185
Two LED exposure per Single-Pulse 1240
sample, PPG_TINT =
μA
117.3μs, LEDx_PA = Dual-Pulse 2480
62mA, PPG_SR = 84sps
VDD Current in Shutdown TA = +25°C 0.6 2.5 µA
VLED Current in Shutdown TA = +25°C 1 µA

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Electrical Characteristics (continued)

(VDDANA = 1.8V, VDDDIG = 1.8V, VLED = 5.0V, ADC_RGE = 16μA, PPG_SR = 1024sps, PPG_TINT = 14.8μs, LED_SETLNG = 6μs,
LEDx_RGE = 31mA, CPD = 65pF, PD_BIAS = 0x1, Iexposure = 1μA, TA = 25°C, min/max are from TA = -40°C to +85°C, unless other-
wise noted. (Note 1) )

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Digital I/O Characteristics
SDO Output Low Voltage VOL_SDO ISINK = 2mA 0.4 V
SDO Output High Voltage VOH_SDO ISOURCE = 2mA VDD-0.4 V
Open-Drain Output Low Voltage VOL_OD ISINK = 6mA, INTB, GPIO1, GPIO2 0.4 V
Input Voltage Low VIL SDI, SCLK, CSB, GPIO1, GPIO2 0.4 V
Input Voltage High VIH SDI, SCLK, CSB, GPIO1, GPIO2 1.4 V
SDI, SCLK, CSB 330
Input Hysteresis VHYS mV
GPIO1, GPO2 240
VIN = 0V, TA = +25°C (SDI, SCLK, CSB,
Input Leakage Current IIN 0.01 1 μA
GPIO1, GPIO2)
Input Capacitance CIN SDI, SCLK, CSB, GPIO1, GPIO2 10 pF
SPI Timing Charateristics
SCLK Frequency fSCLK 8 MHz
SCLK Period tCP 125 ns
SCLK Pulse Width High tCH 40 ns
SCLK Pulse Width Low tCL 40 ns
CSB Fall to SCLK Rise Setup Time tCSS0 To 1st SCLK rising edge 20 ns
Applies to inactive rising edge preceding 1st
CSB Fall to SCLK Rise Hold Time tCSH0 5 ns
rising edge
CSB Rise to SCLK Rise Hold Time tCSH1 Applies to 24th rising edge 500 ns
SCLK Rise to CSB Fall tCSF Applies to 24th rising edge 500 ns
CSB Pulse Width High tCSPW 250 ns
SDI to SCLK Rise Setup Time tDS 10 ns
SDI to SCLK Rise Hold Time tDH 10 ns
SCLK Fall to SDO Transition tDOT CLOAD = 50pF 35 ns
CSB Fall to SDO Enabled tDOE CLOAD = 0pF 12 ns
CSB Rise to SDO Hi-Z tDOZ Disable Time 25 ns
GPIO1 External Sync Pulse Width tPLGPIO1 64 μs
GPIO2 External Clock Input (Note 4) fGPIO2 External Sample Reference Clock on GPIO2 31900 32868 Hz
GPIO2 External Clock Pulse
tPWGPIO2 1 μs
Width
Note 1: All devices are 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by Maxim
Integrated’s bench or proprietary automated test equipment (ATE) characterization.
Note 2: Specifications are guaranteed by Maxim Integrated’s bench characterization and by 100% production test using proprietary
ATE setup and conditions.
Note 3: The LED current is trim in production to meet the IR and RED ADC counts. Actual values may vary by up to ±50%. Values
shown here are for 0% trim.
Note 4: See Register Map/PPG Configuration 2 (0x12) section for the sample rate by the external clock frequency. The sample rate
will be shifted when the external clock frequency shifts.

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Typical Operating Characteristics

(VDD = 1.8V, VLED = 5.0V, GND = PGND = 0V, TA = +25°C, unless otherwise noted.)(TA = +25°C, unless otherwise noted.)

SIGNAL-TO-NOISE RATIO INPUT REFERRED NOISE

vs. ADC INPUT CURRENT vs. PD CAPACITANCE
ADC_RGE = 32ΜA ADC_RGE = 8μA
toc01 toc02
100 350
90 tINT
300 14.8μs
80 29.4μs
58.7μs

INPUT REFERRED NOISE[pA]

SIGNAL-TO-NOISE RATIO[dB]

250 117.3μs
70

60
200
50
150
40 tINT
14.8μs
30 29.4μs 100
58.7μs
20 117.3μs
50
10 PD_BIAS = 1
PD_BIAS = 2
0 0
0.0 0.1 1.0 10.0 100.0 0 50 100 150 200
ADC INPUT CURRENT [μ A] PHOTODIODE CAPACITANCE [pF]

AMBIENT REJECTION AMBIENT LIGHT REJECTION

vs. FREQUENCY RESPONSE EXPOSURE SHIFT vs. AMBIENT INPUT
0
toc03 PD BIAS= 1, PD CAPACITANCE= 60 pF
toc04
4
-10 tINT = 117.3μ s
3.5
EXPOSURE SHIFT FROM DARK [nA]

tINT = 117.3 μ s LED_SETLNG = 6μ s

-20
3
AMBIENT REJECTION [dB]

-30
2.5
-40 2

-50 tINT = 14.8 μ s 1.5 tINT = 117.3μ s

-60 LED_SETLNG = 12μ s
1

-70 0.5

-80 0
10 100 1000 10000 0.1 1 10 100
FREQUENCY OF AMBIENT [Hz] AMBIENT LIGHT CURRENT INPUT [µA]

LED CURRENT vs. SAMPLE RATE

AFE POWER DISSIPATION SINGLE PULSE MODE
LP_MODE = 1 LEDxPA = 60mA
toc05 toc06
400 3500
TINT = 117.3μ s
DUAL CHANNEL tINT
350 TINT = 14.8μ s 3000
14.8 μs
LED AVERAGE CURRENT [µA]

DUAL CHANNEL
300 TINT = 117.3μ s 29.4 μs
2500
SINGLE CHANNEL 58.7 μs
POWER [uW]

250 TINT = 14.8μ s 117.3 μs

SINGLE CHANNEL 2000
200
1500
150
1000
100

50 500

0 0
0 100 200 300 0 100 200 300 400 500
SAMPLE RATE [Hz] SAMPLE RATE (SAMPLES PER SECOND)

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Typical Operating Characteristics (continued)

(VDD = 1.8V, VLED = 5.0V, GND = PGND = 0V, TA = +25°C, unless otherwise noted.)(TA = +25°C, unless otherwise noted.)

LED CURRENT VS. SAMPLE RATE

DUAL PULSE MODE
LEDxPA = 60mA AVERAGE V DD SHUTDOWN CURRENT
toc07 toc08
3500 100

3000 tINT
LED AVERAGE CURRENT [µA]

14.8μs
2500
29.4μs
58.7μs 10

CURRENT [µA]
117.3μs
2000 V DD =1.8V

1500
1
1000

500

0 0.1
0 50 100 150 200 250 -40 10 60 110
SAMPLE RATE (SAMPLES PER SECOND) AMBIENT TEMPERATURE (°C)

POWER SUPPLY REJECTION OF V DD

SUGGESTED LED
vs. FREQUENCY LSB/V
DRIVER HEADROOM VOLTAGE
toc09 VDD = 1.8V
1000 toc10
2500
900
RECOMENDED MINIMUM HEADROOM [mV]

800
2000
700

600
LSB/V

1500
500

400 1000
300

200 500
100

0 0
0x0 0x1 0x2 0x3 0.1 10 1000 100000
LED DRIVER RANGE SETTING (REGISTER CODE) FREQUENCY (Hz)

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Pin Configurations

MAX86140
1 2 3 4 5

VLED SCLK SDO SDI CSB

LED3_DRV INT GPIO1 GPIO2 VREF

LED2_DRV VDD_DIG GND_DIG GND_ANA PD_GND

LED1_DRV VDD_ANA PGND N.C. PD1_IN

BUMPS FACING DOWN, 0.4MM PITCH

1 2 3 4 5

LED1_DRV VDD_ANA PGND N.C. PD1_IN

LED2_DRV VDD_DIG GND_DIG GND_ANA PD_GND

LED3_DRV INT GPIO1 GPIO2 VREF

VLED SCLK SDO SDI CSB

BUMPS FACING UP, 0.4MM PITCH

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Pin Configurations (continued)

MAX86141
1 2 3 4 5

VLED SCLK SDO SDI CSB

LED3_DRV INT GPIO1 GPIO2 VREF

LED2_DRV VDD_DIG GND_DIG GND_ANA PD_GND

LED1_DRV VDD_ANA PGND PD2_IN PD1_IN

BUMPS FACING DOWN, 0.4MM PITCH

1 2 3 4 5

LED1_DRV VDD_ANA PGND PD2_IN PD1_IN

LED2_DRV VDD_DIG GND_DIG GND_ANA PD_GND

LED3_DRV INT GPIO1 GPIO2 VREF

VLED SCLK SDO SDI CSB

BUMPS FACING UP, 0.4MM PITCH

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Pin Description
PIN
NAME FUNCTION
MAX86140 MAX86141
Power
C2 C2 VDD_DIG Digital Logic Supply. Connect to externally-regulated supply. Bypass to GND_DIG
C3 C3 GND_DIG Digital Logic and Digital Pad Return. Connect to GND.
Analog Supply. Connect to externally-regulated supply.  Bypass with a 0.1μF capacitor as
D2 D2 VDD_ANA
close as possible to bump and a 10μF capacitor to GND_ANA.
C4 C4 GND_ANA Analog Power Return. Connect to GND.
LED Power Supply Input. Connect to external voltage supply. Bypass with a 10μF capacitor to
A1 A1 VLED
PGND.
D3 D3 PGND LED Power Return. Connect to GND.
Control Interface
A2 A2 SCLK SPI Clock
A3 A3 SDO SPI Data Ouput
A4 A4 SDI SPI Data Input
A5 A5 CSB SPI Chip select
B2 B2 INT Interrupt. Programmable open-drain Interrupt output signal pin (active-low).
B3 B3 GPIO1 General Purpose I/O. Open-drain when programmed as output (active-low).
B4 B4 GPIO2 General Purpose I/O. Open-drain when programmed as output (active-low).
Optical Pins
— D4 PD2_IN Photodiode Cathode Input
D5 D5 PD1_IN Photodiode Cathode Input
C5 C5 PD_GND Photodiode Anode
D1 D1 LED1_DRV LED Output Driver 1. Connect the LED cathode to LED1_DRV and its anode to the VLED supply.
C1 C1 LED2_DRV LED Output Driver 2. Connect the LED cathode to LED2_DRV and its anode to the VLED supply.
B1 B1 LED3_DRV LED Output Driver 3 Connect the LED cathode to LED3_DRV and its anode to the VLED supply.
Reference
B5 B5 VREF Internal Reference Decoupling Point. Bypass with a 1μF capacitor to GND_ANA.
N.C.
No Connection. Connect to unconnected PCB pad for mechanical stability. N.C. pins should
D4 N.C.
not be connected to any signal, power, or ground pins.

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

Detailed Description The MAX86140/MAX86141 supports Dynamic Power

The MAX86140/MAX86141 are complete integrated optical Down mode (Low-Power mode) in which the power
data acquisition systems, ideal for optical pulse oximetry consumption is decreased between samples. This mode
and heart rate detection applications. Both parts have is only supported for sample rates 128sps and below. For
been designed for the demanding requirements of mobile more details on the power consumption at each sample
and wearable devices and require minimal external hardware rates, refer to the Electrical Characteristics table.
components are necessary for integration into a wear- LED Driver
able device. They include high-resolution, optical readout
The MAX86140/MAX86141 integrates three precision LED
signal processing channels with robust ambient light
driver-current DACs that modulate LED pulses for a
cancellation and high-current LED driver DACs to form a
variety of optical measurements. The LED current DACs
complete optical readout signal chain.
have 8-bits of dynamic range with four programmable
The MAX86140/MAX86141 are fully adjustable through full-scale ranges of 31mA, 62mA, 94mA, and 124mA. The
software registers and the digital output data is stored LED drivers are low dropout current sources, allowing for
in a 128-word FIFO within the IC. The FIFO allows the low-noise, power-supply independent LED currents to be
MAX86140/MAX86141 to be connected to a microcontroller sourced at the lowest supply voltage possible; therefore
or processor on a shared bus, where the data is not being minimizing LED power consumption. The LED pulse width
read continuously from the MAX86140/MAX86141’s can be programmed from 14.8μs to 117.3μs to allow the
registers. Both operate in fully autonomous modes for low algorithms to optimize SpO2 and HR accuracy at the lowest
power battery applications. dynamic power consumption dictated by the application.
The MAX86140 consists of a single optical readout channel,
FIFO Configuration
while the MAX86141 incorporates dual optical readout
channels that operate simultaneously. Both parts have The FIFO is 128 sample depth and is designed to support
three LED drivers and are well suited for a wide variety of various data types, as shown in Table 2. Each sample
optical sensing applications. width is 3 bytes, which includes a 5-bit tag width. The
tag embedded in the FIFO_DATA is used to identify the
The MAX86140/MAX86141 operate on a 1.8V main source of each sample data. The description of each Tag
supply voltage, with a separate 3.1V to 5.0V LED driver is as shown in Table 3.
power supply. Both devices have flexible timing and shut-
down configurations as well as control of individual blocks LED Sequence Control (address 0x20 ~ 0x22)
so an optimized measurement can be made at minimum The data format in the FIFO, as well as the sequencing of
power levels. exposures, are controlled by the LED Sequence Registers
through LEDC1 through LEDC6. There are six LED
Optical Subsystem Sequence Data Items available, as shown in Table 1. The
The optical subsystem in the MAX86140/MAX86141 is exposure sequence cycles through the LED Sequence
composed of ambient light cancellation (ALC), a continuous- bit fields, starting from LEDC1 to LEDC6. The first LED
time sigma-delta ADC, and proprietary discrete time Sequence field set to NONE (0000) ends the sequence.
filter. ALC incorporates a proprietary scheme to cancel
ambient light generated photo diode current, allowing
the sensor to work in high ambient light conditions. The
optical ADC has programmable full-scale ranges of 4μA to
32μA. The internal ADC is a continuous time oversampling
sigma delta converter with 19-bit resolution. The ADC
output data rate can be programmed from 8sps (samples
per second) to 8192sps. The MAX86140 includes a
proprietary discrete time filter to reject 50Hz/60Hz
interference and changing residual ambient light from the
sensor measurements.

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Table 1. LED Sequence Control Registers

REGISTER DEFAULT
ADDRESS B7 B6 B5 B4 B3 B2 B1 B0
NAME VALUE
LED
0x20 Sequence 00 LEDC2[3:0] LEDC1[3:0]
Register 1
LED
0x21 Sequence 00 LEDC4[3:0] LEDC3[3:0]
Register 2
LED
0x22 Sequence 00 LEDC6[3:0] LEDC5[3:0]
Register 3

Table 2 lists the codes for exposures selected in the LED sequence control registers.
Table 2. LED Sequence Register Data Type
LEDCN[3:0] DATA TYPE
0000 NONE
0001 LED1
0010 LED2
0011 LED3
0100 LED1 and LED2 pulsed simultaneously
0101 LED1 and LED3 pulsed simultaneously
0110 LED2 and LED3 pulsed simultaneously
0111 LED1, LED2, and LED3 pulsed simultaneously
1000 Pilot on LED1
1001 DIRECT  AMBIENT
1010 LED4 (external mux control)
1011 LED5 (external mux control)
1100 LED6 (external mux control)
1101 Reserved
1110 Reserved
1111 Reserved

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Table 3 shows the format of the FIFO data along with the associated Tag. In a sample if a picket fence event is detected,
the predicted value is pushed to the FIFO along with its tag (PPFx_LEDCx_DATA).
Table 3. FIFO Data and Tag
TAG[4:0] DATA TYPE FIFO_DATA[23:0] COMMENTS
00001 PPG1_LEDC1_DATA LEDC1_DATA[18:0] If LEDC1 is non-zero
00010 PPG1_LEDC2_DATA LEDC2_DATA[18:0] If LEDC1 and LEDC2 are non-zero
00011 PPG1_LEDC3_DATA LEDC3_DATA[18:0] If LEDC1, LEDC2 and LEDC3 are non-zero
00100 PPG1_LEDC4_DATA LEDC4_DATA[18:0] If LEDC1, LEDC2, LEDC3, and LEDC4 are non-zero
If LEDC1, LEDC2, LEDC3, LEDC4, and LEDC5
00101 PPG1_LEDC5_DATA LEDC5_DATA[18:0]
are non-zero
If LEDC1, LEDC2, LEDC3, LEDC4, LEDC5,
00110 PPG1_LEDC6_DATA LEDC6_DATA[18:0]
and LEDC6 are non-zero
00111 PPG2_LEDC1_DATA LEDC1_DATA[18:0] If LEDC1 is non-zero
01000 PPG2_LEDC2_DATA LEDC2_DATA[18:0] If LEDC1 and LEDC2 are non-zero
01001 PPG2_LEDC3_DATA LEDC3_DATA[18:0] If LEDC1, LEDC2, and LEDC3 are non-zero
If LEDC1, LEDC2, LEDC3, and LEDC4 are
01010 PPG2_LEDC4_DATA LEDC4_DATA[18:0]
non-zero
If LEDC1, LEDC2, LEDC3, LEDC4, and LEDC5
01011 PPG2_LEDC5_DATA LEDC5_DATA[18:0]
are non-zero
If LEDC1, LEDC2, LEDC3, LEDC4, LEDC5,
01100 PPG2_LEDC6_DATA LEDC6_DATA[18:0]
and LEDC6 are non-zero
01101 PPF1_LEDC1_DATA LEDC1_DATA[18:0] If LEDC1 is non-zero (Picket Fence Event)
If LEDC1 and LEDC2 are non-zero (Picket
01110 PPF1_LEDC2_DATA LEDC2_DATA[18:0]
Fence Event)
If LEDC1, LEDC2, and LEDC3 are non-zero 
01111 PPF1_LEDC3_DATA LEDC3_DATA[18:0]
(Picket Fence Event)
10000 Reserved –
10001 Reserved –
10010 Reserved –
10011 PPF2_LEDC1_DATA LEDC1_DATA[18:0] If LEDC1 is non-zero (Picket Fence Event)
If LEDC1 and LEDC2 are non-zero
10100 PPF2_LEDC2_DATA LEDC2_DATA[18:0]
(Picket Fence Event)
If LEDC1, LEDC2, and LEDC3 are non-zero
10101 PPF2_LEDC3_DATA LEDC3_DATA[18:0]
(Picket Fence Event)
10110 Reserved –
10111 Reserved –
11000 Reserved –
11001 PROX1_DATA PROX1_DATA[18:0] Only PILOT LED1 for LEDC1 is used
11010 PROX2_DATA PROX2_DATA[18:0] Only PILOT LED1 for LEDC1 is used
11011 Reserved –
11100 Reserved –
11101 Reserved –
This tag indicates that there was an attempt to
11110 INVALID_DATA Don’t_care[18:0]
read an empty FIFO
11111 TIME_STAMP TIME_STAMP[18:0] If TIME_STAMP_EN = 1, this is TIME_STAMP

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There are seven registers that control how the FIFO is configured and read out. These registers are illustrated below.
Table 4. PPG Configuration
REGISTER
ADDRESS B7 B6 B5 B4 B3 B2 B1 B0
NAME
0x04 FIFO Write Pointer – FIFO_WR_PTR[6:0]
0x05 FIFO Read Pointer – FIFO_RD_PTR[6:0]
0x06 Overflow Counter – OVF_COUNTER[6:0]
FIFO Data
0x07 FIFO_DATA_COUNT[7:0]
Counter
FIFO Data
0x08 FIFO_DATA[7:0]
Register
FIFO
0x09 – FIFO_A_FULL[6:0]
Configuration 1
FIFO TIME_ FLUSH_ FIFO_ A_FULL_
0x0A – – FIFO_RO –
Configuration 2 STAMP_EN FIFO STAT_CLR TYPE

Write Pointer (Register 0x04)

FIFO_WR_PTR[6:0] points to the FIFO location where the next item will be written. This pointer advances for each item
pushed on to the FIFO by the internal conversion process. The write pointer is a 7-bit counter and will wrap around to
count 0x00 on the next item after count 0x7F.
Read Pointer (Register 0x05)
FIFO_RD_PTR[6:0] points to the location from where the next item from the FIFO will be read via the serial interface.
This advances each time an item is read from the FIFO. The read pointer can be both read and written to. This allows an
item to be reread from the FIFO if it has not already been overwritten. The read pointer is updated from a 7-bit counter
and will wrap around to count 0x00 from count 0x7F.
Overflow Counter (Register 0x06)
OVF_COUNTER[6:0] logs the number of items lost if the FIFO is not read in a timely fashion. This counter holds/
saturates at count value 0x7F. When a complete item is popped from the FIFO (when the read pointer advances), the
OVF_COUNTER is reset to zero. This counter is essentially a debug tool. It should be read immediately before reading
the FIFO in order to check if an overflow condition has occurred.
FIFO Data Counter (Register 0x07)
FIFO_DATA_COUNT[7:0] is a read-only register which holds the number of items available in the FIFO for the host to read.
This increments when a new item is pushed to the FIFO, and decrements when the host reads an item from the FIFO.
FIFO Data (Register 0x08)
FIFO_DATA[7:0] is a read-only register used to retrieve data from the FIFO. It is important to burst read the item from the
FIFO. Each item is three bytes. So burst reading three bytes at FIFO_DATA  register via the serial interface advances the
FIFO_RD_PTR. The format and data type of the data stored in the FIFO is determined by the Tag associated with data.
Readout from the FIFO follows a progression defined by LED Sequence Control registers as well. This configuration is
best illustrated by a few examples.
Assume it is desired to perform a SpO2 measurement and also monitor the ambient level on the photodiode to adjust the
IR and red LED intensity. To perform this measurement, configure the following registers:

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LED Sequence Control

LEDC1 = 0x1 (LED1 exposure)
LEDC2 = 0x2 (LED2 exposure)
LEDC3 = 0x9 (DIRECT AMBIENT exposure)
LEDC4 = 0x0 (NONE)
LEDC5 = 0x0 (NONE)
LEDC6 = 0x0 (NONE)
PPG Configuration
PPG1_ADC_RGE[1:0] (PPG1 Gain Range Control)
PPG2_ADC_RGE[1:0] (PPG2 Gain Range Control)
PPG_TINT[1:0] (LED Pulse-Width Control)
PPG_SR[3:0] (Sample Rate)
LED Pulse Amplitude
LED1_PA[7:0] (LED1 Drive Current)
LED2_PA[7:0] (LED2 Drive Current)
When done so the sample sequence and the data format in the FIFO will follow the following time/location sequence.
tag 1, PPG1 LED1 data
tag 7, PPG2 LED1 data
tag 2, PPG1 LED2 data
tag 8, PPG2 LED2 data
tag 3, PPG1 Ambient data
tag 9, PPG2 Ambient data
tag 1, PPG1 LED1 data
tag 7, PPG2 LED1 data
tag 2, PPG1 LED2 data
tag 8, PPG2 LED2 data
tag 3, PPG1 Ambient data
tag 9, PPG2 Ambient data
.
.
.
tag 1, PPG1 LED1 data
tag 7, PPG2 LED1 data
tag 2, PPG1 LED2 data
tag 8, PPG2 LED2 data
tag 3, PPG1 Ambient data
tag 9, PPG2 Ambient data
where:
PPGm LED1 data = the ambient corrected exposure data from LED1 in PPGm channel
PPGm LED2 data = the ambient corrected exposure data from LED2 in PPGm channel
PPGm Ambient data = the direct ambient sample in PPGm channel
m is 1 of PPG1 channel, and 2 for PPG2 channel
For a second example, assume it is desired to pulse LED1 and LED2 simultaneously while also monitoring the ambient level.
 LED Sequence Control
LEDC1 = 0x4 (LED1 and LED2 exposure)
LEDC2 = 0x9 (DIRECT AMBIENT exposure)
LEDC3 = 0x0 (NONE)
LEDC4 = 0x0 (NONE)
LEDC5 = 0x0 (NONE)
LEDC6 = 0x0 (NONE)

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In this case, the sequencing in the FIFO will then be:

tag 1, PPG1 LED1+LED2 data
tag 7, PPG2 LED1+LED2 data
tag 2, PPG 1 Ambient data
tag 8, PPG 2 Ambient data
tag 1, PPG1 LED1+LED2 data
tag 7, PPG2 LED1+LED2 data
tag 2, PPG1 Ambient data
tag 8, PPG2 Ambient data
.
.
.
tag 1, PPG1 LED1+LED2 data
tag 7, PPG2 LED1+LED2 data
tag 2, PPG1 Ambient data
tag 8, PPG2 Ambient data
where:
PPGm LED1+LED2 data = the ambient corrected exposure data from LED1 and LED2 for PPGm channel
PPGm Ambient data = the direct ambient corrected sample for PPGm channel
 The number of bytes of data for the PPG channel is given by: 2 x 3 x K x N
where:
K = the number of active exposures as defined in the LED Sequence Control registers 0x20, 0x21, and 0x22.
N = the number of samples in the FIFO
To calculate the number of available items one can perform the following pseudo-code:
read the OVF_COUNTER register
read the FIFO_DATA_COUNT register
if OVF_COUNTER == 0 //no overflow occurred
NUM_AVAILABLE_SAMPLES = FIFO_DATA_COUNT
else
NUM_AVAILABLE_SAMPLES = 128 // overflow occurred and data has been lost
endif
Table 6 shows the FIFO data format depends on the data type being stored. Optical data, whether full ambient corrected
LED exposure, ambient corrected proximity or direct ambient sampled data is left-justified, as shown in Table 6. Bits
F23:F19 of the FIFO word contains the tag that identifies the data.
Table 6. Optical FIFO Data Format
FIFO DATA FORMAT (FIFO_DATA[23:0])
ADC Tag (TAG[4:0]) ADC Value (FIFO_DATA[18:0])
Res F23 F22 F21 F20 F19 F18 F17 F16 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0
19-
T4 T3 T2 T1 T0 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 O0
bits

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FIFO_A_FULL (address 0x09) bit is set high, the A_FULL interrupt gets asserted only
The FIFO_A_FULL[6:0] field in the FIFO Configuration when a new A_FULL condition is detected. The interrupt
1 register (0x09) sets the watermark for the FIFO and gets cleared on Interrupt Status 1 register read, and does
determines when the A_FULL bit in the Interrupt_Status not re-assert for every sample until a new a-full condition
register (0x00) gets asserted. The A_FULL bit will be set is detected.
when the FIFO contains 128 minus FIFO_A_FULL[6:0] FIFO_STAT_CLR (Address 0x0A)
items. When the FIFO is almost full, if the A_FULL_EN The FIFO_STAT_CLR bit defines whether the A-FULL
mask bit in the Interrupt_Enable register (0x03) is set, then interrupt should get cleared by FIFO_DATA register read.
A_FULL bit gets asserted in the Interrupt Status 1 register If FIFO_STAT_CLR is set low, A_FULL and DATA_RDY
and this bit is routed to the INT pin on the serial interface. interrupts do not get cleared by FIFO_DATA register read
This condition should prompt the applications processor to but get cleared by status register read. If FIFO_STAT_CLR
read samples off of the FIFO before it fills. The A_FULL bit is set high, A_FULL and DATA_RDY interrupts get cleared
is cleared when the status register is read. by a FIFO_DATA register read or a status register read.
The application processor can read both the FIFO_WR_ FLUSH_FIFO (Address 0x0A)
PTR and FIFO_RD_PTR to calculate the number of items
available in the FIFO, or just read the OVF_COUNTER The FIFO Flush bit is used for flushing the FIFO. The
and FIFO_DATA_COUNT registers, and read as many FIFO becomes empty and the FIFO_WR_PTR[6:0],
items as it needs to empty the FIFO. Alternatively, if FIFO_RD_PTR[6:0], FIFO_DATA_COUNT[7:0] and
the applications always responds much faster than OVF_COUNTER[6:0] get reset to zero. FLUSH_FIFO is
the selected sample rate, it could just read 128 minus a self-clearing bit.
FIFO_A_FULL[6:0] items when it gets A_FULL interrupt TIME_STAMP_EN (Address 0x0A)
and be assured that all data from the FIFO are read. When TIME_STAMP_EN bit is set to 1, the 19 bits time
FIFO_RO (Address 0x0A) stamp gets pushed to the FIFO along with its Tag for
The FIFO_RO bit in the FIFO Configuration 2 register every 8 samples. This timestamp is useful for aligning
(0x0A) determines whether samples get pushed on to data from two devices after the host reads the FIFOs of
the FIFO when it is full. If push is enabled when FIFO is those devices. When TIME_STAMP_EN bit is set to 0, the
full, old samples are lost. If FIFO_RO is not set, the new sample counter is not pushed to FIFO.
sample is dropped and the FIFO is not updated.
A_FULL_TYPE (Address 0x0A)
The A_FIFO_TYPE bit defines the behavior of the A_FULL
interrupt. If the A_FIFO_TYPE bit is set low, the A_FULL
interrupt gets asserted when the A_FULL condition is detected
and cleared by status register read, but reasserts for every
sample if the A_FULL condition persists. If A_FIFO_TYPE

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Pseudo-Code Example of Initializing the Optical AFE

The following pseudo-code shows an example of configuring MAX86140/MAX86141 for a SpO2 applications, where
LED1 and LED2 are IR and red LED, respectively.

DEVICE OPEN
START;
// AFE Initialization
WRITE RESET[0] to 0x1; // Soft Reset (Register 0x0D[0])
DELAY 1ms;
WRITE SHDN[0] to 0x1; // Shutdown (Register 0x0D[1])
READ Interrupt_Status_1; // Clear Interrupt (Register 0x00)
READ Interrupt_Status_2; // Clear Interrupt (Register 0x01)
WRITE PPG_TINT[1:0] to 0x3; // Pulse Width = 123.8ms (Register 0x11[1:0])
WRITE PPG1_ADC_RGE1:0] to 0x2; // ADC Range = 16μA (Register 0x11[3:2])
WRITE PPG2_ADC_RGE1:0] to 0x2; // ADC Range = 16μA (Register 0x11[3:2])
// For MAX86141 when used in Dual Channel only
WRITE SMP_AVE[2:0] to 0x0; // Sample Averaging = 1 (Register 0x12[2:0])
WRITE PPG_SR[4:0] to 0x00; // Sample Rate = 25sps (Register 0x12[7:3])
WRITE LED_SETLNG[1:0] to 0x3; // LED Settling Time = 12ms (Register 0x13[7:6])
WRITE PD_BIAS1[2:0] to 0x01; // PD 1 Biasing for Cpd = 0~65pF (Register 0x15[2:0])
WRITE PD_BIAS2[2:0] to 0x01; // PD 1 Biasing for Cpd = 0~65pF (Register 0x15[2:0])
// For MAX86141 when used in Dual Channel only
WRITE LED1_RGE[1:0] to 0x3; // LED Driver 1 Range = 124mA (Register 0x15[2:0])
WRITE LED2_RGE[1:0] to 0x3; // LED Driver 2 Range = 124mA (Register 0x15[2:0])
WRITE LED1_DRV[1:0] to 0x20; // LED 1 Drive Current = 15.36mA (Register 0x23[7:0])
WRITE LED2_DRV[1:0] to 0x20; // LED 2 Drive Current = 15.36mA (Register 0x24[7:0])
WRITE LP_Mode[0] to 0x1; // Low Power mode enabled
// FIFO Configuration
WRITE FIFO_A_FULL[6:0] to 0xF; // FIFO INT triggered condition (Register 0x09[6:0])
WRITE FIFO_RO to 0x1; // FIFO Roll Over enabled (Register 0x0A[1])
WRITE A_FULL_EN to 0x1; // FIFO_A_FULL interrupt enabled (Register 0x02[7])
WRITE LEDC1[3:0] to 0x1; // LED1 exposure configured in time slot 1
WRITE LEDC2[3:0] to 0x2; // LED2 exposure configured in time slot 1
WRITE LEDC3[3:0] to 0x0;
WRITE LEDC4[3:0] to 0x0;
WRITE LEDC5[3:0] to 0x0;
WRITE LEDC6[3:0] to 0x0;
WRITE SHDN[0] to 0x0; // Start Sampling STOP;

Pseudo-Code for Interrupt Handling with FIFO_A_FULL

The following pseudo-code shows an example on handling the Interrupt when using A_FULL Interrupt.

Interrupt handlervoid irqHandler(void)

{
uint8_t intStatus;
//Read Status
ReadReg(0x00, &intStatus);

if ( intStatus& 0x80 ) { //A FULL RDY

device_data_read(); //Data Read Routine
}

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
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Pseudo-Code Example of Reading Data from FIFO

Example pseudo-code for reading data from FIFO when using single photodiode channel and two LED channels.

void device_data_read(void) {
uint8_t sampleCnt;
uint8_t regVal;
uint8_t dataBuf[128*2*3]; //128 FIFO samples, 2 channel, 3 byte/channel

int led1[32];
int led2[32];

ReadReg(0x07, &sampleCnt);

//Read FIFO
ReadFifo(dataBuf, sampleCnt * 3);
int i = 0;
for ( i = 0; i < sampleCnt; i++ ) {
led1[i] = ((dataBuf[i*6+0] << 16 ) | (dataBuf[i*6+1] << 8) | (dataBuf[i*6+2])) &
0x7ffff;
led2[i] = ((dataBuf[i*6+3] << 16 ) | (dataBuf[i*6+4] << 8) | (dataBuf[i*6+5])) &
0x7ffff;
}
}

Example pseudo-code for reading data from FIFO when using dual photodiode channels and two LED channels.

void device_data_read(void) {
uint8_t sampleCnt;
uint8_t regVal;
uint8_t dataBuf[128*2*2*3]; //128 FIFO samples, 2 channel, 2 PD, 3 byte/channel

int led1A[32];
int led1B[32];
int led2A[32];
int led2B[32];

ReadReg(0x07, &sampleCnt);

//Read FIFO
ReadFifo(dataBuf, sampleCnt * 3);
int i = 0;
for ( i = 0; i < sampleCnt; i++ ) {
led1A[i] = ((dataBuf[i*12+0] << 16 ) | (dataBuf[i*12+1] << 8) | (dataBuf[i*12+2])) &
0x7ffff; // LED1, PD1
led1B[i] = ((dataBuf[i*12+3] << 16 ) | (dataBuf[i*12+4] << 8) | (dataBuf[i*12+5])) &
0x7ffff; // LED1, PD2
led2A[i] = ((dataBuf[i*12+6] << 16 ) | (dataBuf[i*12+7] << 8) | (dataBuf[i*12+8])) &
0x7ffff; // LED2, PD1
led2B[i] = ((dataBuf[i*12+9] << 16 ) | (dataBuf[i*12+10] << 8) | (dataBuf[i*12+11]))
& 0x7ffff; // LED2, PD2
}
}

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
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Optical Timing
The MAX86140/MAX86141 optical controller is capable of
being configured to make a variety of measurements. Each
LED exposure is ambient light compensated before the
ADC conversion.
The controller can be configured to pulse one, two or three
LED drivers sequentially so as to make measurements at
multiple wavelengths as is done in a pulse oximetry 
measurements or simultaneously to drive multiple LEDs
such as is done with heart rate measurements on the wrist.
The controller is also configurable to measure direct
ambient level for every exposure sample. The direct
ambient measurement can be used to adjust the LED
drive level to compensate for increased noise levels when
high interfering ambient signals are present.
The following optical timing diagrams illustrate several
possible measurement configurations.

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
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One LED Pulsing with No Direct Ambient Sampling One LED Pulsing with Direct Ambient Sampling
The optical timing diagram below represents just LED1 The optical timing diagram below represents just LED1
pulsing during the exposure time with no direct ambient pulsing during the exposure time with direct ambient
sampling enabled. This timing mode would be used when sampling enabled. This timing mode would be used when
heart rate is being measured with a single green LED. heart rate is being measured with a single, green LED. In
In this mode a single optical sampled value will appear this mode a single optical sampled value followed by the
successively in the FIFO. ambient sampled value will appear successively in the FIFO.

tPW
LED1_DRV
tSAMPLE

LED2_DRV

LED3_DRV
tLED_SETLNG

LED1 LED1
PD_SAMPLE EXPOSURE EXPOSURE
SAMPLE SAMPLE

tINT
NOTE: LED is on when LEDx_DRV is low

Figure 1. Timing for LED1 Pulsing with No Direct Ambient Sampling

tPW
LED1_DRV
tSAMPLE

LED2_DRV

LED3_DRV
tLED_SETLNG

LED1 DIRECT LED1

PD_SAMPLE EXPOSURE AMBIENT EXPOSURE
SAMPLE SAMPLE SAMPLE

tINT tINT
NOTE: LED is on when LEDx_DRV is low

Figure 2. Timing for LED1 Pulsing with Direct Ambient Sampling

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
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Two LEDs Pulse Simultaneously with Direct All LED Pulsing Simultaneously with Direct
Ambient Sampling Ambient Sampling
The optical timing diagram below represents both LED1 The optical timing diagram below represents all three
and LED2 pulsing simultaneously with direct ambient LEDs pulsing simultaneously with direct ambient sampling
sampling enabled. This timing mode would be used when enabled. This timing mode would be used when heart
heart rate is being measured with two green LEDs. In rate is being measured with three green LEDs. In this
this mode a single optical sampled value followed by mode, a single optical sampled value, followed by the
the ambient sampled value will appear in successive the ambient sampled value, will appear in successive the
FIFO locations. The direct ambient sampling is typically FIFO locations. The direct ambient sampling is typically
used to compensate the LED drive levels as the optical used to compensate the LED drive levels as the optical
noise level can be elevated from ambient shot noise. noise level can be elevated from ambient shot noise.

tPW
LED1_DRV
tSAMPLE

tPW
LED2_DRV

LED3_DRV
tLED_SETLNG

LED1&2 DIRECT LED1&2

PD_SAMPLE EXPOSURE AMBIENT EXPOSURE
SAMPLE SAMPLE SAMPLE

tINT tINT
NOTE: LED is on when LEDx_DRV is low

Figure 3. Timing for LED1 and LED2 Pulsing Simultaneously with Direct Ambient Sampling

tPW
LED1_DRV
tSAMPLE

tPW
LED2_DRV

tPW
LED3_DRV
tLED_SETLNG

LED1&2&3 DIRECT LED1&2&3

PD_SAMPLE EXPOSURE AMBIENT EXPOSURE
SAMPLE SAMPLE SAMPLE

tINT tINT
NOTE: LED is on when LEDx_DRV is low

Figure 4. Timing for LED1, LED2, and LED3 Pulsing Simultaneously with Direct Ambient Sampling

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
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Two LEDs Pulse Sequentially with Direct Ambient optical sampled value for each LED will appear successively,
Sampling followed by the direct ambient sampled value in the FIFO.
The timing diagram below illustrates the optical All LEDs Pulse Sequential with Direct Ambient
timing when both LED1 and LED2 are enabled to pulse Sampling
sequentially and direct ambient sampling is also enabled.
The optical timing diagram below illustrates the three
This timing mode would be used when SpO2 is being
LEDs pulsing sequentially, followed by a direct ambient
measured with IR and red LEDs. The optical sampled
sample. This timing mode would be used when heart
value for each LED will appear successively, followed
rate on a green LED is combined with and SpO2
by the direct ambient sampled value in the FIFO. when
measurement using IR and red LEDs.
SpO2 is being measured with IR and red LEDs. The

tPW
LED1_DRV
tSAMPLE

tPW
LED2_DRV

LED3_DRV
tLED_SETLNG tLED_SETLNG

LED1 LED2 DIRECT LED1

PD_SAMPLE EXPOSURE EXPOSURE AMBIENT EXPOSURE
SAMPLE SAMPLE SAMPLE SAMPLE

tINT tINT tINT

NOTE: LED is on when LEDx_DRV is low

Figure 5. Timing for LED1 and LED2 Pulsing Sequentially with Direct Ambient Sampling

tPW
LED1_DRV
tSAMPLE

tPW
LED2_DRV

tPW
LED3_DRV
tLED_SETLNG tLED_SETLNG tLED_SETLNG

LED1 LED2 LED3 DIRECT LED1

PD_SAMPLE EXPOSURE EXPOSURE EXPOSURE AMBIENT EXPOSURE
SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE

tINT tINT tINT tINT

NOTE: LED is on when LEDx_DRV is low

Figure 6. Timing for LED1, LED2, and LED3 Pulsing Sequentially with Direct Ambient Sampling

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

GPIO Configuration
The MAX86140/MAX86141 support several means by which they can synchronize to external sensors, muxes, and be
extended to allow for more flexibility in the measurement configuration. This functionality is extended through the GPIO1
and GPIO2 pins and is selected by the GPIO CTRL bit field in the PPG SYNC Control register (0x10). The following
describes option and the functional state of GPIO1 and GPIO2 as well as the part behavior.
GPIO CTRL[3:0] 0000 and 0001: Stand Along With and Without External Mux

Table 7.  GPIO Mode 0000 and 0001

GPIO GPIO1 GPIO2
COMMENT
CTRL FUNCTION FUNCTION
GPIO1 will be active if any of the LEDCn[3:0] states A, B, or C are enabled in the exposure
sequence. In this case, GPIO1 will be low during exposures on LED4, LED5 or LED6, otherwise
Tristate or
0000 Disabled it will be high. If LEDCn[3:0] state A, B, or C is not enabled in the exposure sequence, GPIO1
Mux Control
will be tristate unless externally pulled up. GPIO2 is disabled. Sample and exposure timing is
controlled by the internal 32768Hz oscillator.
GPIO1 will be active if any of the LEDCn[3:0] states A, B, or C are enabled in the exposure sequence.
Input
In this case, GPIO1 will be low during exposures on LED4, LED5 or LED6; otherwise, it will be high.
Tristate or 32768Hz or
0001 If LEDCn[3:0] state A, B, or C is not enabled in the exposure sequence, GPIO1 will be tristate unless
Mux Control 32000Hz
externally pulled up. GPIO2 is an input 32768/32000Hz. Sample and exposure timing is controlled by
Clock Input
GPIO2 clock input.

1.8V
0.1μF 10μF
1μF
VDDIO
VDD_ANA

VDD_DIG
REF

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE
AMBIENT CANCELLATION SDO SDO
CANCELLATION
CSB CSB

PD1_IN SPI
RTC_CLK NOTE 1

19-BIT CURRENT ADC

INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
(MAX86141 ONLY)
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

NOTE 1: WHEN GPIO_CTRL[3:0] = 0001 ONLY.

Figure 7. Block Diagram for GPIO CTRL[3:0] 0000 and 0001 Without External Mux

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

tPW tPW tPW

LED1_DRV
tSAMPLE

tPW tPW
LED2_DRV

tPW tPW
LED3_DRV

Figure 8. Timing Diagram for GPIO CTRL[3:0] 0000 and 0001 Without External Mux

1.8V
0.1μF 10μF
1μF
VDDIO
VDD_ANA

VDD_DIG
REF

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE
AMBIENT CANCELLATION SDO SDO
CANCELLATION
CSB CSB

VDDIO
PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC

R
(MAX86141 ONLY)
GPIO1
GPIO2 RTC_CLK NOTE 1
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

3x2:1
MUX

NOTE 1: WHEN GPIO_CTRL[3:0] = 0001 only

Figure 9. Block Diagram for GPIO CTRL[3:0] 0000 and 0001 With External Mux

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

tPW tPW tPW

LED1_DRV
tSAMPLE

tPW tPW
LED2_DRV

tPW tPW
LED3_DRV

GPIO1

Figure 10. Timing Diagram for GPIO CTRL[3:0] 0000 and 0001 with External Mux

GPIO CTRL[3:0] 0010: Start of Sample Input with and without External Mux

Table 8. GPIO Mode 0010

GPIO CTRL GPIO1 FUNCTION GPIO2 FUNCTION COMMENT
GPIO1 is defined as a sample
trigger input (Slave). This input
can come from an external source
or from another MAX86140/
MAX86141 in master sample
mode. GPIO2 will be active if any
of the LEDCn[3:0] states A, B, or
C are enabled in the exposure
Input Tristate or
0010 sequence. In this case, GPIO2
Sample Trigger Mux Control
will be low during exposures on
LED4, LED5 or LED6, otherwise
it will be high. If LEDCn[3:0] state
A, B, or C is not enabled in the
exposure sequence, GPIO2 will
be tristate unless externally pulled
up. Exposure timing is controlled
by internal oscillator.

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

1.8V
0.1μF 10μF
1μF
VDDIO

VDD_ANA

VDD_DIG
REF

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE
AMBIENT CANCELLATION SDO SDO
CANCELLATION
CSB CSB

PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
(MAX86141 ONLY) SAMPLE INPUT
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

Figure 11. Block Diagram for GPIO CTRL[3:0] 0010 Without External Mux

tPW tPW tPW

LED1_DRV
tSAMPLE

tPW tPW
LED2_DRV

tPW tPW
LED3_DRV

GPIO1
Sample Input

Figure 12. Timing Diagram for GPIO CTRL[3:0] 0010 Without External Mux

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

1.8V
0.1μF 10μF
1μF
VDDIO

VDD_ANA

VDD_DIG
REF

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE
AMBIENT CANCELLATION SDO SDO
CANCELLATION
CSB CSB

SAMPLE INPUT
PD1_IN SPI
19-BIT CURRENT ADC VDDIO
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
(MAX86141 ONLY)
GPIO1

R
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

3x2:1
MUX

Figure 13. Block Diagram for GPIO CTRL[3:0] 0010 with External Mux

tPW tPW tPW

LED1_DRV
tSAMPLE

tPW tPW
LED2_DRV

tPW tPW
LED3_DRV

GPIO1
Sample Input

GPIO2

Figure 14. Timing Diagram for GPIO CTRL[3:0] 0010 with External Mux

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

GPIO CTRL[3:0] 0011: Start of Sample Input with External Clock

Table 9. GPIO Mode 0011
GPIO1
GPIO CTRL GPIO2 FUNCTION COMMENT
FUNCTION
GPIO1 is defined as a sample
trigger input (Slave). This input
can come from an external source
Input
Input or from another MAX86140/
0011 32768Hz
Sample Trigger MAX86141 in master sample mode.
or 32000Hz Clock Input
GPIO2 is an input 32768/32000Hz
clock input. Exposure timing is
controlled by GPIO2 clock input.

1.8V
0.1μF 10μF
1μF
VDDIO
VDD_ANA

VDD_DIG
REF

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE
AMBIENT CANCELLATION SDO SDO
CANCELLATION
CSB CSB

PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
(MAX86141 ONLY) SAMPLE INPUT
GPIO1
GPIO2 RTC_CLK
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

Figure 15. Block Diagram for GPIO CTRL[3:0] 0011

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

tPW tPW tPW

LED1_DRV
tSAMPLE

tPW tPW
LED2_DRV

tPW tPW
LED3_DRV

GPIO1
Sample Input

Figure 16. Timing Diagram for GPIO CTRL[3:0] 0011

GPIO CTRL[3:0] 0100: Start of Sample Output With and Without External Mux
Table 10. GPIO Mode 0100
GPIO1
GPIO CTRL GPIO2 FUNCTION COMMENT
FUNCTION
GPIO1 is defined as a master
sample output. The GPIO1 output
can be used to trigger a second
sensor. When used with a second
MAX86140/MAX86141 set to slave
sample mode, the master sample
timing will drive slave sample time.
GPIO2 will be active if any of the
LEDCn[3:0] states A, B, or C are
Active Output Tristate or
0100 enabled in the exposure sequence.
Master Sample Output Mux Control
In this case, GPIO2 will be low
during exposures on LED4, LED5
or LED6, otherwise it will be high. If
LEDCn[3:0] state A, B, or C is not
enabled in the exposure sequence,
GPIO2 will be tristate unless
externally pulled up. Sample and
exposure timing is controlled by
internal oscillator.

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

1.8V
0.1μF 10μF
1μF
VDDIO

VDD_ANA

VDD_DIG
REF

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE
AMBIENT CANCELLATION SDO SDO
CANCELLATION
CSB CSB

VDDIO
PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC

R
(MAX86141 ONLY) SAMPLE OUTPUT
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

Figure 17. Block Diagram for GPIO CTRL[3:0] 0100 Without External Mux

tPW tPW tPW

LED1_DRV
tSAMPLE

tPW tPW
LED2_DRV

tPW tPW
LED3_DRV

GPIO1
Sample Output

Figure 18. Timing Diagram for GPIO CTRL[3:0] 0100 Without External Mux

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

1.8V
0.1μF 10μF
1μF
VDDIO

VDD_ANA

VDD_DIG
REF

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE
AMBIENT CANCELLATION SDO SDO
CANCELLATION
CSB CSB

VDDIO
PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC

R
(MAX86141 ONLY) SAMPLE OUTPUT
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

3x2:1
MUX

Figure 19. Block Diagram for GPIO CTRL[3:0] 0100 with External Mux

tPW tPW tPW

LED1_DRV
tSAMPLE

tPW tPW
LED2_DRV

tPW tPW
LED3_DRV

GPIO1
Sample Output

GPIO2

Figure 20. Timing Diagram for GPIO CTRL[3:0] 0100 with External Mux

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

GPIO CTRL[3:0] 0101: Start of Sample Output with RTC Input Clock
Table 11. GPIO Mode 0101
GPIO1
GPIO CTRL GPIO2 FUNCTION COMMENT
FUNCTION
GPIO1 is defined as a master
sample output. The GPIO1 output
can be used to trigger a second
sensor. When used with a second
Active Output Input MAX86140/MAX86141 set to slave
0101
Master Sample Output 32768/32000Hz Clock Input sample mode, the master sample
timing will drive slave sample time.
GPIO2 is an input 32768/32000Hz.
Exposure timing is controlled by
GPIO2 clock input.

1.8V
0.1μF 10μF
1μF
VDDIO
VDD_ANA

VDD_DIG
REF

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE
AMBIENT CANCELLATION SDO SDO
CANCELLATION
CSB CSB

VDDIO
PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
R

(MAX86141 ONLY) SAMPLE OUTPUT

GPIO1
GPIO2 RTC_CLK
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

Figure 21. Block Diagram for GPIO CTRL[3:0] 0101

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

tPW tPW tPW

LED1_DRV
tSAMPLE

tPW tPW
LED2_DRV

tPW tPW
LED3_DRV

GPIO1
Sample Output

Figure 22. Timing Diagram for GPIO CTRL[3:0] 0101

GPIO CTRL[3:0] 0110 and 0111: Master/Slave with External Mux

Table 12. GPIO Mode 0110 and 0111
GPIO GPIO1 GPIO2
COMMENT
CTRL FUNCTION FUNCTION
GPIO1 is defined as an exposure trigger input (Slave). This input can come from an external
source or from another MAX86140 in master sample mode. Both sample and exposure
Input
Tristate or timing is controlled by the GPIO1 input. GPIO2 will be active if any of the LEDCn[3:0] states
0110 Exposure
Mux Control A, B, or C are enabled in the exposure sequence. In this case, GPIO2 will be high during
Trigger
exposures on LED4, LED5 or LED6, otherwise it will be low. If LEDCn[3:0] state A, B, or C is
not enabled in the exposure sequence, GPIO2 will be tristate.
GPIO1 is defined as a master sample output. The GPIO1 output can be used to trigger
Active and second sensor. When used with a second MAX86140 set to slave exposure mode, the
Output master exposure timing will drive slave exposure time. GPIO2 will be active if any of the
Tristate or
0111 Master LEDCn[3:0] states A, B, or C are enabled in the exposure sequence. In this case, GPIO2 will
Mux Control
Exposure be high during exposures on LED4, LED5 or LED6, otherwise it will be low. If LEDCn[3:0]
Output state A, B, or C is not enabled in the exposure sequence, GPIO2 will be tristate. Sample and
exposure time is controlled internally

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

1.8V
0.1μF 10μF
1μF VDDIO

VDD_ANA

VDD_DIG
REF
MASTER

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE SDO SDO
AMBIENT CANCELLATION
CANCELLATION CSB CSB

PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
(MAX86141 ONLY)
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

1.8V
0.1μF 10μF
1μF
VDD_ANA

VDD_DIG
REF

SLAVE

DIE TEMP
REFERENCE INT
12-BIT ADC
SCLK
SDI
DIGITAL NOISE SDO
AMBIENT CANCELLATION
CANCELLATION CSB

VDDIO
PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
R

(MAX86141 ONLY)
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

3x2:1
MUX

Figure 23. Block Diagram for GPIO CTRL[3:0] 0110 and 0111 with A Single External Mux

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

1.8V
0.1μF 10μF
1μF VDDIO

VDD_ANA

VDD_DIG
REF
MASTER

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE SDO SDO
AMBIENT CANCELLATION
CANCELLATION CSB CSB

PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
(MAX86141 ONLY)
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
VDDIO
PGND

GND_ANA

3x2:1 GND_DIG
MUX

R
R
1.8V
0.1μF 10μF
1μF
VDD_ANA

VDD_DIG
REF

SLAVE

DIE TEMP
REFERENCE INT
12-BIT ADC
SCLK
SDI
DIGITAL NOISE SDO
AMBIENT CANCELLATION
CANCELLATION CSB

PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128- WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
(MAX86141 ONLY)
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

3x2:1
MUX

Figure 24. Block Diagram for GPIO CTRL[3:0] 0110 and 0111 With Two External Muxes

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

tPW tPW tPW

LED1_DRV
MASTER & SLAVE
tSAMPLE

tPW tPW
LED2_DRV
MASTER & SLAVE

tPW tPW
LED3_DRV
MASTER & SLAVE

GPIO1
MASTER

GPIO2
MASTER & SLAVE

Figure 25. Timing Diagram for GPIO CTRL[3:0] 0110 and 0111 With External Mux

GPIO CTRL[3:0] 0110 and 1000: Master/Slave with and without External Mux
Table 13. GPIO Mode 0110 and 1000
GPIO GPIO1 GPIO2
COMMENT
CTRL FUNCTION FUNCTION
GPIO1 is defined as an exposure trigger input (Slave). This input can come from an
external source or from another MAX86140/MAX86141 in master sample mode. Both
Input sample and exposure timing is controlled by the GPIO1 input. GPIO2 will be active if any
Tristate or
0110 Exposure of the LEDCn[3:0] states A, B, or C are enabled in the exposure sequence. In this case,
Mux Control
Trigger GPIO2 will be low during exposures on LED4, LED5, or LED6, otherwise it will be high.
If LEDCn[3:0] state A, B, or C is not enabled in the exposure sequence, GPIO2 will be
tristate unless externally pulled up.
Active
GPIO1 is defined as a master sample output. The GPIO1 output can be used to trigger
Output Input
and second sensor. When used with a second MAX86140 /MAX86141 set to slave
1000 Master 32768/32000Hz
exposure mode, the master exposure timing will drive slave exposure time. GPIO2 is an
Exposure Clock Input
input 32768/32000Hz. Sample and exposure timing is controlled by GPIO2 clock input.
Output

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

1.8V
0.1μF 10μF
1μF VDDIO

VDD_ANA

VDD_DIG
REF
MASTER

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE SDO SDO
AMBIENT CANCELLATION
CANCELLATION CSB CSB

PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE

RTC_CLK NOTE 1
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
(MAX86141 ONLY)
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

1.8V
0.1μF 10μF
1μF
VDD_ANA

VDD_DIG
REF

SLAVE

DIE TEMP
REFERENCE INT
12-BIT ADC
SCLK
SDI
DIGITAL NOISE SDO
AMBIENT CANCELLATION
CANCELLATION CSB

VDDIO
PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
R

(MAX86141 ONLY)
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

NOTE 1: WHEN GPIO_CTRL[3:0] = 1000 ONLY

Figure 26. Block Diagram for GPIO CTRL[3:0] 0110 and 1000 Without External Mux

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MAX86140/ Best-in-Class Optical Pulse Oximeter and
MAX86141 Heart-Rate Sensor for Wearable Health

tPW tPW tPW

LED1_DRV
MASTER & SLAVE
tSAMPLE

tPW tPW
LED2_DRV
MASTER & SLAVE

tPW tPW
LED3_DRV
MASTER & SLAVE

GPIO1
MASTER

Figure 27. Timing Diagram for GPIO CTRL[3:0] 0110 and 1000 Without External Mux

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1.8V
0.1μF 10μF
1μF VDDIO

VDD_ANA

VDD_DIG
REF
MASTER

R
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE SDO SDO
AMBIENT CANCELLATION
CANCELLATION CSB CSB

PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
128-WORD

RTC_CLK note1
PD_GND
FIFO
PD2_IN 19-BIT CURRENT ADC
(MAX86141 ONLY)
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

1.8V
0.1μF 10μF
1μF
VDD_ANA

VDD_DIG
REF

SLAVE

DIE TEMP
REFERENCE INT
12-BIT ADC
SCLK
SDI
DIGITAL NOISE SDO
AMBIENT CANCELLATION
CANCELLATION CSB

VDDIO
PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
R

(MAX86141 ONLY)
GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

VBAT
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

3x2:1
MUX

NOTE 1: WHEN GPIO_CTRL[3:0] = 1000 ONLY

Figure 28. Block Diagram for GPIO CTRL[3:0] 0110 and 1000 With External Mux

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tPW tPW tPW

LED1_DRV
MASTER & SLAVE
tSAMPLE

tPW tPW
LED2_DRV
MASTER & SLAVE

tPW tPW
LED3_DRV
MASTER & SLAVE

GPIO1
MASTER

GPIO2
SLAVE

Figure 29. Timing Diagram for GPIO CTRL[3:0] 0110 and 1000 with External Mux

GPIO CTRL[3:0] 1001 Hardware Sync

Table 14. GPIO Mode 1001
GPIO GPIO1 GPIO2
COMMENT
CTRL FUNCTION FUNCTION
Input GPIO1 is defined as a start of sample sync input. The rising edge of GPIO1 causes
Input
32768Hz the present sample sequence to be terminated and reinitiated on the next rising edge
1001 HW_FORCE_
or 32000Hz of GPIO2 input. GPIO2 is an input 32768/32000Hz. Sample and exposure timing is
SYNC
Clock Input controlled by GPIO2 clock input.

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Proximity Mode Function When the proximity mode is enabled and the measurement
The MAX86140/MAX86141 includes an optical proximity assigned to LEDC1 with the LED current in PILOT_
function that could significantly reduce energy PA exceeds the PROX_INT_THRESH, the MAX86140/
consumption and extend battery life when the sensor is MAX86141 will also generate a Proximity Detect Interrupt
not in contact with the skin. Proximity mode is enabled (register 0x01[4]). In such an event MAX86140/MAX86141
by setting PROX_INT_EN bit field to 1 in the Interrupt will switch to normal mode, changing the sample rate to
Enable 2 register (address 0x02[4]), setting a threshold that assigned in PPG Configuration 2 register (address
in the PROX_INT_THRESH register (address 0x14) and 0x12) bit field PPG_SR and the LED current assigned to
assigning an LED current in the PILOT_PA (address the measurement of LEDC1. Therefore, the MAX86140 is
0x29). Proximity mode also requires that LED Sequence able to switch to proximity mode and back to normal mode
Register 1, field LEDC1 (address [3:0]) to be assigned to without microprocessor interaction.
a specific measurement and that measurement is correctly The threshold applied to PROX_INT_THRESH should be
connected to a light source. The LEDC1 measurement is well below that of a usable signal at the maximum LED
used to detect the optical presents of a reflecting object current applied to LEDC1 but high enough to not be
in proximity mode and thus must be valid for proximity triggered by noise from distant objects. Further the
mode to work. current assigned to PILOT_PA should be much lower
When enabled, the Proximity Detect Interrupt (register than that assigned to LEDx_PA in normal mode. This
0x01[4]) will be asserted and proximity mode will be will ensure that the signal obtained from LEDC1 will drop
entered when the value of the measurement assigned significantly when entering proximity mode, thus providing
to LEDC1 drops below the PROX_INT_THRESH. When enough hysteresis to eliminate multiple interrupts being
entering proximity mode, the MAX86140/MAX86141 will generated at the proximity/normal mode transition.
drop the current to the LED(s) assigned to LEDC1 to To guarantee that MAX86140/MAX86141 will successfully
PILOT_PA value, reduce the sample rate to 8sps and transition from proximity mode to normal mode, the
operates in Low Power mode. The intent here is to both PROX_INT_THRESH should be low enough and the
reduce the consumed LED current and MAX86140/ PILOT_PA high enough to ensure that the device mounted
MAX86141 power to a minimum during situations where on the darkest of skins will return a signal above the
there is no reflective returned signal. It is also intended to PROX_INT_THRESH at the PILOT_PA current.
reduce the emitted light to a minimum or even below that Note that proximity mode is only available to LEDC1
perceivable by the human eye. measurements that are made with PD1_IN optical channel
without an external mux. When proximity mode is active,
LEDC2~LEDC6 will be ignored. The threshold applied to
PROX_INT_THRESH register are in units of 2048LSBs.

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Sensor Initialized with

PROX mode on
(PROX_INT_EN=1)

PROX mode
(LED assigned to LEDC1
turned on based on
PILOT_PA settings) Note1
Remains in
PROX mode
NO

ADC Count
> Proximity Mode
ThresholdNote2?

YES (Object detected)

PROX_INT
asserted Exit PROX Mode
+
PROX_INT Cleared by reading
Interrupt Status1 Register
Enter the Normal Data Acquisition
+
Based note3 FIFO_DATA Flushed

Re-enter
PROX mode Host read out
FIFO_DATA

NO

ADC Count
< Proximity Mode
ThresholdNote2? Enter PROX Mode
+
PROX_INT Cleared by reading
Interrupt Status1 Register
+
PROX_INT FIFO_DATA Flushed
asserted

Note 1: Sample Rate= 8sps, and operates in Low Power Mode during PROX mode
.
Note 2: Proximity Mode Threshold= PROX_INT_THRESH* 2048
Note 3: Configurations as defined in LEDx_PA[7:0] and PPG_SR[4:0]

Figure 30. Proximity Function Flow Diagram

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Picket Fence Detect-and-Replace Function simply the previous ADC converted point. If PF_ORDER
Under typical situations, the rate of change of ambient = 1, the predicted point is a least square fit extrapolation
light is such that the ambient signal level during exposure based on the previous four picket fence outputs, which,
can be accurately predicted and high levels of ambient under normal circumstances, is identical to the ADC
rejection are obtained. However, it is possible to have converted inputs.
situations where the ambient light level changes extremely The threshold used in detecting a picket fence event
rapidly, for example when in a car with direct sunlight is a low passed version of the running estimation error
exposure passes under a bridge and into a dark shadow. computed above times a multiplier. The multiplier used
In these situations, it is possible for the MAX86140/ is set by the THRESHOLD_SIGMA_MULT (address
MAX86141 ambient light correction (ALC) circuit to fail 0x16[1:0]) bits and can be 4, 8, 16, or 32 times the
and produce and erroneous estimation of the ambient light running low-passed filter output of the estimation error.
during the exposure interval. The MAX86140/MAX86141 The low-pass filter function is controlled by two parameters,
has a built-in algorithm, called the picket fence function, the IIR_TC (address 0x16[5:4]) bits and IIR_INIT_VALUE
that can correct for these extreme conditions resultant (address 0x16[3:2]) bits. The IIR_TC bits control the filters
failure of the ALC circuit. time constant and are adjustable from 8 to 64 samples.
The picket fence function works on the basis that the The IIR_INIT_VALUE bits control the initial values for the
extreme conditions causing a failure of the ALC are IIR low pass filter when the algorithm is initialized.
rare events. These events resulting in a large deviation When a picket fence event is detected, the option of how
from the past sample history of a normal PPG riding to extrapolate the correct point is again controlled by the
on a motion effect signal, which normally would change PF_ORDER bit. This point can be identical as the previous
relatively slowly with respect to the sampling interval. point (PF_ORDER = 0) or a least square fit extrapola-
Under these conditions, it is possible to detect sample tion based on the previous four ADC converted points
values that are well outside the normal sample to sample (PF_ORDER = 1).
deviation and replace those samples with an extrapolated
value based on the relatively recent history of samples. Figure 31 below illustrates the function in block
diagram form. If the picket fence algorithm is enabled
The picket fence function is enabled by setting PF_ (bit PF_ENABLE = 1), the input from the ADC, s(n)
ENABLE (address 0x16[7]) bit to 1. The power on reset generates p(n) in a way that is dependent on the value
default of MAX86140/MAX86141 has the picket fence of the PF_ORDER bit. Value s(n) is subtracted from p(n)
function disabled. The function begins with detecting a and turned into a positive number d(n) and fed into the
picket fence event. Detection is done by taking the absolute IIR low-pass filter producing value lpf(n). The output of the
value of the difference between the present ADC low pass filter lpf(n) is then multiplied by a user constant,
converted value a predicted point, called an estimation THRESHOLD_SIGMA_MULT to produce the picket fence
error, and comparing this estimation error to a threshold. threshold, PFT(n). The value d(n) is then compared to this
If the estimation error exceeds the threshold, then the threshold and if greater than the PFT(n), the point s(n) is
present ADC converted point is considered a picket fence replaced with the point p(n).
event.
The predicted point referred to above is computed in one
of two ways, set by the value in the PF_ORDER (address
0x16[6]) bit. If PF_ORDER = 0 the predicted point is

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s(n) p(n) note1

INPUT SAMPLE PREDICTED SAMPLE
IIR_INIT_VALUE

- IIR LOW-FILTER

IIR_TC

d(n) note2 lpf(n)

THRESHOLD_SIGMA_MULT

Picket Event Not Detected Picket Fence Threshold,

NO d(n) > PFT ?
DOUT=s(n) PFT(n)

YES

Picket Event Detected

DOUT=p(n)

Note 1: If PG_ORDER = 0, p(n) = s(n-1). If PG_ORDER = 1, p(n) = s(n - 1) + 0.5s(n - 2) - 0.5s(n - 4)

Note 2: d(n) = ABS [ p(n) - s(n) ]

Figure 31. Picket Fence Function Flow

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This scheme essentially produces a threshold that tracks trace is the real ADC sample points, the red traces are
the past returned optical signal with a band width based the output of the low-pass filter of the error estimation
on the past historical change sample to sample. Figure 32 mirrored around the ADC points and the blue traces are
below illustrates graphically how the threshold detection the threshold values.
scheme works on a real PPG signal. Note that the black

# 10
5 Picket Fence Algorithm Variables

Raw PPG
1.46 PPG+Estimation Error
PPG-Estimation Error
PPG+Threshod
PPG-Threshold
1.44

1.42

1.4

1.38
ADC Codes (LSB)

1.36

1.34

1.32 Transient That Does Qualify

As A Picket Fence Event

1.3

1.28 Transient That Does Qualify

As A Picket Fence Event

18 20 22 24 26 28 30 32 34 36
Time (sec)

Figure 32. Picket Fences Variables In A PPG Waveform

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The recommended settings for the picket fence algorithm The combined VDD_ANA and VDD_DIG pins should
are the default power on reset values for all registers but then be decoupled with a 0.1µF or larger ceramic chip
THRESHOLD_SIGMA_MULT bits. Here it is recommended capacitor to the PCB ground plane. In addition, the VREF
that the 32x value 0x3 be used so only large excursions pin should be decoupled to the PCB GND plane with a
are classified as picket fence events. Lower values of 1.0μF ceramic capacitor. The voltage on the VREF pin
THRESHOLD_SIGMA_MULT can cause the algorithm to is nominally 1.21V, so a 6.3V rated ceramic capacitor
go off track with extremely noisy waveform. should be adequate for this purpose. It is recommended
that all decoupling caps use individual vias to the PCB
Photo Diode Biasing GND plane to avoid mutual impedance coupling between
The MAX86140/MAX86141 provides multiple photo diode decoupled supplies when sharing vias.
biasing options (see Table 15). These options allow the
The most critical aspect of the PCB layout of MAX86140/
MAX86140/MAX86141 to operate with a large range of
MAX86141 is the handling of the PD_IN and PD_
photo diode capacitance. The PDBIAS values adjust the
GND nodes. Parasitic capacitive coupling to the PD_IN
PD_IN bias point impedance to ensure that the photo
can result in additional noise being injected into the
diode settles rapidly enough to support the sample timing.
MAX86140/MAX86141 front-end. To minimize external
As the PDBIAS values goes up, the input-referred noise interference coupling to PD_IN, it is recommended that
of the MAX86140/MAX86141 goes up. The relationship the PD_IN node be fully shielded by the PD_GND node.
between PDBIAS and noise with increasing photo diode An example of this recommendation is shown below.
capacitance is illustrated in the "Input Referred Noise In the three layers shown, the PD_IN node is shielded
vs. PD Capacitance" graph of the Typical Operating with a coplanar PD_GND trace on the top layer, the
Characteristics section. Because of the increased noise layer on which the MAX86140/MAX86141 is mounted.
with PDBIAS, the lowest recommended PDBIAS values On the bottom layer, the photo diode cathode is entirely
should be used for a given photo diode capacitance. shielded with the PD_GND shield, which is also the photo
diode anode. Note, also, that the PD_GND shield also is
Layout Guidelines
extended below the photo diode. This is done because,
The MAX86140/MAX86141 is a high dynamic range analog in most photo diodes, the cathode is the bulk of the
front-end (AFE) and its performance can be adversely silicon. Therefore, shielding beneath the photo diode will
impacted by the physical printed circuit board (PCB) terminate the capacitance to the bulk or cathode side to
layout. Maxim recommends that all bypass recommendations the reference node (PD_GND). On the layer just above
in the pin table be followed. Specifically, it is the bottom (layer 5, in this case), the section of the GND
recommended that the VDD_ANA and VDD_DIG pins be plane has been opened up, connected to PD_GND to
shorted at the PCB. Maxim also recommends that GND_ shield the PD_IN node below the photo diode cathode
ANA, GND_DIG, and PGND be shorted to a single PCB contact. Finally, the PD_GND pin should only be attached
ground plane. These three pins have been assigned along to the PCB GND in only one point. This is shown on the
a single column so they can be shorted and combined into top layer.
a single via on the edge of the WLP grid array.

Table 15. Recommended PDBIAS Values Based on the Photo Diode Capacitance
PDBIAS<2:0> PHOTO DIODE CAPACITANCE
0x001 0pF to 65pF
0x101 65pF to 130pF
0x110 130pF to 260pF
0x111 260pF to 520pF
All other values Not recommended

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Figure 33. Example PCB Layout, Layer 1 (Top, MAX86140)

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Figure 34. Example PCB Layout, Layer 6 (Bottom, Optical Layer)

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Figure 35. Example PCB Layout, Layer5 (Ground Layer)

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SPI Timing sists of a one-byte register address (A[7:0]), followed by a

one-byte command word that defines the transaction as
Detailed SPI Timing
write or read, followed by a single-byte data word either
The detailed SPI timing is illustrated below. The timings written to, or read from, the register location provided in
indicated are all specified in the Electrical Characteristics the first byte.
table.
Write mode operations will be executed on the 24th SCLK
Single-Word SPI Register Read/Write Transaction rising edge using the first three bytes of data available. In
The MAX86140/MAX86141 is SPI/QSPI/Micro-wire/DSP write mode, any data supplied after the 24th SCLK
compatible. The operation of the SPI interface is shown rising edge will be ignored. Subsequent writes require
below. Data is strobed into the MAX86140/MAX86141 on CSB to deassert high and then assert low for the next write
the SCLK rising edge while clocked out on the SCLK falling command. A rising CSB edge preceding the 24th rising
edge. All single-word SPI read and write operations are edge of SCLK by tCSA (detailed SPI timing diagram), will
done in a 3-byte, 24 clock cycle SPI instruction framed by result in the transaction being aborted.
a CSB low interval. The content of the SPI operation con-

SDI A7 A6 A5 A4 A3 A2 A1 A0 R/W X DIN2 DIN1 DIN0 A7'

tDS
tDH tCP
SCLK 1 2 3 4 5 6 7 8 9 22 23 24 1'
tCSH0 tCSS0 tCL tCH tDOT tCSH1
CSB
tCSPW tCSF
SDO Z
DO2 DO2 DO0
tDOE tDOZ
GPIOx
tPLGPIOx

Figure 36. Detailed SPI Timing Diagram

CSB

SDI A7 A6 A5 A4 A3 A2 A1 A0 W DON’T CARE D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE

SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Z Command Executed Ignored
Z
SDO Edges

Figure 37. SPI Write Transaction

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Read mode operations will access the requested data read mode, the first byte being the register address, the
on the 16th SCLK rising edge, and present the MSB of second being a read command. The subsequent SCLKs
the requested data on the following SCLK falling edge, consist of FIFO data, 24 SCLKs per word. All words in
allowing the µC to latch the data MSB on the 17th SCLK the FIFO should be read with a single FIFO burst read
rising edge. Configuration and status registers are avail- command.
able through normal mode readback sequences. FIFO Each FIFO sample consists of 3 bytes per sample and thus
reads must be performed with a burst mode FIFO read requires 24 SCLKs per sample to readout. The first byte
(see SPI FIFO Burst Mode Read Transaction). If more (SCLK 16 to 23) consists of a tag indicating the data type
than 24 SCLK rising edges are provided in a normal of the subsequent bits. Following the tag is the MSBs of the
read sequence, the excess edges will be ignored and the subsequent data (MSB, MSB-1, and MSB-2). The next byte
device will read back zeros. (SCLK 24 to 31) consists of data bits MSB-3 to MSB-19. The
SPI FIFO Burst Mode Read Transaction final byte of each sample (SCLK 32 to 40) consists of the
The MAX86140/MAX86141 provides a FIFO burst read data LSB bits. The number of words in the FIFO depends
mode to increase data transfer efficiency. The first 16 on the FIFO configuration. See FIFO Configuration for
SCLK cycles operate exactly as described for the normal more details the FIFO configuration and readout.

CSB

SDI A7 A6 A5 A4 A3 A2 A1 A0 R DON’T CARE

Interrupt/Read Pointer Updated (If Applicable)
SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Z Ignored
Z Edges
SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0

Figure 38. SPI Read Transaction

CSB

SDI A7 A6 A5 A4 A3 A2 A1 A0 R DON’T CARE

SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Z
SDO

SCLK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 32 33 34 35 36 37 38 39 40

SDO T4A T3A T2A T1A T0A O18A O17A O16A O15A O14A O13A O12A O11A O10A O9A O8A O7A O6A O5A O4A O3A O2A O1A O0A

SCLK 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

SDO T4B T3B T2B T1B T0B O18B O17B O16B O15B O14B O13B O12B O11B O10B O9B O8B O7B O6B O5B O4B O3B O2B O1B O0B

CSB

SCLK N N+ N+ N+
9 17 24
Z
SDO T4C T3C T2C T1C T0C O18C O17C O16C O15C O14C O13C O12C O11C O10C O9C O8C O7C O6C O5C O4C O3C O2C O1C O0C

Figure 39. SPI FIFO Burst Mode Read Transaction

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Register Map
User Register Map
ADDRESS NAME MSB LSB
Status
DIE_
DATA_ ALC_ PROX_ LED_ VDD_ PWR_
0x00 Interrupt Status 1[7:0] A_FULL TEMP_
RDY OVF INT COMPB OOR RDY
RDY
SHA_
0x01 Interrupt Status 2[7:0] – – – – – – –
DONE
LED_ DIE_
A_FULL_ DATA_ ALC_ PROX_ VDD_
0x02 Interrupt Enable 1[7:0] COMPB_ TEMP_ –
EN RDY_EN OVF_EN INT_EN OOR_EN
EN RDY_EN
SHA_
0x03 Interrupt Enable 2[7:0] – – – – – – – DONE_
EN
FIFO
0x04 FIFO Write Pointer[7:0] – FIFO_WR_PTR[6:0]
0x05 FIFO Read Pointer[7:0] – FIFO_RD_PTR[6:0]
0x06 Over Flow Counter[7:0] – OVF_COUNTER[6:0]
0x07 FIFO Data Counter[7:0] FIFO_DATA_COUNT[7:0]
0x08 FIFO Data Register[7:0] FIFO_DATA[7:0]
FIFO Configuration
0x09 – FIFO_A_FULL[6:0]
1[7:0]
FIFO_
FIFO Configuration FLUSH_ A_FULL_ FIFO_
0x0A – – – STAT_ –
2[7:0] FIFO TYPE RO
CLR
System Control
SINGLE_ LP_
0x0D System Control[7:0] – – – – SHDN RESET
PPG MODE
PPG Configuration
TIME_ SW_
0x10 PPG Sync Control[7:0] STAMP_ – – FORCE_ GPIO_CTRL[3:0]
EN SYNC
PPG Configuration ALC_ ADD_ PPG2_ADC_ PPG1_ADC_
0x11 PPG_TINT[1:0]
1[7:0] DISABLE OFFSET RGE[1:0] RGE[1:0]
PPG Configuration
0x12 PPG_SR[4:0] SMP_AVE[2:0]
2[7:0]
DIG_
PPG Configuration BURST_
0x13 LED_SETLNG[1:0] FILT_ – – BURST_RATE[1:0]
3[7:0] EN
SEL
Prox Interrupt
0x14 PROX_INT_THRESH[7:0]
Threshold[7:0]
0x15 Photo Diode Bias[7:0] – PDBIAS2[2:0] – PDBIAS1[2:0]

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Register Map (continued)

ADDRESS NAME MSB LSB
PPG Picket Fence Detect and Replace
PF_ PF_ THRESHOLD_
0x16 Picket Fence[7:0] IIR_TC[1:0] IIR_INIT_VALUE[1:0]
ENABLE ORDER SIGMA_MULT[1:0]
LED Sequence Control
LED Sequence
0x20 LEDC2[3:0] LEDC1[3:0]
Register 1[7:0]
LED Sequence
0x21 LEDC4[3:0] LEDC3[3:0]
Register 2[7:0]
LED Sequence
0x22 LEDC6[3:0] LEDC5[3:0]
Register 3[7:0]
LED Pulse Amplitude
0x23 LED1 PA[7:0] LED1_DRV[7:0]
0x24 LED2 PA[7:0] LED2_DRV[7:0]
0x25 LED3_PA[7:0] LED3_DRV[7:0]
0x26 LED4 PA[7:0] LED4_DRV[7:0]
0x27 LED5 PA[7:0] LED5_DRV[7:0]
0x28 LED6 PA[7:0] LED6_DRV[7:0]
0x29 LED PILOT PA[7:0] PILOT_PA[7:0]
0x2A LED Range 1[7:0] – – LED3_RGE[1:0] LED2_RGE[1:0] LED1_RGE[1:0]
0x2B LED Range 2[7:0] – – LED6_RGE[1:0] LED5_RGE[1:0] LED4_RGE[1:0]
PPG1_HI_RES_DAC
S1_
HRES_
0x2C S1 HI RES DAC1[7:0] – S1_HRES_DAC1[5:0]
DAC1_
OVR
S2_
HRES_
0x2D S2 HI RES DAC1[7:0] – S2_HRES_DAC1[5:0]
DAC1_
OVR
S3_
HRES_
0x2E S3 HI RES DAC1[7:0] – S3_HRES_DAC1[5:0]
DAC1_
OVR
S4_
HRES_
0x2F S4 HI RES DAC1[7:0] – S4_HRES_DAC1[5:0]
DAC1_
OVR
S5_
HRES_
0x30 S5 HI RES DAC1[7:0] – S5_HRES_DAC1[5:0]
DAC1_
OVR
S6_
HRES_
0x31 S6 HI RES DAC1[7:0] – S6_HRES_DAC1[5:0]
DAC1_
OVR

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Register Map (continued)

ADDRESS NAME MSB LSB
PPG2_HI_RES_DAC
S1_
HRES_
0x32 S1 HI RES DAC2[7:0] – S1_HRES_DAC2[5:0]
DAC2_
OVR
S2_
HRES_
0x33 S2 HI RES DAC2[7:0] – S2_HRES_DAC2[5:0]
DAC2_
OVR
S3_
HRES_
0x34 S3 HI RES DAC2[7:0] – S3_HRES_DAC2[5:0]
DAC2_
OVR
S1_
HRES_
0x35 S4 HI RES DAC2[7:0] – S4_HRES_DAC2[5:0]
DAC2_
OVR
S2_
HRES_
0x36 S5 HI RES DAC2[7:0] – S5_HRES_DAC2[5:0]
DAC2_
OVR
S3_
HRES_
0x37 S6 HI RES DAC2[7:0] – S6_HRES_DAC2[5:0]
DAC2_
OVR
Die Temperature
Die Temperature TEMP_
0x40 – – – – – – –
Configuration[7:0] EN
Die Temperature
0x41 TEMP_INT[7:0]
Integer[7:0]
Die Temperature
0x42 – – – – TEMP_FRAC[3:0]
Fraction[7:0]
SHA256
0xF0 SHA Command[7:0] SHA_CMD[7:0]
SHA_
0xF1 SHA Configuration[7:0] – – – – – – SHA_EN
START
Memory
MEM_ BANK_
0xF2 Memory Control[7:0] – – – – – –
WR_EN SEL
0xF3 Memory Index[7:0] MEM_IDX[7:0]
0xF4 Memory Data[7:0] MEM_DATA[7:0]
Part ID
0xFF Part ID[7:0] PART_ID[7:0]

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Interrupt Status 1 (0x00)

BIT 7 6 5 4 3 2 1 0
LED_ DIE_TEMP_
Field A_FULL DATA_RDY ALC_OVF PROX_INT VDD_OOR PWR_RDY
COMPB RDY
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
Access Type Read Only Read Only Read Only Read Only Read Only Read Only Read Only Read Only

A_FULL
This is a read-only bit. This bit is cleared when the Interrupt Status 1 Register is read. It is also cleared when FIFO_
DATA register is read, if FIFO_STAT_CLR = 1.
VALUE ENUMERATION DECODE
0 OFF Normal Operation
Indicates that the FIFO buffer will overflow the threshold set by FIFO_A_FULL[6:0] on the
1 ON
next sample.

DATA_RDY
This is a read-only bit and it is cleared by reading the Interrupt Status 1 register (0x00). It is also cleared by reading
the FIFO_DATA register if FIFO_STAT_CLR = 1.
VALUE ENUMERATION DECODE
0 OFF Normal Operation
1 ON This interrupt triggers when there is a new data in the FIFO.

ALC_OVF
This is a read-only bit. The interrupt is cleared by reading the Interrupt Status 1 register (0x00).
VALUE ENUMERATION DECODE
0 OFF Normal Operation
This interrupt triggers when the ambient light cancellation function of the photodiode has
1 ON reached its maximum limit due to overflow, and therefore, ambient light is affecting the
output of the ADC.

PROX_INT
VALUE ENUMERATION DECODE
0 OFF Normal Operation
Indicates that the ADC reading of the LED configured in LEDC1 has crossed the proximity
threshold.
1 ON If PROX_INT_EN is 0, then the prox mode is disabled and the exposure sequence
configured in LED Sequence Control Registers begins immediately.
This bit is cleared when the Interrupt Status 1 Register is read.

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LED_COMPB
LED is not compliant. At the end of each sample, if the LED driver is not compliant, LED_COMPB interrupt is asserted
if LED_COMPB_EN is set to 1. It is a read-only bit and is cleared when the status register is read.
VALUE ENUMERATION DECODE
0 COMPLIANT LED driver is compliant
1 NOT_COMPLIANT LED driver is not compliant

DIE_TEMP_RDY
This is a read-only bit and is automatically cleared when the temperature data is read, or when the Interrupt Status 1
Register is read.
VALUE ENUMERATION DECODE
0 OFF Normal Operation
1 ON Indicates that the TEMP ADC has finished it's current conversion.

VDD_OOR
This is a read-only bit. It is automatically cleared when the Interrupt Status 1 register is read.
The detection circuitry has a 10ms delay time, and will continue to trigger as long as the VDD_ANA is out of range.
VALUE ENUMERATION DECODE
0 OFF Normal operation
1 ON Indicates that VDD_ANA is greater than 2.05V or less than 1.65V.

PWR_RDY
This is a read-only bit and indicates that VDD had gone below the UVLO threshold. This bit is not triggered by a soft
reset. This bit is cleared when either Interrupt Status 1 Register is read, or by setting SHDN bit to 1.
VALUE ENUMERATION DECODE
0 OFF Normal Operation
1 ON Indicates that VBATT went below the UVLO threshold.

Interrupt Status 2 (0x01)

BIT 7 6 5 4 3 2 1 0
Field – – – – – – – SHA_DONE
Reset – – – – – – – 0x0
Access Type – – – – – – – Read Only

SHA_DONE
SHA256 Authentication Done status bit is set to 1 when the authentication algorithm completes. This is a read-only bit
and gets cleared when the Status Register is read.
VALUE ENUMERATION DECODE
0x0 SHA Authentication not done
0x1 SHA Authentication done

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Interrupt Enable 1 (0x02)

BIT 7 6 5 4 3 2 1 0
DATA_ ALC_OVF_ PROX_INT_ LED_ DIE_TEMP_ VDD_OOR_
Field A_FULL_EN –
RDY_EN EN EN COMPB_EN RDY_EN EN
Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 –
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read Write, Read –

A_FULL_EN
VALUE ENUMERATION DECODE
0 OFF A_FULL interrupt is disabled
1 ON A_FULL interrupt in enabled

DATA_RDY_EN
VALUE ENUMERATION DECODE
0 OFF DATA_RDY interrupt is disabled
1 ON DATA_RDY interrupt is enabled.

ALC_OVF_EN
VALUE ENUMERATION DECODE
0 OFF ALC_OVF interrupt is disabled
1 ON ALC_OVF interrupt in enabled

PROX_INT_EN
When PROX_INT_EN is enabled, the exposure programmed in the LEDC1 Sequence Register is used for proximity
detection. If the ADC reading for this exposure is below 2048 times the threshold programmed in PROX_INT_THRESH
register, the device is in proximity mode. Otherwise, it is in normal mode.
When the device is in proximity mode, the sample rate used is 8Hz, and the device starts data acquisition in pilot mode,
using only one exposure of the LED programmed in LEDC1 register, and the LED current programmed in PILOT_PA reg-
ister.
When the device is in normal mode, the sample rate used is as defined under PPG_SR register, and the device starts
data acquisition in normal mode, using all the exposures programmed in the LED Sequence registers and appropriate
LED currents.
PROX_INT interrupt is asserted when the devices enters proximity mode or normal mode if PROX_INT_EN is
programmed to 1.

VALUE ENUMERATION DECODE

0 OFF Proximity mode and PROX_INT interrupt are disabled
1 ON Proximity mode and PROX_INT interrupt are enabled

LED_COMPB_EN
VALUE ENUMERATION DECODE
0 DISABLE LED_COMPB interrupt is disabled
1 ENABLE LED_COMPB interrupt is enabled

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DIE_TEMP_RDY_EN

VALUE ENUMERATION DECODE

0 OFF DIE_TEMP_RDY interrupt is disabled
1 ON DIE_TEMP_RDY interrupt is enabled

VDD_OOR_EN
VALUE ENUMERATION DECODE
0 OFF Disables the VDD_OVR interrupt
1 ON Enables the VDD_OVR interrupt

Interrupt Enable 2 (0x03)

BIT 7 6 5 4 3 2 1 0
SHA_
Field – – – – – – –
DONE_EN
Reset – – – – – – – 0x0
Access Type – – – – – – – Write, Read

SHA_DONE_EN
Enable SHA_DONE Interrupt
VALUE ENUMERATION DECODE
0x0 SHA_DONE interrupt disabled
0x1 SHA_DONE interrupt enabled

FIFO Write Pointer (0x04)

BIT 7 6 5 4 3 2 1 0
Field – FIFO_WR_PTR[6:0]
Reset – 0x0
Access Type – Read Only

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FIFO_WR_PTR
This points to the location where the next sample will be written. This pointer advances for each sample pushed on to
the circular FIFO.
See FIFO Configuration for details.
FIFO Read Pointer (0x05)
BIT 7 6 5 4 3 2 1 0
Field – FIFO_RD_PTR[6:0]
Reset – 0x0
Access Type – Write, Read

FIFO_RD_PTR
The FIFO Read Pointer points to the location from where the processor gets the next sample from the FIFO via the
serial interface. This advances each time a sample is popped from the circular FIFO.
The processor may also write to this pointer after reading the samples. This allows rereading (or retrying) samples from
the FIFO. However, writing to FIFO_RD_PTR may have adverse effects if it results in the FIFO being almost full.
Refer to FIFO Configuration for details.
Overflow Counter (0x06)
BIT 7 6 5 4 3 2 1 0
Field – OVF_COUNTER[6:0]
Reset – 0x0
Access Type – Read Only

OVF_COUNTER
When FIFO is full, any new samples will result in new or old samples getting lost, depending on FIFO_RO.
OVF_COUNTER counts the number of samples lost. It saturates at 0x7F.
Refer to FIFO Configuration for details.
FIFO Data Counter (0x07)
BIT 7 6 5 4 3 2 1 0
Field FIFO_DATA_COUNT[7:0]
Reset 0x0
Access Type Read Only

FIFO_DATA_COUNT
This is a read-only register that holds the number of items available in the FIFO for the host to read. This increments
when a new item is pushed to the FIFO and decrements when the host reads an item from the FIFO.
Refer to FIFO Configuration for details.

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FIFO Data Register (0x08)

BIT 7 6 5 4 3 2 1 0
Field FIFO_DATA[7:0]
Reset 0x0
Access Type Read Only

FIFO_DATA
This is a read-only register and is used to get data from the FIFO. Refer to FIFO Configuration for details.
FIFO Configuration 1 (0x09)

BIT 7 6 5 4 3 2 1 0
Field – FIFO_A_FULL[6:0]
Reset – 0x3F
Access Type – Write, Read

FIFO_A_FULL
These bits indicate how many new samples can be written to the FIFO before the interrupt is asserted. For example, if
set to 0xF, the interrupt triggers when there are 15 empty spaces left (113 entries), and so on.
Refer to FIFO Configuration for details.

FIFO_A_FULL<6:0> FREE SPACE BEFORE INTERRUPT # OF SAMPLES IN FIFO

0 0 128
1 1 127
2 2 126
3 3 125
---- ---- ----
126 126 2
127 127 1

FIFO Configuration 2 (0x0A)

BIT 7 6 5 4 3 2 1 0
FLUSH_ FIFO_ A_FULL_
Field – – – FIFO_RO –
FIFO STAT_CLR TYPE
Reset – – – 0x0 0x0 0x0 0x0 –
Access Type – – – Write, Read Write, Read Write, Read Write, Read –

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FLUSH_FIFO
When this bit is set to ‘1’, the FIFO gets flushed, FIFO_WR_PTR and FIFO_RD_PTR are reset to zero and FIFO_DATA_
COUNT becomes 0. The contents of the FIFO are lost.
FIFO_FLUSH is a self-clearing bit.
Refer to FIFO Configuration for details.
FIFO_STAT_CLR
This defines whether the A-FULL interrupt should get cleared by FIFO_DATA register read.
Refer to FIFO Configuration for details.
VALUE ENUMERATION DECODE
A_FULL and DATA_RDY interrupts do not get cleared by FIFO_DATA register read. They
0 RD_DATA_NOCLR
get cleared by status register read.
A_FULL and DATA_RDY interrupts get cleared by FIFO_DATA register read or status
1 RD_DATA_CLR
register read.

A_FULL_TYPE
This defines the behavior of the A_FULL interrupt.

VALUE ENUMERATION DECODE

A_FULL interrupt gets asserted when the a_full condition is detected. It is cleared by status
0 AFULL_RPT
register read, but re-asserts for every sample if the a_full condition persists.
A_FULL interrupt gets asserted only when the a_full condition is detected. The interrupt
1 AFULL_ONCE gets cleared on status register read, and does not re-assert for every sample until a new
a-full condition is detected.

FIFO_RO
Push enable when FIFO is full:
This bit controls the behavior of the FIFO when the FIFO becomes completely filled with data.
Push to FIFO is enabled when FIFO is full if FIFO_RO = 1 and old samples are lost. Both FIFO_WR_PTR increments for
each sample after the FIFO is full. FIFO_RD_PTR also increments for each sample pushed to the FIFO.
Push to FIFO is disabled when FIFO is full if FIFO_RO = 0 and new samples are lost. FIFO_WR_PTR does not increment for
each sample after the FIFO is full.
When the device is in PROX mode, push to FIFO is enabled independent of FIFO_RO setting.
Refer to FIFO Configuration for details.

VALUE ENUMERATION DECODE

0 OFF The FIFO stops on full.
1 ON The FIFO automatically rolls over on full.

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System Control (0x0D)

BIT 7 6 5 4 3 2 1 0
Field – – – – SINGLE_PPG LP_MODE SHDN RESET
Reset – – – – 0x0 0x0 0x0 0x0
Access Type – – – – Write, Read Write, Read Write, Read Write, Read

SINGLE_PPG
In signal PP devices, this bit is ignored. In dual PPG devices, if this bit is 0, use two PPG channels; otherwise, use only
PPG1 channel.
VALUE ENUMERATION DECODE
0x0 DUAL_PPG Both PPG channels are enabled
0x1 SINGLE_PPG Only PPG1 channel is enabled

LP_MODE
In low power mode, the sensor can be dynamically powered down between samples to conserve power. This dynamic power
down mode option only supports samples rates of 256sps and below.
VALUE ENUMERATION DECODE
0 OFF Dynamic power down is disabled.
Dynamic power down is enabled. The device automatically enters low power mode be-
1 ON tween samples for samples rates 256sps and below.
This mode is not available for higher sample rates.

SHDN
The part can be put into a power-save mode by setting this bit to one. While in power-save mode, all configuration reg-
isters retain their values, and write/read operations function as normal. All interrupts are cleared to zero in this mode.

VALUE ENUMERATION DECODE

0 OFF The part is in normal operation. No action taken.
The part can be put into a power-save mode by writing a ‘1’ to this bit. While in this mode
all configuration registers remain accessible and retain their data. ADC conversion data
contained in the registers are previous values. Writeable registers also remain accessible
1 ON
in shutdown. All interrupts are cleared. In this mode the oscillator is shutdown and the part
draws minimum current. If this bit is asserted during an active conversion then the conversion
is aborted.

RESET
When this bit is set, the part undergoes a forced power-on-reset sequence. All configuration, threshold, and data
registers including distributed registers are reset to their power-on-state. This bit then automatically becomes ‘0’ after
the reset sequence is completed.
VALUE ENUMERATION DECODE
0 OFF The part is in normal operation. No action taken.
The part undergoes a forced power-on-reset sequence. All configuration, threshold and
1 ON data registers including distributed registers are reset to their power-on-state. This bit then
automatically becomes ‘0’ after the reset sequence is completed.

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PPG Sync Control (0x10)

BIT 7 6 5 4 3 2 1 0
TIME_ SW_FORCE_
Field – – GPIO_CTRL[3:0]
STAMP_EN SYNC
Reset 0x0 – – 0x0 0x0
Access Type Write, Read – – Write, Read Write, Read

TIME_STAMP_EN
Enable pushing TIME_STAMP to FIFO. Refer to FIFO Configuration for details.
VALUE ENUMERATION DECODE
0x0 DISABLE TIME_STAMP is not pushed to FIFO
0x1 ENABLE TIME_STAMP is pushed to FIFO for a block of eight samples.

SW_FORCE_SYNC
Writing a 1 to this bit, aborts current sample and starts a new sample. This is a self clearing bit.
GPIO_CTRL
The table below shows how the two GPIO ports are control for different modes of operation.
When two devices are configured to work as master-slave device pairs, they have to be configured identical for the
following configuration register fields:
     • PPG_SR
     • PPG_TINT
     • SMP_AVE
     • TIME_STAMP_EN
     • FIFO_A_FULL
     • FIFO_ROLLS_ON_FULL
Number of LED Sequence Registers (LEDC1 to LEDC6) programmed should be same in both the devices. In Exposure
Trigger mode, if Ambient is programmed in one of the registers, it needs to be in the same LEDCx register in both the
devices.
GPIO_CTRL register for both the devices should be programmed to be either Sample Trigger or Exposure Trigger.
It is also important to configure the Slave first and then the Master.
DATA_RDY or A_FULL interrupt should be enabled only on the Master. When interrupt is asserted read the Master first
and then the Slave. Read same number of items from both devices.
Refer to GPIO Configuration for details.
GPIO_CTRL GPIO1 GPIO2
COMMENT
[3:0] FUNCTION FUNCTION
GPIO1 will be active if any of the LEDCn[3:0] states A, B, or C are enabled in the
exposure sequence. In this case, GPIO1 will be low during exposures on LED4, LED5, or
Tristate or
0000 Disabled LED6, otherwise it will be high. If LEDCn[3:0] state A, B, or C is not enabled in the
Mux Control
exposure sequence, GPIO1 will be tristate unless externally pulled up. GPIO2 is disabled.
Sample and exposure timing is controlled by the internal 32768Hz oscillator.
GPIO1 will be active if any of the LEDCn[3:0] states A, B, or C are enabled in the
Input
exposure sequence. In this case, GPIO1 will be low during exposures on LED4, LED5
Tristate or 32768Hz or
0001 or LED6, otherwise it will be high. If LEDCn[3:0] state A, B, or C is not enabled in the
Mux Control 32000Hz
exposure sequence, GPIO1 will be tristate unless externally pulled up. GPIO2 is an input
Clock Input
32768/32000Hz. Sample and exposure timing is controlled by GPIO2 clock input.

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GPIO_CTRL GPIO1 GPIO2

COMMENT
[3:0] FUNCTION FUNCTION
GPIO1 is defined as a sample trigger input (Slave). This input can come from an external
source or from another MAX86140/MAX86141 in master sample mode. GPIO2 will be active
Input Tristate or
if any of the LEDCn[3:0] states A, B, or C are enabled in the exposure sequence. In this case,
0010 Sample Mux
GPIO2 will be low during exposures on LED4, LED5, or LED6, otherwise it will be high. If
Trigger Control
LEDCn[3:0] state A, B, or C is not enabled in the exposure sequence, GPIO2 will be tristate
unless externally pulled up. Exposure timing is controlled by internal oscillator.
Input
Input GPIO1 is defined as a sample trigger input (Slave). This input can come from an external
32768Hz or
0011 Sample source or from another MAX86140/MAX86141 in master sample mode. GPIO2 is an input
32000Hz
Trigger 32768/32000Hz clock input. Exposure timing is controlled by GPIO2 clock input.
Clock Input
GPIO1 is defined as a master sample output. The GPIO1 output can be used to trigger
a second sensor. When used with a second MAX86140/MAX86141 set to slave sample
mode, the master sample timing will drive slave sample time. GPIO2 will be active if any
Active Output Tristate or
of the LEDCn[3:0] states A, B, or C are enabled in the exposure sequence. In this case,
0100 Master Sample Mux
GPIO2 will be low during exposures on LED4, LED5 or LED6, otherwise it will be high.
Output Control
If LEDCn[3:0] state A, B, or C is not enabled in the exposure sequence, GPIO2 will be
tristate unless externally pulled up. Sample and exposure timing is controlled by internal
oscillator.
Input GPIO1 is defined as a master sample output. The GPIO1 output can be used to
Active Output
32768/ trigger and second senor. When used with a second MAX86140/MAX86141 set to slave
0101 Master Sample
32000Hz sample mode, the master sample timing will drive slave sample time. GPIO2 is an input
Output
Clock Input 32768/32000Hz. Exposure timing is controlled by GPIO2 clock input.
GPIO1 is defined as an exposure trigger input (Slave). This input can come from an external
source or from another MAX86140/MAX86141 in master sample mode. Both sample and
Input Tristate or
exposure timing is controlled by the GPIO1 input. GPIO2 will be active if any of the LEDCn[3:0]
0110 Exposure Mux
states A, B, or C are enabled in the exposure sequence. In this case, GPIO2 will be low during
Trigger Control
exposures on LED4, LED5, or LED6, otherwise it will be high. If LEDCn[3:0] state A, B, or C is not
enabled in the exposure sequence, GPIO2 will be tristate unless externally pulled up.
GPIO1 is defined as a master sample output. The GPIO1 output can be used to trig-
ger and second sensor. When used with a second MAX86140/MAX86141 set to slave
Active Output Tristate or exposure mode, the master exposure timing will drive slave exposure time. GPIO2 will be
0111 Master Expo- Mux active if any of the LEDCn[3:0] states A, B, or C are enabled in the exposure sequence. In
sure Output Control this case, GPIO2 will be low during exposures on LED4, LED5 or LED6, otherwise it will be
high. If LEDCn[3:0] state A, B, or C is not enabled in the exposure sequence, GPIO2 will
be tristate unless externally pulled up. Sample and exposure time is controlled internally
Input GPIO1 is defined as a master sample output. The GPIO1 output can be used to trigger second sensor.
Active Output
32768/ When used with a second MAX86140/MAX86141 set to slave exposure mode, the master exposure
1000 Master Expo-
32000Hz timing will drive slave exposure time. GPIO2 is an input 32768/32000Hz. Sample and exposure timing is
sure Output
Clock Input controlled by GPIO2 clock input.
Input Input GPIO1 is defined as a start of sample sync input. The falling edge of GPIO1 causes the
HW_ 32768Hz present sample sequence to be terminated and reinitiated on the next rising edge of
1001
FORCE_ or 32000Hz GPIO2 input. GPIO2 is an input 32768/32000Hz. Sample and exposure timing is controlled
SYNC Clock Input by GPIO2 clock input.

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PPG Configuration 1 (0x11)

BIT 7 6 5 4 3 2 1 0
ALC_DIS- ADD_OFF-
Field PPG2_ADC_RGE[1:0] PPG1_ADC_RGE[1:0] PPG_TINT[1:0]
ABLE SET
Reset 0x0 0 0x0 0x0 0x3
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read

ALC_DISABLE
VALUE ENUMERATION DECODE
0 OFF ALC is enabled
1 ON ALC is disabled

ADD_OFFSET
ADD_OFFSET is an option designed for dark current measurement. By adding offset to the PPG Data would allow dark
current measurement without clipping the signal below 0.
When ADD_OFFSET is set to 1, an offset is added to the PPG Data to be able to measure the dark current. The offset
is 8192 counts if PPG_SR is programmed for single pulse mode. The offset is 4096 counts if PPG_SR is programmed
for dual pulse mode.
PPG2_ADC_RGE
These bits set the ADC range of the SPO2 sensor, as shown in the table below.
PPG_ADC_RGE<1:0> LSB [pA] FULL SCALE [nA]
00 78125 4096
01 15.625 8192
10 31.25 16384
11 62.5 32768

PPG1_ADC_RGE
These bits set the ADC range of the SPO2 sensor, as shown in the table below.
PPG_ADC_RGE<1:0> LSB [pA] FULL SCALE [nA]
00 7,8125 4096
01 15.625 8192
10 31.25 16384
11 62.5 32768

PPG_TINT
These bits set the pulse width of the LED drivers and the integration time of PPG ADC as shown in the table below.
tPW = tTINT + tLED_SETLNG + 0.5μs

RESOLUTION
PPG_TINT<1:0> TPW, PULSE WIDTH [μS] TTINT, INTEGRATION TIME [μS]
BITS
00 21.3 14.8 19
01 35.9 29.4 19
10 65.2 58.7 19
11 123.8 117.3 19

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PPG Configuration 2 (0x12)

BIT 7 6 5 4 3 2 1 0
Field PPG_SR[4:0] SMP_AVE[2:0]
Reset 0x11 0x0
Access Type Write, Read Write, Read

PPG_SR
These bits set the effective sampling rate of the PPG sensor as shown in the table below. The default on-chip sampling
clock frequency is 32768Hz.
Note: If a sample rate is set that can not be supported by the selected pulse width and number of exposures per sample, then
the highest available sample rate will be automatically set. The user can read back this register to confirm the sample rate.

SAMPLING CLOCK
32768HZ 32000HZ
FREQUENCY
PPG_SR<4:0> Samples per Second Samples per Second Pulses Per Sample, N
0x00 24.995 24.409 1
0x01 50.027 48.855 1
0x02 84.021 82.051 1
0x03 99.902 97.561 1
0x04 199,805 195.122 1
0x05 399.610 390.244 1
0x06 24.995 24.409 2
0x07 50.027 48.855 2
0x08 84.021 82.051 2
0x09 99.902 97.561 2
0x0A 8.000 7.8125 1
0x0B 16.000 15.625 1
0x0C 32.000 31.250 1
0x0D 64.000 62.500 1
0x0E 128.000 125.000 1
0x0F 256.000 250.000 1
0x10 512.000 500.000 1
0x11 1024.000 1000.000 1
0x12 2048.000 2000.000 1
0x13 4096.000 4000.000 1
0x14-1F Reserved Reserved Reserved

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Maximum Sample rates (sps) supported for all the Integration Time (PPG_TINT) and Number of Exposures:
NUMBER OF EXPO- PPG_TINT = 3
PPG_TINT = 0 (14.8μS) PPG_TINT = 1 (29.4μS) PPG_TINT = 2 (58.7μS)
SURE PER SAMPLE (117.3μS)
1 Exposure, N = 1 4096 2048 2048 1024
2 Exposures, N = 1 2048 1024 1024 512
3 Exposures, N = 1 1024 1024 512 512
4 Exposures, N = 1 1024 512 512 400
5 Exposures, N = 1 512 512 512 256
6 Exposures, N = 1 512 512 400 256
1 Exposure, N = 2 100 100 100 100
2 Exposures, N = 2 100 84 84 84
3 Exposures, N = 2 50 50 50 50
4 Exposures, N = 2 25 25 25 25
5 Exposures, N = 2 25 25 25 25
6 Exposures, N = 2 25 25 25 25

SMP_AVE
To reduce the amount of data throughput, adjacent samples (in each individual channel) can be averaged and decimated
on the chip by setting this register.
These bits set the number of samples that are averaged on chip before being written to the FIFO.
SMP_AVE[2:0] SAMPLE AVERAGE
000 1 (no averaging)
001 2
010 4
011 8
100 16
101 32
110 64
111 128

When BURST_EN is 1, SMP_AVE defines the number of conversions per burst. Depending on the BURST_RATE
programmed and the PPG_SR used, it may not be possible to accommodate some of SMP_AVE values. In that case,
SMP_AVE will take the highest value that can be accommodated. If SMP_AVE = 0 cannot be accommodated, burst
mode is disabled.
Note: PPG_SR itself depends on Number of conversions per sample (LEDC1 to LEDC6) and the LED Integration time
(PPG_TINT).
The following table shows the maximum SMP_AVE allowed for various configurations of BURST_RATE and PPG_SR:

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PPG_SR   USED BURST_RATE = 0 (8HZ) BURST_RATE = 1 (32HZ) BURST_RATE = 2 (84HZ) BURST_RATE = 3 (256HZ)
0 (25Hz, N = 1) 1 DIS DIS DIS
1 (50Hz, N = 1) 2 0 DIS DIS
2 (84Hz, N = 1) 3 1 DIS DIS
3 (100Hz, N = 1) 3 1 DIS DIS
4 (200Hz, N = 1) 4 2 0 DIS
5 (400Hz, N = 1) 5 3 1 DIS
6 (25Hz, N = 2) 1 DIS DIS DIS
7 (50Hz, N = 2) 2 0 DIS DIS
8 (84Hz, N = 2) 3 1 DIS DIS
9 (100Hz, N = 2) 3 1 DIS DIS
A (8Hz, N = 1) DIS DIS DIS DIS
B (16Hz, N = 1) 0 DIS DIS DIS
C (32Hz, N = 1) 1 DIS DIS DIS
D (64Hz, N = 1) 2 0 DIS DIS
E (128Hz, N = 1) 3 1 0 DIS
F (256Hz, N = 1) 4 2 1 DIS
10 (512Hz, N = 1) 5 3 2 DIS
11 (1024Hz, N = 1) 6 4 3 0
12 (2048Hz, N = 1) 7 5 4 1
13 (4096Hz, N = 1) 7 6 5 2

PPG Configuration 3 (0x13)

BIT 7 6 5 4 3 2 1 0
DIG_FILT_
Field LED_SETLNG[1:0] – – BURST_RATE[1:0] BURST_EN
SEL
Reset 0x1 0x0 – – 0x0 0x0
Access Type Write, Read Write, Read – – Write, Read Write, Read

LED_SETLNG
Delay from rising-edge of LED to start of ADC integration. This allows for the LED current to settle before the start
of ADC integration.
TLED_SETLNG, LED_SETLNG<1:0> DELAY (μS)
00 4.0
01 6.0 (default)
10 8.0
11 12.0

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DIG_FILT_SEL
Select digital filter type.
VALUE ENUMERATION DECODE
0x0 Use CDM
0x1 Use FDM

BURST_RATE
VALUE ENUMERATION DECODE
0x0 8Hz
0x1 32Hz
0x2 84Hz
0x3 256Hz

BURST_EN
When Burst Mode is disabled, PPG data conversions are continuous at the sample rate defined by PPG_SR register,
When Burst mode is enabled, a burst of PPG data conversions occur at the sample rate defined by PPG_SR register.
Number of conversion in the burst is defined by the SMP_AVE register. Average data from the burst of data conversions
is pushed to the FIFO. The burst repeats at the rate defined in BURST_RATE[2:0] register. If the number of conversions
cannot be accommodated, the device will use the next highest number of conversions.
If the effective PPG_SR is too slow to accommodate the burst rate programmed, BURST_EN is automatically set to 0,
and the device runs in continuous mode.
Note: Each data conversion cycle is a sequence of conversions defined in the LEDC1 to LEDC6 registers.
VALUE ENUMERATION DECODE
0x0 Disable Burst Conversion mode
0x1 Enable Burst Conversion Mode

Prox Interrupt Threshold (0x14)

BIT 7 6 5 4 3 2 1 0
Field PROX_INT_THRESH[7:0]
Reset 0x00
Access Type Write, Read

PROX_INT_THRESH
This register sets the LED1 ADC count that will trigger the transition between proximity mode and normal mode. The
threshold is defined as the 8 MSB bits of the ADC count. For example, if PROX_INT_THRESH[7:0] = 0x01, then an ADC
value of 2048 (decimal) or higher triggers the PROX interrupt. If PROX_INT_THRESH[7:0] = 0xFF, then only a saturated
ADC triggers the interrupt.
See the Proximity Mode Function section in the detailed description for more details on the operation of proximity mode.

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Photo Diode Bias (0x15)

BIT 7 6 5 4 3 2 1 0
Field – PDBIAS2[2:0] – PDBIAS1[2:0]
Reset – 0x0 – 0x0
Access Type – Write, Read – Write, Read

PDBIAS2
See Photo Diode Biasing for more information.
PDBIAS2<2:0> PHOTO DIODE CAPACITANCE
0x001 0pF to 65pF
0x101 65pF to 130pF
0x110 130pF to 260pF
0x111 260pF to 520pF
All other values Not recommended

PDBIAS1
See Photo Diode Biasing for more information.
PDBIAS1<2:0> PHOTO DIODE CAPACITANCE
0x001 0pF to 65pF
0x101 65pF to 130pF
0x110 130pF to 260pF
0x111 260pF to 520pF
All other values Not recommended

Picket Fence (0x16)

BIT 7 6 5 4 3 2 1 0
PF_EN- THRESHOLD_SIGMA_
Field PF_ORDER IIR_TC[1:0] IIR_INIT_VALUE[1:0]
ABLE MULT[1:0]
Reset 0x0 0x1 0x00 0x00 0x00
Access Type Write, Read Write, Read Write, Read Write, Read Write, Read

PF_ENABLE
Refer to Picket Fence Detect-and-Replace Function for details.
PF_ENABLE set to 1 enabled the picket-fence detect and replace method.
VALUE ENUMERATION DECODE
0 OFF Disable (default)
1 ON Enable Detect and Replace

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PF_ORDER
PF_ORDER determines which prediction method is used: the last sample or a linear fit to the previous four samples.
Refer to Picket Fence Detect-and-Replace Function for details.
VALUE ENUMERATION DECODE
0 OFF Last Sample (1 point)
1 ON Fit 4 points to a line for prediction (default)
IIR_TC
IIR_TC<1:0> determines the IIR filter bandwidth where the lowest setting has the narrowest bandwidth of a first-order
filter.
Refer to Picket Fence Detect-and-Replace Function for details.
IIR_TC<1:0> COEFFICIENT SAMPLES TO 90%
00 1/64 146
01 1/32 72
10 1/16 35
11 1/8 17

IIR_INIT_VALUE
This IIR filter estimates the true standard deviation between the actual and predicted sample and tracks the ADC Range
setting.
Refer to Picket Fence Detect-and-Replace Function for details.
IIR_INIT_VALUE<1:0> CODE
00 64
01 48
10 32
11 24

THRESHOLD_SIGMA_MULT
GAIN resulting from the SIGMA_MULT<1:0> setting determines the number of standard deviations of the delta between
the actual and predicted sample beyond which a picket-fence event is triggered.
Refer to Picket Fence Detect-and-Replace Function for details.

THRESHOLD_SIGMA_MULT<1:0> GAIN
00 4
01 8
10 16
11 32

LED Sequence Register 1 (0x20)

BIT 7 6 5 4 3 2 1 0
Field LEDC2[3:0] LEDC1[3:0]
Reset 0x0 0x0
Access Type Write, Read Write, Read

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LEDC2
These bits set the data type for LED Sequence 2 of the FIFO.
See FIFO Configuration for more information.
LEDC1
These bits set the data type for LED Sequence 1 of the FIFO.
See FIFO Configuration for more information.
LED Sequence Register 2 (0x21)
BIT 7 6 5 4 3 2 1 0
Field LEDC4[3:0] LEDC3[3:0]
Reset 0x0 0x0
Access Type Write, Read Write, Read

LEDC4
These bits set the data type for LED Sequence 4 of the FIFO.
See FIFO Configuration for more information.
LEDC3
These bits set the data type for LED Sequence 3 of the FIFO.
See FIFO Configuration for more information.
LED Sequence Register 3 (0x22)
BIT 7 6 5 4 3 2 1 0
Field LEDC6[3:0] LEDC5[3:0]
Reset 0x0 0x0
Access Type Write, Read Write, Read

LEDC6
These bits set the data type for LED Sequence 6 of the FIFO.
See FIFO Configuration for more information.
LEDC5
These bits set the data type for LED Sequence 5 of the FIFO.
See FIFO Configuration for more information.
LED1 PA (0x23)
BIT 7 6 5 4 3 2 1 0
Field LED1_DRV[7:0]
Reset 0x00
Access Type Write, Read

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LED1_DRV
These bits set the nominal drive current of LED 1, as shown in the table below.
LEDX_RGE<1:0> 00 01 10 11
LEDx_PA<7:0> LED Current [mA] LED Current [mA] LED Current [mA] LED Current [mA]
00000000 0.00 0.00 0.00 0.00
00000001 0.12 0.24 0.36 0.48
00000010 0.24 0.48 0.73 0.97
00000011 0.36 0.73 1.09 1.45
............
11111100 30.6 61.3 91.9 122.5
11111101 30.8 61.5 92.3 123.0
11111110 30.9 61.8 92.6 123.5
11111111 31.0 62.0 93.0 124.0
LSB 0.12 0.24 0.36 0.48

LED2 PA (0x24)
BIT 7 6 5 4 3 2 1 0
Field LED2_DRV[7:0]
Reset 0x00
Access Type Write, Read

LED2_DRV
These bits set the nominal drive current of LED 2. See LED1_DRV for description.
LED3_PA (0x25)
BIT 7 6 5 4 3 2 1 0
Field LED3_DRV[7:0]
Reset 0x00
Access Type Write, Read

LED3_DRV
These bits set the nominal drive current of LED 2. See LED1_DRV for description.
LED4 PA (0x26)
BIT 7 6 5 4 3 2 1 0
Field LED4_DRV[7:0]
Reset 0x00
Access Type Write, Read

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LED4_DRV
These bits set the nominal drive current of LED 4. See LED1_DRV for description.
LED5 PA (0x27)
BIT 7 6 5 4 3 2 1 0
Field LED5_DRV[7:0]
Reset 0x00
Access Type Write, Read

LED5_DRV
These bits set the nominal drive current of LED 5. See LED1_DRV for description.
LED6 PA (0x28)
BIT 7 6 5 4 3 2 1 0
Field LED6_DRV[7:0]
Reset 0x00
Access Type Write, Read

LED6_DRV
These bits set the nominal drive current of LED 6. See LED1_DRV for description.
LED PILOT PA (0x29)
BIT 7 6 5 4 3 2 1 0
Field PILOT_PA[7:0]
Reset 0x00
Access Type Write, Read

PILOT_PA
The purpose of PILOT_PA<7:0> is to set the LED power during the PROX mode, as well as in Multi-LED mode. These
bits set the nominal drive current for the pilot mode as shown in the table below.
When LED x is used, the respective LEDx_RGE<1:0> is used to control the range of the LED driver in conjunction
with PILOT_PA<7:0>. For instance, if LED1 is used in the PILOT mode, then,  LED1_RGE<1:0> together with PILOT_
PA<7:0> will be used to set the LED1 current.
LEDX_RGE<1:0> 00 01 10 11
PILOT_PA<7:0> LED Current [mA] LED Current [mA] LED Current [mA] LED Current [mA]
00000000 0.00 0.00 0.00 0.00
00000001 0.12 0.24 0.36 0.48
00000010 0.24 0.48 0.73 0.97
00000011 0.36 0.73 1.09 1.45
............
11111100 30.6 61.3 91.9 122.5
11111101 30.8 61.5 92.3 123.0
11111110 30.9 61.8 92.6 123.5
11111111 31.0 62.0 93.0 124.0
LSB 0.12 0.24 0.36 0.48

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LED Range 1 (0x2A)

BIT 7 6 5 4 3 2 1 0
Field – – LED3_RGE[1:0] LED2_RGE[1:0] LED1_RGE[1:0]
Reset – – 0x00 0x00 0x00
Access Type – – Write, Read Write, Read Write, Read

LED3_RGE
Range selection of the LED current. Refer to LED1_PA[7:0] for more details.
LEDX_RGE<1:0>
LED CURRENT[mA]
(X = 1 TO 6)
00 31
01 62
10 93
11 124

LED2_RGE
Range selection of the LED current. Refer to LED3_RGE[1:0] for more details.
LED1_RGE
Range selection of the LED current. Refer to LED3_RGE[1:0] for more details.
LED Range 2 (0x2B)
BIT 7 6 5 4 3 2 1 0
Field – – LED6_RGE[1:0] LED5_RGE[1:0] LED4_RGE[1:0]
Reset – – 0x00 0x00 0x00
Access Type – – Write, Read Write, Read Write, Read

LED6_RGE
Range selection of the LED current. Refer to LED3_RGE[1:0] for more details.
LED5_RGE
Range selection of the LED current. Refer to LED3_RGE[1:0] for more details.
LED4_RGE
Range selection of the LED current. Refer to LED3_RGE[1:0] for more details.

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S1 HI RES DAC1 (0x2C)

BIT 7 6 5 4 3 2 1 0
S1_HRES_
Field – S1_HRES_DAC1[5:0]
DAC1_OVR
Reset 0x0 – 0x00
Access Type Write, Read – Write, Read

S1_HRES_DAC1_OVR
VALUE ENUMERATION DECODE
0 OFF The high resolution DAC for PPG1 is controlled by the chip.
This  allows the high-resolution DAC for PPG1 used in exposure 1 to be controlled by the
1 ON
software.

S1_HRES_DAC1
If S1_ HI_RES_DAC1_OVR = 1, then bits S1_HRES_DAC1<5:0> set the high-resolution DAC code used in PPG1 ADC.
This allows the algorithm to control ADC subranging.
If S1_ HI_RES_DAC1_OVR = 0, then bits S1_HRES_DAC1<5:0> have no effect on the PPG1 ADC.
S2 HI RES DAC1 (0x2D)
BIT 7 6 5 4 3 2 1 0
S2_HRES_
Field – S2_HRES_DAC1[5:0]
DAC1_OVR
Reset 0x0 – 0x00
Access Type Write, Read – Write, Read

S2_HRES_DAC1_OVR
VALUE ENUMERATION DECODE
0 OFF The high resolution DAC for PPG1 is controlled by the chip.
This allows the high-resolution DAC for PPG1 used in exposure 2 to be controlled by the
1 ON
software.

S2_HRES_DAC1
If S2_ HI_RES_DAC1_OVR = 1, then bits S2_HRES_DAC1<5:0> set the high-resolution DAC code used in PPG1 ADC.
This allows the algorithm to control ADC subranging.
If S2_ HI_RES_DAC1_OVR = 0, then bits S2_HRES_DAC1<5:0> have no effect on the PPG1 ADC.

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S3 HI RES DAC1 (0x2E)

BIT 7 6 5 4 3 2 1 0
S3_HRES_
Field – S3_HRES_DAC1[5:0]
DAC1_OVR
Reset 0x0 – 0x0
Access Type Write, Read – Write, Read

S3_HRES_DAC1_OVR

VALUE ENUMERATION DECODE

0x0 OFF The high resolution DAC for PPG1 is controlled by the chip
This  allows the high-resolution DACfor PPG1  used in exposure 3 to be controlled by the
0x1 ON
software.

S3_HRES_DAC1
If S3_ HI_RES_DAC1_OVR = 1 then bits S3_HRES_DAC1<5:0> set the high-resolution DAC code used in PPG1 ADC.
This allows the algorithm to control ADC subranging.
If S3_ HI_RES_DAC1_OVR = 0 then bits S3_HRES_DAC1<5:0> have no effect on the PPG1 ADC.
S4 HI RES DAC1 (0x2F)
BIT 7 6 5 4 3 2 1 0
S4_HRES_
Field – S4_HRES_DAC1[5:0]
DAC1_OVR
Reset 0b0 – 0x0
Access Type Write, Read – Write, Read

S4_HRES_DAC1_OVR

VALUE ENUMERATION DECODE

0x0 OFF The high resolution DAC for PPG1 is controlled by the chip.
This allows the high-resolution DAC for PPG1 used in exposure 4 to be controlled by the
0x1 ON
software.

S4_HRES_DAC1
If S4_ HI_RES_DAC1_OVR = 1 then bits S4_HRES_DAC1<5:0> set the high-resolution DAC code used in PPG1 ADC.
This allows the algorithm to control ADC subranging.
If S4_ HI_RES_DAC1_OVR = 0 then bits S4_HRES_DAC1<5:0> have no effect on the PPG1 ADC.

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S5 HI RES DAC1 (0x30)

BIT 7 6 5 4 3 2 1 0
S5_HRES_
Field – S5_HRES_DAC1[5:0]
DAC1_OVR
Reset 0b0 – 0x0
Access Type Write, Read – Write, Read

S5_HRES_DAC1_OVR

VALUE ENUMERATION DECODE

0x0 OFF The high-resolution DAC for PPG1 is controlled by the chip.
This allows the high-resolution DAC for PPG1 used in exposure 5 to be controlled by the
0x1 ON
software.

S5_HRES_DAC1
If S5_ HI_RES_DAC1_OVR = 1, then bits S5_HRES_DAC1<5:0> set the high-resolution DAC code used in PPG1 ADC.
This allows the algorithm to control ADC subranging.
If S5_ HI_RES_DAC1_OVR = 0, then bits S5_HRES_DAC1<5:0> have no effect on the PPG1 ADC.
S6 HI RES DAC1 (0x31)
BIT 7 6 5 4 3 2 1 0
S6_HRES_
Field – S6_HRES_DAC1[5:0]
DAC1_OVR
Reset 0b0 – 0x0
Access Type Write, Read – Write, Read

S6_HRES_DAC1_OVR

VALUE ENUMERATION DECODE

0x0 OFF The high-resolution DAC for PPG1 is controlled by the chip.
This allows the high-resolution DAC for PPG1 used in exposure 6 to be controlled by the
0x1 ON
software.

S6_HRES_DAC1
If S6_ HI_RES_DAC1_OVR = 1, then bits S6_HRES_DAC1<5:0> set the high-resolution DAC code used in PPG1 ADC.
This allows the algorithm to control ADC subranging.
If S6_ HI_RES_DAC1_OVR = 0, then bits S6_HRES_DAC1<5:0> have no effect on the PPG1 ADC.

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S1_HI RES DAC2 (0x32)

BIT 7 6 5 4 3 2 1 0
S1_HRES_
Field – S1_HRES_DAC2[5:0]
DAC2_OVR
Reset 0x0 – 0x00
Access Type Write, Read – Write, Read

S1_HRES_DAC2_OVR

VALUE ENUMERATION DECODE

0 OFF The high-resolution DAC for PPG2 is controlled by the chip.
This  allows the high-resolution DAC for PPG2 used in exposure 1 to be controlled by the
1 ON
software.

S1_HRES_DAC2
If S1_ HI_RES_DAC2_OVR = 1, then bits S1_HRES_DAC2<5:0> set the high-resolution DAC code used in PPG2 ADC.
This allows the algorithm to control ADC subranging.
If S1_ HI_RES_DAC2_OVR = 0, then bits S1_HRES_DAC2<5:0> have no effect on the PPG2 ADC.
S2 HI RES DAC2 (0x33)
BIT 7 6 5 4 3 2 1 0
S2_HRES_
Field – S2_HRES_DAC2[5:0]
DAC2_OVR
Reset 0x0 – 0x0
Access Type Write, Read – Write, Read

S2_HRES_DAC2_OVR
VALUE ENUMERATION DECODE
0 OFF The high-resolution DAC for PPG2 is controlled by the chip.
This allows the high-resolution DAC for PPG2 used in exposure 2 to be controlled by the
1 ON
software.

S2_HRES_DAC2
If S2_ HI_RES_DAC2_OVR = 1, then bits S2_HRES_DAC2<5:0> set the high-resolution DAC code used in
PPG2 ADC. This allows the algorithm to control ADC subranging.
If S2_ HI_RES_DAC2_OVR = 0, then bits S2_HRES_DAC2<5:0> have no effect on the PPG2 ADC.
S3 HI RES DAC2 (0x34)
BIT 7 6 5 4 3 2 1 0
S3_HRES_
Field – S3_HRES_DAC2[5:0]
DAC2_OVR
Reset 0b0 – 0x0
Access Type Write, Read – Write, Read

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S3_HRES_DAC2_OVR
VALUE ENUMERATION DECODE
0 OFF The high-resolution DAC for PPG2 is controlled by the chip.
This allows the high-resolution DAC for PPG2 used in exposure 3 to be controlled by the
1 ON
software.

S3_HRES_DAC2
If S3_ HI_RES_DAC2_OVR = 1, then bits S3_HRES_DAC2<5:0> set the high-resolution DAC code used in PPG2 ADC.
This allows the algorithm to control ADC subranging.
If S3_ HI_RES_DAC2_OVR = 0 then bits S3_HRES_DAC2<5:0> have no effect on the PPG2 ADC.
S4 HI RES DAC2 (0x35)
BIT 7 6 5 4 3 2 1 0
S4_HRES_
Field – S4_HRES_DAC2[5:0]
DAC2_OVR
Reset 0b0 – 0x0
Access Type Write, Read – Write, Read

S4_HRES_DAC2_OVR
VALUE ENUMERATION DECODE
0x0 OFF The high-resolution DAC for PPG2 is controlled by the chip.
This allows the high-resolution DAC for PPG2 used in exposure 4 to be controlled by the
0x1 ON
software.

S4_HRES_DAC2
If S4_ HI_RES_DAC2_OVR = 1, then bits S4_HRES_DAC2<5:0> set the high resolution DAC code used in PPG2 ADC.
This allows the algorithm to control ADC subranging.
If S4_ HI_RES_DAC2_OVR = 0, then bits S4_HRES_DAC2<5:0> have no effect on the PPG2 ADC.
S5 HI RES DAC2 (0x36)
BIT 7 6 5 4 3 2 1 0
S5_HRES_
Field – S5_HRES_DAC2[5:0]
DAC2_OVR
Reset 0b0 – 0x0
Access Type Write, Read – Write, Read

S5_HRES_DAC2_OVR
VALUE ENUMERATION DECODE
0x0 OFF The high-resolution DAC for PPG2 is controlled by the chip.
This allows the high-resolution DAC for PPG2 used in exposure 5 to be controlled by the
0x1 ON
software.

S5_HRES_DAC2
If S5_ HI_RES_DAC2_OVR = 1, then bits S5_HRES_DAC2<5:0> set the high-resolution DAC code used in PPG2 ADC.
This allows the algorithm to control ADC subranging.
If S5_ HI_RES_DAC2_OVR = 0, then bits S5_HRES_DAC2<5:0> have no effect on the PPG2 ADC.

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S6 HI RES DAC2 (0x37)

BIT 7 6 5 4 3 2 1 0
S6_HRES_
Field – S6_HRES_DAC2[5:0]
DAC2_OVR
Reset 0b0 – 0x0
Access Type Write, Read – Write, Read

S6_HRES_DAC2_OVR
VALUE ENUMERATION DECODE
0x0 OFF The high-resolution DAC for PPG2 is controlled by the chip.
0x1 ON This allows the high-resolution DAC for PPG2 used in exposure 6 to be controlled by the software.

S6_HRES_DAC2
If S6_ HI_RES_DAC_2OVR = 1, then bits S6_HRES_DAC2<5:0> set the high-resolution DAC code used in PPG2 ADC.
This allows the algorithm to control ADC subranging.
If S6_ HI_RES_DAC2_OVR = 0, then bits S6_HRES_DAC2<5:0> have no effect on the PPG2 ADC.
Die Temperature Configuration (0x40)
BIT 7 6 5 4 3 2 1 0
Field – – – – – – – TEMP_EN
Reset – – – – – – – 0x0
Access Type – – – – – – – Write, Read

TEMP_EN
The bit gets cleared after temperature measurement completes.
VALUE ENUMERATION DECODE
0x0 Idle
0x1 Start one temperature measurement

Die Temperature Integer (0x41)

BIT 7 6 5 4 3 2 1 0
Field TEMP_INT[7:0]
Reset 0x0
Access Type Read Only

TEMP_INT
This register stores the integer temperature data in 2s complimnet form. 0x00 = 0°C, 0x7F = 127°C and 0x80 = -128°C
Note: TINT and TFRAC registers should be read through the Serial Interface in burst mode, to ensure that they belong
to the same sample.
Die Temperature Fraction (0x42)
BIT 7 6 5 4 3 2 1 0
Field – – – – TEMP_FRAC[3:0]
Reset – – – – 0x0
Access Type – – – – Read Only

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TEMP_FRAC
This register store the fractional temperature data in increments of 0.0625°C. 0x1 = 0.0625°C  and 0xF = 0.9375°C.
Note: TINT and TFRAC registers should be read through the Serial Interface in burst mode, to ensure that they belong
to the same sample.
SHA Command (0xF0)
BIT 7 6 5 4 3 2 1 0
Field SHA_CMD[7:0]
Reset 0x0
Access Type Write, Read

SHA_CMD
VALUE ENUMERATION DECODE
0X35 MAC WITH ROM ID
0X36 MAC WITHOUT ROM ID
OTHERS RESERVED

SHA Configuration (0xF1)

BIT 7 6 5 4 3 2 1 0
SHA_
Field – – – – – – SHA_EN
START
Reset – – – – – – 0x0 0x0
Access Type – – – – – – Write, Read Write, Read

SHA_EN
Authentication is performed using a FIPS 180-3 compliant SHA-256 one-way hash algorithm on a 512-bit message block.
The message block consists of a 160-bit secret, a 160-bit challenge and 192 bits of constant data. Optionally, the 64-bit
ROM ID replaces 64 of the 192 bits of constant data used in the hash operation. 16 bits out of the 160-bit secret and 16
bits of ROM ID are programmable–8 bits each in metal and 8 bits each in OTP bits.
The host and the MAX86140 both calculate the result based on a mutually known secret. The result of the hash opera-
tion is known as the message authentication code (MAC) or message digest. The MAC is returned by the MAX86140 for
comparison with the host’s MAC. Note that the secret is never transmitted on the bus and thus cannot be captured by
observing bus traffic. Each authentication attempt is initiated by the host system by writing a 160-bit random challenge
into the SHA memory address space 0x00h to 0x09h. The host then issues the compute MAC or compute MAC with
ROM ID command. The MAC is computed per FIPS 180-3, and stored in address space 0x00h to 0x0Fh overwriting the
challenge value.
Note that the results of the authentication attempt are determined by host verification. Operation of the MAX86140 is not
affected by authentication success or failure.

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Sequence of operation is as follows:

●● Enable SHA_DONE Interrupt.
●● Enable SHA_EN bit.
●● Write 160-bit random challenge value to RAM using registers MEM_IDX and MEM_DATA.
●● Write command, with ROM ID (0x35) or without ROM ID (0x36), to SHA_CMD register.
●● Write 1 to SHA_START and 1 to SHA_EN bit.
●● Wait for SHA_DONE interrupt.
●● Read 256 MAC value from RAM using registers MEM_IDX and MEM_DATA.
●● Compare MAC from MAX86140 wth Host's precalculated MAC.
●● Check PASS or FAIL.
●● Disable SHA_EN bit ( Write 0 to SHA_EN bit).

VALUE ENUMERATION DECODE

0x0 Authentication is disabled
0x1 Authentication is enabled

SHA_START
The bit gets cleared after authentication completes. The valid command (0x35 or 0x36) should be written to the SHA_
CMD register and challenge value should be written to the RAM by Host before writing 1 to this bit.
Memory Control (0xF2)
BIT 7 6 5 4 3 2 1 0
MEM_WR_
Field – – – – – – BANK_SEL
EN
Reset – – – – – – 0x0 0x0
Access Type – – – – – – Write, Read Write, Read

MEM_WR_EN
Enable write access to Memory through SPI.

VALUE ENUMERATION DECODE

0x0 Writing to memory through SPI is disabled.
0x1 Writing to memory through SPI is enabled

BANK_SEL
Selects the memory bank for reading and writing.
Burst reading or writing the memory past 0xFF automatically increments BANK_SEL to 1.
VALUE ENUMERATION DECODE
0x0 Select Bank 0, address 0x00 to 0xFF
0x1 Select Bank 1, address 0x100 to 0x17f

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Memory Index (0xF3)

BIT 7 6 5 4 3 2 1 0
Field MEM_IDX[7:0]
Reset 0x0
Access Type Write, Read

MEM_IDX
Index to Memory for reading and writing. The memory is 384 bytes, and is divided into two banks - Bank 0 from  0x00
to 0xFF and Bank 1 is from 0x100 to 0x17F. The bank is selected by the BANK_SEL register bit. MEM_IDX is the starting
address for burst writing to or reading from memory. Burst accessing the memory past 0xFF accesses Bank 1. The
memory address saturates at 0x17F.
Memory Data (0xF4)
BIT 7 6 5 4 3 2 1 0
Field MEM_DATA[7:0]
Reset 0x0
Access Type Write, Read, Dual

MEM_DATA
Data to be written or data read from Memory
Reading this register does not automatically increment the register address. So burst reading this register read the
same register over and over, but the address to the Memory autoincrements until BANK_SEL becomes 1 and MEM_IDX
becomes 0x7F.
Part ID (0xFF)
BIT 7 6 5 4 3 2 1 0
Field PART_ID[7:0]
Reset 0xXX
Access Type Read Only

PART_ID
This register stores the part identifier for the chip.
PART_ID MAX # # OF PPG CHANNELS
0x24 MAX86140 1
0x25 MAX86141 2

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Typical Application Circuit

1.8V
0.1μF 10μF
1μF
VDDIO NOTE 2

VDD_ANA

VDD_DIG
VREF

R NOTE 1
DIE TEMP
REFERENCE INT INT
12-BIT ADC
SCLK SCLK

HOST (AP)
SDI SDI
DIGITAL NOISE
AMBIENT CANCELLATION SDO SDO
CANCELLATION
CSB CSB

PD1_IN SPI
19-BIT CURRENT ADC
INTERFACE
PD_GND 128-WORD
FIFO
PD2_IN 19-BIT CURRENT ADC
(MAX86141 ONLY) GPIO1
GPIO2
DIGITAL NOISE
AMBIENT CANCELLATION
(MAX86141 ONLY)
CANCELLATION
(MAX86141 ONLY)

5.0V NOTE 3
VLED
LED1_DRV CONTROLLER
10μF
LED2_DRV LED DRIVERS
LED3_DRV
MAX86140/MAX86141
PGND

GND_ANA

GND_DIG

NOTE 1: THE VALUE OF INT PULLUP RESISTORS SHOULD BE BASED ON THE SYSTEM DESIGN.
NOTE 2: VDDIO IS THE SYSTEM I/O VOLTAGE SUPPLY.
NOTE 3: VLED IS THE LED POWER SUPPLY INPUT, IT SHOULD BE BASED ON THE SPECIFICATIONS OF THE LED USED.

Ordering Information
PART NUMBER TEMP RANGE PIN-PACKAGE CONFIGURATION
20-pin WLP, 2.048mm x 1.848mm, 5 x 4,
MAX86140ENP+ -40°C to +85°C Single-Channel Optical AFE
0.4mm ball pitch
20-pin WLP, 2.048mm x 1.848mm, 5 x 4,
MAX86141ENP+ -40°C to +85°C Dual-Channel Optical AFE
0.4mm ball pitch

+Denotes a lead(Pb)-free/RoHS-compliant package.

T = Tape and reel.

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Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 5/17 Initial release —
1 8/17 Added MAX86141 part number to data sheet 1–88

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2017 Maxim Integrated Products, Inc. │  89
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