CS8351-Digital Principles and System Design PDF
CS8351-Digital Principles and System Design PDF
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VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203
DEPARTMENT OF
COMPUTER SCIENCE AND ENGINEERING
QUESTION BANK
III SEMESTER
Regulation – 2017
Prepared by
Dr.L.Karthikeyan AP/CSE
Ms.A.Vidhya Ap/CSE
Ms.Shanthi S AP/CSE
www.rejinpaul.com
VALLIAMMAI ENGINEERING COLLEGE
SRM Nagar, Kattankulathur – 603 203.
QUESTION BANK
UNIT I
PART – A
Q.No Questions BT Competence
1. Define Multilevel Gates. Level
BTL-1 Remember
2. Describe weighted binary code and Non –weighted
BTL-1 Remember
code.
3. Explain Canonical and Standard Forms. BTL-5 Evaluate
4. Define and prove the consensus theorem. BTL-1 Remember
5. State and Apply DeMorgan’s theorem.
BTL-3 Apply
[(x+y)’+(x+y)’]’=x+y
6. Explain the principle of duality. BTL-5 Evaluate
7. Describe the Commutative law and convert (126)10 to
BTL-2 Understand
octal.
8. What is meant by self-Complementing Code and
BTL -1 Remember
convert (0.6875)10 to Binary
9. Differentiate SOP and POS and convert
BTL-4 Analyze
(101101.1101)2 to Hexadecimal.
10. Develop XOR gate using only 4 NAND gates. BTL-6 Create
11. Give the octal equivalent of hexadecimal numbers of
BTL-2 Understand
DC.BA and AB.CD
12. Explain any four Boolean theorems with example. BTL-4 Analyze
13. Develop AND gate using NAND. BTL-6 Create
14. Define distributive law and associative law BTL-1 Remember
15. Describe Excess-3 code BTL-1 Remember
16. Summarize about the limitations of Karnaugh map. BTL-2 Remember
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17. Infer AND gate using only NOR gate. BTL-4 Analyze
18. Apply 10’s compliment to subtract 52532 - 3250 BTL-3 Apply
19. Give the Truth Table of XOR gate. BTL-2 Understand
20. Solve the following:
(i)(1001010.1101001)2 to base 16
(ii)(231.07)8 to base 10 BTL-3 Apply
PART – B
1 i) Define K-map and simplify
F(A,B,C,D)=∑(0,1,2,5,8,9,10) in sum of products
BTL-1 Remember
and product of sum using K-map. (10)
ii) Describe negative and positive logic. (3)
2 Discuss the following switching functions using K-map
F(A,B,C,D)= ∑(0,3,5,7,8,9,10,12,15) (8) BTL-2 Understand
(ii)Realize the above expression using logic gates. (5)
3 Describe the MSP form of the switching function
F(a,b,c,d)=_(0,2,4,6,8)+_d(10,11,12,13,14,15) (8) BTL-1 Remember
ii) Check if NOR Operator is associative. (5)
4 i)Apply the switching function
f(x,y,z)= ∑m(0,1,3,4,12,14,15) using NAND gate. (8) BTL-3 Apply
(ii)Check if NAND operator is associative. (5)
Explain5 the following Boolean expression in
5 Product-of –sum and Sum-of –product using Karnaugh
map for AC’ + B’D + A’CD + ABCD. (13) BTL-4 Analyze
i)Discuss
7 and minimize the following expression using
7 Karnaugh map.
Y=A’BC’D’+A’BC’D+ABC’D’+AB’C’D+A’B’CD’ (10) BTL-2 Understand
ii)State and prove DeMorgan’s theorem. (3)
BTL-1 Remember
PART-C
C y
5 BTL-4 Analyze
ii) With a neat diagram explain the 4 bit adder with carry
look ahead. (7)
A
F
B
12 BTL-2 Understand
C
PART-C
i)Design and analyse a 8421 to gray code converter and
1 convert it using only NAND gate. (8) BTL-4 Analyze
ii)Design an magnitude comparator. (7)
i)Summarize the procedure to build a 4-to-16 decoder, using
only 2-to-4 decoders. (8)
2 BTL-5 Evaluate
ii) Design half adder and Half subtractor. (7)
UNIT III
BTL-3 Apply
PART-C
4 Design and explain the sequential circuit for the state diagram
shown below. Use JK flip-flop. (15)
BTL-5 Evaluate
UNIT IV
BTL-1 Remember
a a b 0 0
BTL-6 Create
b c d 0 0
c a d 0 0
d e f 0 1
e a f 0 1
f g f 0 1
g a f 0 1
PART – A
Q.N Questions BT Competence
1o Define RAM and its types. Level
BTL-1 Remember
2 List the Read and write operation for RAM. BTL-1 Remember
3 Explain ROM and draw its block diagram. BTL-5 Evaluate
4 Define PROM, EPROM and EEPROM. BTL-1 Remember
5 Demonstrate why memory decoding is needed. BTL-3 Apply
6 Explain hamming code. BTL-5 Evaluate
7 Illustrate the various types of ROM. BTL-3 Apply
8 List the three types of PLD. BTL -1 Remember
9 Point out the programmable array logic (PAL). BTL-4 Analyze
10 Formulate the programmable logic array (PLA). BTL-6 Create
11 Express what a sequential programmable device is. BTL-2 Understand
12 Point out in detail about various types of sequential
BTL-4 Analyze
programmable device.
13 Design the block diagram of CPLD. BTL-6 Create
14 Describe FPGA. BTL-1 Remember
15 Define SPLD. BTL-1 Remember
16 Differentiate PLA and PAL. BTL-2 Remember
17 Explain Error Detecting code. BTL-4 Analyze
18 Distinguish between SRAM and DRAM. BTL-2 Understand