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    Cisc Vs Risc

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    Georgiana Danila
    The document compares RISC and CISC architectures. CISC uses complex instructions that perform multiple operations in one instruction, like multiplying two numbers in memory with a single "MULT" instruction. RISC breaks operations into simpler instructions that each require one clock cycle, like using separate "LOAD", "PROD", and "STORE" instructions. While RISC requires more instructions, each executes faster so total time is similar. RISC also allows for pipelining and leaves more room for registers in the processor hardware.

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    Cisc Vs Risc

    Uploaded by

    Georgiana Danila
    54 views3 pages
    The document compares RISC and CISC architectures. CISC uses complex instructions that perform multiple operations in one instruction, like multiplying two numbers in memory with a single "MULT" instruction. RISC breaks operations into simpler instructions that each require one clock cycle, like using separate "LOAD", "PROD", and "STORE" instructions. While RISC requires more instructions, each executes faster so total time is similar. RISC also allows for pipelining and leaves more room for registers in the processor hardware.

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    Cisc vs Risc

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    The document compares RISC and CISC architectures. CISC uses complex instructions that perform multiple operations in one instruction, like multiplying two numbers in memory with a single "MULT" instruction. RISC breaks operations into simpler instructions that each require one clock cycle, like using separate "LOAD", "PROD", and "STORE" instructions. While RISC requires more instructions, each executes faster so total time is similar. RISC also allows for pipelining and leaves more room for registers in the processor hardware.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    54 views3 pages

    Cisc Vs Risc

    Uploaded by

    Georgiana Danila
    The document compares RISC and CISC architectures. CISC uses complex instructions that perform multiple operations in one instruction, like multiplying two numbers in memory with a single "MULT" instruction. RISC breaks operations into simpler instructions that each require one clock cycle, like using separate "LOAD", "PROD", and "STORE" instructions. While RISC requires more instructions, each executes faster so total time is similar. RISC also allows for pipelining and leaves more room for registers in the processor hardware.

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    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 3

    The simplest way to examine the advantages and disadvantages of RISC architecture is

    by contrasting it with it's predecessor: CISC (Complex Instruction Set Computers)


    architecture.

    Multiplying Two Numbers in Memory


    On the right is a diagram representing the storage scheme
    for a generic computer. The main memory is divided into
    locations numbered from (row) 1: (column) 1 to (row) 6:
    (column) 4. The execution unit is responsible for carrying out
    all computations. However, the execution unit can only
    operate on data that has been loaded into one of the six
    registers (A, B, C, D, E, or F). Let's say we want to find the
    product of two numbers - one stored in location 2:3 and
    another stored in location 5:2 - and then store the product
    back in the location 2:3.

    The CISC Approach


    The primary goal of CISC architecture is to complete a task
    in as few lines of assembly as possible. This is achieved by
    building processor hardware that is capable of understanding
    and executing a series of operations. For this particular task,
    a CISC processor would come prepared with a specific instruction (we'll call it "MULT").
    When executed, this instruction loads the two values into separate registers, multiplies
    the operands in the execution unit, and then stores the product in the appropriate
    register. Thus, the entire task of multiplying two numbers can be completed with one
    instruction:

    MULT 2:3, 5:2

    MULT is what is known as a "complex instruction." It operates directly on the computer's


    memory banks and does not require the programmer to explicitly call any loading or
    storing functions. It closely resembles a command in a higher level language. For
    instance, if we let "a" represent the value of 2:3 and "b" represent the value of 5:2, then
    this command is identical to the C statement "a = a * b."

    One of the primary advantages of this system is that the compiler has to do very little
    work to translate a high-level language statement into assembly. Because the length of
    the code is relatively short, very little RAM is required to store instructions. The
    emphasis is put on building complex instructions directly into the hardware.

    The RISC Approach


    RISC processors only use simple instructions that can be executed within one clock
    cycle. Thus, the "MULT" command described above could be divided into three separate
    commands: "LOAD," which moves data from the memory bank to a register, "PROD,"
    which finds the product of two operands located within the registers, and "STORE,"
    which moves data from a register to the memory banks. In order to perform the exact
    series of steps described in the CISC approach, a programmer would need to code four
    lines of assembly:

    LOAD A, 2:3
    LOAD B, 5:2
    PROD A, B
    STORE 2:3, A

    At first, this may seem like a much less efficient way of completing the operation.
    Because there are more lines of code, more RAM is needed to store the assembly level
    instructions. The compiler must also perform more work to convert a high-level language
    statement into code of this form.

    CISC RISC However, the RISC strategy


    Emphasis on hardware Emphasis on software also brings some very
    Includes multi-clock Single-clock, important advantages. Because
    complex instructions reduced instruction only each instruction requires only
    one clock cycle to execute, the
    Memory-to-memory: Register to register:
    entire program will execute in
    "LOAD" and "STORE" "LOAD" and "STORE"
    approximately the same
    incorporated in instructions are independent instructions
    amount of time as the multi-
    Small code sizes, Low cycles per second,
    cycle "MULT" command. These
    high cycles per second large code sizes
    RISC "reduced instructions"
    Transistors used for storing Spends more transistors require less transistors of
    complex instructions on memory registers hardware space than the
    complex instructions, leaving
    more room for general purpose registers. Because all of the instructions execute in a
    uniform amount of time (i.e. one clock), pipelining is possible.

    Separating the "LOAD" and "STORE" instructions actually reduces the amount of work
    that the computer must perform. After a CISC-style "MULT" command is executed, the
    processor automatically erases the registers. If one of the operands needs to be used for
    another computation, the processor must re-load the data from the memory bank into a
    register. In RISC, the operand will remain in the register until another value is loaded in
    its place.

    The Performance Equation


    The following equation is commonly used for expressing a computer's performance
    ability:

    The CISC approach attempts to minimize the number of instructions per program,
    sacrificing the number of cycles per instruction. RISC does the opposite, reducing the
    cycles per instruction at the cost of the number of instructions per program.

    RISC Roadblocks
    Despite the advantages of RISC based processing, RISC chips took over a decade to gain
    a foothold in the commercial world. This was largely due to a lack of software support.

    Although Apple's
    Power Macintosh line
    featured RISC-based
    chips and Windows
    NT was RISC
    compatible, Windows
    3.1 and Windows 95
    were designed with
    CISC processors in
    mind. Many
    companies were
    unwilling to take a
    chance with the
    emerging RISC technology. Without commercial interest, processor developers were
    unable to manufacture RISC chips in large enough volumes to make their price
    competitive.

    Another major setback was the presence of Intel. Although their CISC chips were
    becoming increasingly unwieldy and difficult to develop, Intel had the resources to plow
    through development and produce powerful processors. Although RISC chips might
    surpass Intel's efforts in specific areas, the differences were not great enough to
    persuade buyers to change technologies.

    The Overall RISC Advantage


    Today, the Intel x86 is arguable the only chip which retains CISC architecture. This is
    primarily due to advancements in other areas of computer technology. The price of RAM
    has decreased dramatically. In 1977, 1MB of DRAM cost about $5,000. By 1994, the
    same amount of memory cost only $6 (when adjusted for inflation). Compiler technology
    has also become more sophisticated, so that the RISC use of RAM and emphasis on
    software has become ideal.

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