The interrelationship between software and hardware 415

10
OPTION 2
THE INTERRELATIONSHIP BETWEEN
SOFTWARE AND HARDWARE

In this option, we examine the basis of digital computer hardware; data, storage and
processing. We consider the manner in which data is represented within the computer.
Different data types require different methods of binary representation; all are based
on the binary number system. We then examine the circuits that allow us to store and
process this data. Logic gates are the building blocks for integrated circuits. What are
logic gates and how are they combined to perform new and varied functions? We
answer these questions and design some simple integrated circuits. In particular, we
investigate circuits used to perform binary addition and those used to store binary
data.
The final section of this option describes the programming and interfacing of
hardware devices. We examine the data streams required to provide input to various
hardware devices as well as the returned output data streams. The format and
processing required to generate and understand these data streams, is discussed. We
look at a number of practical examples where this infonnation is utilised to control
hardware devices in real world applications.

Consider the following:

Computers can only process binary data; that is strings of zeros and ones. Considering
this fact, it seems remarkable that computers are able to perform such a broad range of
tasks. How can strings of binary digits be used to show videos, track bank account
transactions or control a production line of robots? Many people consider the
computer to be the most significant invention of all time.

GROUP TASK Discussion

Develop a list of tasks that would be impossible to perform without the
assistance of computers. How are computers able to perform all these
tasks using just binary numbers and combinations of circuits?

GROUP TASK Discussion

Why would many people consider the computer to be the most significant
invention of all time? Consider prior inventions and discoveries that were
necessary before the computer, as we know it could be developed.

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416 Chapter 10

REPRESENTATION OF DATA WITHIN THE COMPUTER

All data within a computer system is stored and
processed in binary. The binary or base 2 number
system, uses only 2 digits; zero and one. These
binary digits or bits can be stored in a variety of
ways depending on the particular medium. For
example, lands and pits on a CD-ROM,
magnetised needles on the surface of a floppy disk
or high and low voltages sent down a
communication path. Later in this chapter, we will Fig 10.1
examine how binary is stored and processed using Hard disk drives, CDs, D VDs andflash
memory all store binary data.
integrated circuits.
Before considering methods of representing data using binary numbers, we need an
understanding of how the binary system operates. Once we have an understanding of
the binary system, we shall consider common methods for representing characters,
integers and fractions. We conclude by examining binary arithmetic; addition,
subtraction, multiplication and division.
THE BINARY NUMBER SYSTEM
The decimal number system is based on the number ten hence we require ten symbols.
We call these symbols digits; in decimal or base 10 we use the digits 0, 1,2,3,4,5,6,
7,8 and 9. The binary number system is based on the number two, hence we require 2
symbols or digits, and we use 0 and 1.
The placement of each digit in Decimal
relation to other digits 103=1000 102=100 10 1=10 10°=1
Number
determines its place value. For 3407 3 4 0 7
example, the decimal number 968 0 9 6 8
3407 means three thousands, four 1082 1 0 8 2
hundreds, zero tens and seven 6600 6 6 0 0
123 0 1 2 3
units. The four is said to have a
0 0 0 0 0
place value of 100, or 102. The 9999 9 9 9 9
three has a place value of 1000 or
Fig 10.2
103 • In other words, 3407 could Decimal numbers have place values based on
be written as (3 x 103) + powers ofthe number ten.
(4 X 102) + (0 X 10 1) + (7 x 10°).

GROUP TASK Activity

Write down a series of ten decimal numbers between 0 and 1 million.
Create a table, such as the one in Fig 10.2, and complete the table using
your ten numbers.

Binary numbers are based on the number two thus place value is determined by
powers of two. The binary number 11 Olean be written as (1 x 23) + (1 X 22) +
(0 X 21) + (1 x 2°). In decimal, the binary number 1101 has a value of 8 + 4 + 0 + 1,
which is equal to 13. We write this as 11012 = 13 10, the subscript is used to indicate
the base used. Leading zeros have no effect on the value of a number. For example,
0001011 h is equivalent to 1011 h. Zeros between non-zero digits are required to
ensure correct place value. For example, 111 h is not the same number as 1011102 •

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 The interrelationship between software and hardware 417

When using binary numbers with computer systems it is usual to retain the leading
zeros to make up numbers with a multiple of 8 bits. For example, we write 0011101lz
rather than 1110 11 2 • This is because computers deal with binary numbers of a specific
length. Generally, Binary
27=128 26=64 2 5=32 24=16 2 3=8 22=4 21=2 2°=1
binary numbers Number
are expressed in 11010111 1 1 0 1 0 1 1 1
series of 8 bits, 00101111 0 0 1 0 1 1 1 1
01110111 0 1 1 1 0 1 1 1
called a byte. Most
01011100 0 1 0 1 1 1 0 0
computers store
and process data in Fig 10.3
Binary numbers have place values based on the number two.
multiples of 8 bits;
the number of bits processed at a time is called the word length of the processor.
Common processors have word lengths of 8, 16, 32 or 64 bits.

GROUP TASK Activity

°
Write down a series of ten binary numbers between and 11111111.
Create a table, such as the one in Fig 10.3, and complete the table using
your ten numbers. What is the largest number you can store using 8 bits?

Counting in binary
Decimal Binary Decimal Binary
As is the case in the decimal system, once 1 1 21 10101
we run out of digits we increment the 2 10 22 10110
number held to the left and set the current 3 11 23 10111
value back to zero. For example, in decimal 4 100 24 11000
we count 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 5 101 25 11001
6 110 26 11010
12 ... 19,20,21. .. 29,30,31, etc. In binary,
7 111 27 11011
we only have only two digits so our 8 1000 28 11100
numbers very quickly become long. For 9 1001 29 11101
example, in binary we count 1, 10, 11, 100, 10 1010 30 11110
101, 110, 111, 1000, 1001, 1010, 1011, 11 1011 31 11111
1100, 1101, 1110, 1111, 10000, we are 12 1100 32 100000
already using five digit numbers yet in 13 1101 33 100001
14 1110 34 100010
decimal we have only reached a value of 16. 15 1111 35 100011
Fortunately, computers are particularly 16 10000 36 100100
good at storing vast amounts of data, so the 17 10001 37 100101
18 10010 38 100110
length of binary numbers is relatively
19 10011 39 100111
insignificant in computing terms. Humans, 20 10100 40 101000
on the other hand, find binary numbers
Fig lOA
difficult to accurately read and process. To Counting in binary and decimal.
simplify binary numbers for humans, we
use the hexadecimal number system.

GROUP TASK Activity

The large number of digits used to represent numbers using binary
provides difficulties for us mere mortals. For example 12 =1 10, 102 =2 1°'
°'
1002 =41°' 10002 =8 1 100002 =16 1°' 1000002 =32 10 • Extend this sequence to
32 bits, that is a one followed by thirty one zeros.

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418 Chapter 10

Hexadecimal numbers
Hexadecimal numbers use the base sixteen number Decimal Binary Hexadecimal
system. Hex meaning six and dec meaning ten so 0 0000 0
hexadecimal refers to sixteen. Hexadecimal numbers 1 0001 1
are used because they greatly simplify the task of 2 0010 2
writing binary numbers yet conversion between base 2 3 0011 3
4 0100 4
and base 16 is simple. An eight digit binary number,
5 0101 5
one byte, can be written as a two digit hexadecimal 6 0110 6
number. Each sequence of four bits, called a nibble, 7 0111 7
converts neatly into a single hexadecimal digit. 8 1000 8
In base 16, we require sixteen unique symbols to use as 9 1001 9
10 1010 A
our digits. Because hexadecimal is so often used on
11 1011 B
computers, it makes sense to use symbols available on 12 1100 C
a standard keyboard. We use the sixteen symbols 0, 1, 13 1101 D
2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E and F as our digits. 14 1110 E
Furthermore, special symbols are often used to indicate 15 1111 F
the number following is in base 16. &H13 and Ox13 are Fig 10.5
the equivalent of 13 16, similarly &H6E and Ox6E are Decimal to Binary to
hexadecimal conversion.
equivalent to writing 6E16.
As is the case in other bases, place value is determined by the position of each digit.
The magnitude of each place value is calculated using powers of the base number. For
example 3E716 can be written as (3 x 162) + (E X 16 1) +(7 x 16°) and 50AB 16 as
(5 x 163) + (0 X 162) + (A X 16 1) +(B x 16°).

II
",~,,~~~~~~: ~~1~>';
GROUP TASK Activity
Although not strictly required in this course, base 8 or octal numbers are
often used in conjunction with computer systems. Make up a table of
octal numbers compared with their binary equivalents. Why do you think
octal numbers would be of use in regard to computers?

Converting between hexadecimal, binary and decimal

Most electronic calculators include functions to perform conversions between
numbers in different bases. In this course, we need to understand the processes taking
place to perform these conversions.
• Binary to decimal conversion
To convert a binary number to decimal, we write the binary number in expanded form
and then calculate the result. For example, let us convert 11011 b into decimal.
1l01lb =(1 x2 5)+(1 x2 4)+(Ox2 3)+(1 x2 2)+(1 x2 1)+(1 x 2°)
=32+16+0+4+2+1
= 5510
• Hexadecimal to decimal conversion
Again, we write the number in expanded form and calculate the result. For example,
let us convert 5C316 into decimal.
5C3 16 = (5 X 162) + (C X 16 1) + (3 x 16°)
= (5 x 256) + (12 x 16) + (3 xl)
= 1280 + 192 + 3
= 1475 10

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 The interrelationship between software and hardware 419

• Decimal to binary conversion

This process is slightly more complex as we have not grown up learning powers of
two. There are two common methods of performing these conversions; the first
involves subtraction, the second repeated division.
Suppose we wish to find the binary equivalent of the decimal number 109.
Method 1.
1. Firstly, we determine the value of the power of two closest to but smaller than the
number. In this case 64 is the value that meets this criteria, as 128 is larger than
109.
109
2. Subtract this number from the original number. - 64
That is 109 - 64 = 45, note that 45 is less than 45
64, the result will always be less than the --
- 32
number subtracted. The first or left hand digit 13
in the answer is a 1. 0
Result
13
3. We now consider half of 64, namely 32. 45 - Working (from
-8 top to
32 = 13, the second digit in the answer is also a 5 bottom)
1. -4
4. We now consider half of 32, namely 16. As 16 1
is greater than 13 the third digit in the answer o
is a O. 1
5. We now consider half of 16, namely 8. 13 - 8 -~
= 5, the fourth digit in the answer is a 1. Fig 10.6
6. We now consider half of 8, namely 4. 5 - 4 = Setting outfor working using method 1.
1, the fifth digit in the answer is a 1.
7. We now consider half of 4, namely 2. As 2 is greater than 1 the sixth digit is a O.
8. Finally, we consider half of 2, namely 1. 1 - 1 = 0, the seventh digit is a one.
Our answer is 11 0 11 0 h, so 10910 = 11 0 11 0 h Fig 10.6 shows the working out
required to use this method.
Method 2.
Using this method, we repeatedly divide the 109
+2
number by two. The remainders after these
54
divisions are the answer in reverse order. +2 0
1. 109 + 2 = 54 with a remainder of 1. The first 27
or right hand digit is a 1. +2
Result
13
2. 54 + 2 = 27 remainder O. The second digit is a O. Working (from
+2 bottom
3. 27 + 2 = 13 remainder 1. The third digit is a 1. 6 to top)
4. 13 + 2 = 6 remainder 1. The fourth digit is a 1. +2 0
- -
5. 6 + 2 = 3 remainder O. The fifth digit is a O. 3
6. 3 + 2 = I remainder 1. The sixth digit is a 1. +2
7. 1 + 2 = 0 remainder 1. The seventh digit is a 1.
+2
Again our answer is 110110lz, so 109 10 = o
11 0 11 0 h Fig 10.7 shows the working out Fig 10.7
required to use this method. Setting out for working using method 2.

GROUP TASK Activity

Use each of the above two methods to convert a series of ten decimal
numbers into binary. Use numbers in the range 0 to 255. Why do you
think a range of 0 to 255 has been stipulated?

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420 Chapter 10

• Decimal to hexadecimal conversion

The essence of the two methods discussed abov~ for converting decimal to binary, can
be used for converting decimal to hexadecimal. The difference being that we are
working in base 16 rather than base 2. As a conse?uence, we are working with powers
of 16, namely 164=65536, 163=4096, 162=256, 16 =16 and 16°=1.
Suppose we wish to find the hexadecimal equivalent of the decimal number 10952.
Method 1
This method requires division by powers of 16, which makes the arithmetic somewhat
difficult.
1. Firstly, we determine the value of the power of sixteen closest to but smaller than
the number. In this case 163 or 4096 is the value that meets this criteria, as 65536
is larger than 10952.
2. Divide this number into the original number.
10952
That is 10952 + 4096 = 2 with a remainder of - 8192 2
2760. Note that 10952 - (2 x 4096) = 10952- 2760
8192 = 2760. The first or left hand digit in the - 2560 10=A Result
Working (from
answer is a 2. 200 top to
-192 12=C bottom)
3. We now divide 2760 by 162 or 256. That is, 8
2760 + 256 = 10 with a remainder of 200. The -8 8
second digit in the answer is' a 10, which is o
represented in hexadecimal by the symbol A. Fig 10.8
4. We now divide 200 by 16. 200 + 16 = 12 with a Setting out for working
remainder of 8. The third digit in the answer is using method 1.
a 12, which is represented in hexadecimal by
the symbol C.
5. The final digit must be an 8.
Our answer is 2AC8 l 6, so 1095210 = 2AC8 l6 . Fig 10.8 shows the working out required
to use this method.
Method 2
This method requires repeated division by 16. The remainders forming the result in
reverse order. .
1. 10952 + 16 = 684 remainder 8. The first or 10952
right hand digit in the answer is an 8. + 16 8
2. 684 + 16 = 42 remainder 12. The second digit 684
Result
+ 16 12=C
in the answer is 12 which is represented by the Working (from
42 bottom
symbol C. + 16 lO=A to top)
3. 42 + 16 = 2 remainder 10. The third digit in the 2
answer is 10 which is represented by the + 16 2
symbolA. o
4. As 2 is less than 16 this b~comes the final digit. Fig 10.9
Setting out for working
Again our answer is 2AC8 l6 , so 1095210 = 2AC8 l6 . using method 2.
Fig 10.9 shows the working required to use this
method.

GROUP TASK Activity

Use each of the above two methods to convert a series of ten decimal
numbers into hexadecimal. Use numbers in the range 0 to 65535.

Software Design and Development -The HSC Course

 The interrelationship between software and hardware 421

• Binary to hexadecimal and hexadecimal to binary conversion

Converting between base 2 and base 16 is relatively simple as 16 is a power of 2.
Each group of four bits, called a nibble, converts neatly into a single hexadecimal
digit. Similarly, each hexadecimal digit converts neatly into a nibble of 4 bits. Fig
10.5 shows the conversion between each hexadecimal digit and binary, it is
worthwhile committing this table to memory.
Suppose we wish to convert the binary number 1011010110 into hexadecimal.
1. Firstly, we split the number into nibbles commencing with the right hand side and
adding leading zeros if necessary. That is, 1011010110 becomes 0010 1101 0110.
2. Convert each nibble into its hexadecimal digit equivalent. 00102 = 216, 110h =
D 16 and 01102 = 616.
3. These hexadecimal digits become the answer. Thus 10110101102 = 2D6 16 which
can also be written as &H2D6 or Ox2D6.
Suppose we wish to convert A30 16 into binary.
1. A means 10. This is represented by the binary nibble 1010.
2. 3 is represented by the binary nibble 0010.
3. 0 is represented by the binary nibble 0000.
4. Combining these nibbles gives the result 1010001000002.

GROUP TASK Activity

Create a series of 10 two and three digit hexadecimal numbers. Convert
each of these numbers into binary and then reverse the process to convert
them back into hexadecimal.

CHARACTER REPRESENTATION
Characters must be represented using binary code if they are to be stored and
processed by computers. There are two types of characters that require representation,
printable characters and non-printable characters. The printable characters include all
the upper and lower case letters of the English alphabet together with numbers,
punctuation marks and some other special characters such as the percent and dollar
sign. In addition there are thousands of characters which form part of the numerous
languages throughout the world. Finally there are non-printable characters which are
often called control characters. These characters are not displayed on the screen but
rather are used to perform commonly required functions. For example, backspace and
delete are generally used to remove data, carriage returns and linefeed characters
influence formatting, and acknowledge (ACK) and negative acknowledge (NAK)
characters are used for communication.
There are various methods used for coding characters into binary. The most common
methods are ASCII (American Standard Code for Information Interchange) and
Unicode. In the past other coding systems such EBCDIC (Extended Binary Coded
Decimal Interchange Code) were used. Note: EBCDIC is pronounced eb-sih-dik.
Unicode is the current standard as it includes characters and symbols for all current
languages. In addition Unicode includes all of the original ASCII character set. In the
next section, we examine ASCII and Unicode in more detail.

GROUP TASK Discussion

Unicode is the standard method of representing characters on the Web.
What if different coding systems were in common usage? What problems
would this present to software developers? Discuss. '

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 422 Chapter 10

ASCII Code
ASCII is an acronym for American Standard Code for Char Dec Char Dec
NUL 0 @ 64
Information Interchange and is pronounced ass-kee. ASCII SOH 1 A 65
is a seven-bit code, which means there are 128 different STX 2 B 66
characters in the standard ASCII character set. ETX 3 C 67
EOT 4 D 68
ENQ 5 E 69
Many extensions to the standard ASCII character set ACK 6 F 70
emerged over the years; until recently most of these were 8 BEL 7 G 71
bit codes. By extending the code from 7 to 8 bits, another BS 8 H 72
HT 9 I 73
128 characters can be represented. Various different LF 10 J 74
extended ASCII systems arose during the 1980s until the VT 11 K 75
FF 12 L 76
ISO Latin 1 system became the defacto standard. ISO Latin CR 13 M 77
1 is another 8-bit system that includes the standard ASCII SO 14 N 78
character set. The International Standards Organization S1 15 0 79
DLE 16 P 80
developed this standard for use on the World Wide Web. DCI 17 Q 81
All these 8-bit systems use values above 127 to represent DC2 18 R 82
DC3 19 S 83
various foreign language, graphical and mathematical DC4 20 T 84
characters. For example, the character Yz in ISO Latin 1 uses NAK 21 U 85
SYN 22 V 86
code 189. The ISO Latin 1 codes together with ASCII are ETB 23 W 87
incorporated within the modem Unicode system. Therefore, CAN 24 X 88
code 189 in Unicode also represents the character Yz. The EM 25 Y 89
SUB 26 Z 90
standard ASCII codes shown in Fig 10.10 are correct for ESC 27 [ 91
both ISO Latin 1 and Unicode. FS 28 \ 92
GS 29 1 93
Standard ASCII has been developed to simplify the process RS 30 A
94
US 31 95
of sorting. Notice that the code for 'A' is less than 'B' is Space 32 96
less than 'c' and so on. Sorting alphabetically can be ! 33 a 97
" 34 b 98
accomplished using the numerical ASCII codes. 'A' has an # 35 c 99
ASCII value of 65 or 1000001 in binary, 'a' has a code of $ 36 d 100
97 or 1100001 in binary. Each capital letter has an ASCII % 37 e 101
& 38 f 102
code 32 less than its lower case equivalent. This difference 39 g 103
of 32 affects the value of the second highest order bit from a ( 40 h 104
) 41 i 105
o to a L * 42 j 106
+ 43 k 107
44 1 108
Consider the following: - 45 ill 109
46 Ii 110
I 47 0 111
0 48 P 112
The word 'HELLO' coded in ASCII is 72, 69, 76, 76, 79. 1 49 q 113
The 7 bit ASCII equivalent is 1001000, 1000101, 1001100, 2 50 r 114
1001100, 1001111. 3 51 s 115
4 52 t 116
The lower case word 'hello' can be similarly coded as 104, 5 53 u 117
6 54 v 118
101, 108, 108, Ill. In binary, we get 1101000, 1100101, 7 55 w 119
1101100, 1101100, 110111 L 8 56 x 120
9 57 y 121
Notice that the last 5 bits of each character are the same in : 58 z 122
upper and lower case.
59 r 123
< 60 J 124
= 61 } 125
> 62 - 126
GROUP TASK Discussion ? 63 DEL 127
Explain how the above situation can assist
Fig 10.10
when sorting and searching strings of
The ASCII character set.
characters.

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 The interrelationship between software and hardware 423

Unicode
Unicode specifies a unique number for every character in every language. Prior to the
introduction and acceptance of Unicode in the 19908 there were many different
coding systems in use for different languages. This meant that many codes referred to
quite different characters and hence global communication of text in electronic form
was difficult and often involved complex conversion. Currently Unicode is the global
standard for coding characters. New characters and languages, including ancient
scripts, are continually being added to the Unicode standard. The current standard
including all coded characters is available to all at www.unicode.org. Once a code is
assigned to a particular character then it will never change. This guarantee means any
text coded using Unicode will be readable forever by any Unicode aware software.
To represent every current and future character in any language clearly requires a
large and complex system. The Unicode system is based on a total of 17 code planes.
Each code plane is 16-bits long; therefore each plane can include up to 2 16=65536
different characters. A total of around 1 million unique characters can be represented.
The first plane, plane 0, is called the Basic Multilingual Plane or BMP. The 65536
code points on the BMP include all the characters for most modem languages in use
today. The remaining 16 code planes are largely unused apart from some ancient
languages and various specialist symbols.
Within the 16-bit Basic Multilingual Plane (BMP) are aU the ASCII characters whose
code points are identical to their corresponding ASCII codes. For example, an upper
case "A" uses code 65 (or 41 16) in both ASCII and Unicode. Many of the earlier ISO
Latin 1 codes are also identical. Furthermore many characters from other languages
have been assigned codes so that conversion between older systems and Unicode is
straightforward.
GROUP TASK Practical Activity
In Microsoft Word any character can be displayed by entering its Unicode
...
hexadecimal code point value followed by Alt-x. Type your name using
this "Alt-x" system of data entry.

The Unicode standard recommends that code points should be specified using "U+"
followed by the hexadecimal value of the character, so capital "A" is specified as
"U+0041". As the BMP is plane 0 then 16-bit values (4 hexadecimal digits) are
assumed to be from the BMP. Characters from planes 1 to 16 are expressed using an
extra one or two hexadecimal digits. For example "U+IFOA1" through to
"U+ 1FODF" are characters representing playing cards, i.e. through to
The leading 1 means these codes are found on plane 1.
There are three Unicode standards for representing text namely, UTF-8, UTF-16 and
UTF-32, which unsurprisingly use 8-bits, 16-bits and 32-bits respectively to represent
characters. UTF-8 is within the majority of web page files, UTF-16 is widely used
within many desktop applications and UTF-32 is currently rarely used. At first glance
these usage comments may appear strange as the range of Unicode characters is from
0 16 up to 1OFFFF 16. The maximum value of lOFFFF 16 includes 6 hexadecimal digits
which correspond to 24-bits so surely 8~bits or 16-bits are insufficient? Clearly the
encoding system cannot use just 8-bits or even 16-bits to represent all the possible
Unicode code points. To overcome this problem both UTF-8 and UTF-16 use
multiples of 8-bits (or 16-bits) to represent many of the less commonly used and
numerically larger code points. This means the more common characters can be stored
much more economically than is the case with UTF-32.

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 424 Chapter 10

GROUP TASK Research Activity

Just because Unicode specifies a code point for a character does not mean
that every font will include that character. Research and locate a font
which includes the playing card characters U+1FOAl through to
U+1FODF referred to above.

Consider UTF -8 encoding:

The Unicode code points range from 0 16 up to 10FFFF 16. UTF-8 encoding requires
from one to four bytes to represent each possible Unicode code point. All the ASCII
characters require a single byte and their codes are identical to the corresponding
ASCII code which is a significant advantage over UTF-16.

Unicode Number of bits in

Binary range of code point UTF -8 encoding
range code point

U+OOOO to
U+OO7F
o to 1111111 1 to 7 Oxxxxxxx

U+0080 to
10000000 to 11111111111 8 to 11 110xxxxx 10xxxxxx
U+07FF

U+0800 to 100000000000 to 1110xxxx 10xxxxxx

12 to 16
U+FFFF 1111111111111111 10xxxxxx

U+lOOOO to 10000000000000000 to 11110xxx lOxxxxxx

17 to 21
10FFFF 100001111111111111111 10xxxxxx 10xxxxxx
Fig 10.11
Unicode UTF-8 encoding

Notice that each of the multiple byte UTF-8 encodings begins with the same number
of 1s as there are bytes in the encoding. This feature allows software to determine the
byte length of each encoded character as it is being read. In addition all subsequent
bytes in a multi-byte encoding commence with 10. This removes all ambiguity as all
bytes beginning with a zero are single bytes (same as ASCII), all bytes commencing
with 11 are the start of a multi-byte encoding and all bytes commencing with 10 are
subsequent bytes within a multi-byte encoding.
'ill An upper case "A" is code point U+0041 (65 in decimal) which is 1000001 in
binary and would be stored in a UTF -8 file as the single byte 01000001 2 which is
simply 41 16.
fI The Greek letter pi "11:" is code point U+03CO (960 in decimal) which is in the
range U+0080 to U+07FF and is 1111000000 in binary. From Fig 10.11 the
required UTF -8 encoding is 110xxxxx 10xxxxxx which includes 11 x symbols,
however there are 10 digits in 11110000002 so we need to add a leading 0 to make
the required 11 x symbols. Therefore the character "n" in UTF -8 is represented by
11001111 100000002 which is CF80 16.

GROUP TASK Practical Activity

We noted earlier that U+1FOAl through to U+1FODF are characters
representing playing cards. Determine the code point for the Ace of
hearts and convert this value to its UTF-8 representation.

Software Design and Development -The HSC Course

 The interrelationship between software and hardware 425

Consider UTF -16 encoding:

The Unicode code points range from 0 16 up to 10FFFF 16 . UTF-16 encoding uses
either one or two 16-bit sequences to represent each Unicode code point. In UTF -16
all the plane 0 (BMP) characters are simply represented identically to their code point.
For instance U+0041 is represented by the 16-bits 00000000 01000001 2 which is
0041 16 . Code points in planes 1 through to 17 require a pair of 16-bit codes or a total
of 32-bits per character. These 16-bit pairs are known as surrogates. The first is called
the lead (or high) surrogate and the second is called the trail (or low) surrogate.
Notice that for every ASCII character in UTF-l6 the leading byte is a sequence of
eight zeros. Clearly this is an inefficient use of storage, partiCUlarly for files which
contain only ASCII text. However, for processing purposes this issue is minor as for
virtually all current CPUs and RAM modules 16-bits is the smallest addressable unit.
Even if UTF-8 encoding is used then ultimately 16-bits per character are utilised
during processing.
Let us consider the system used to calculate UTF -16 surrogate values for code planes
1 to 17. These Unicode code points are in the range U+10000 to U+lOFFFF, therefore
we can immediately subtract 10000 16 from each code point and save one hexadecimal
digit (4-bits). We now have values in the range 0 16 to FFFFF 16 which in binary
requires 20-bits. If we split the 20-bits into two equal parts then each part will contain
lO-bits in the range 0 16 to 3FF 16 as 111111111 h (ten binary ones) is equal to 3FF 16.
The high 10-bits are added to D800 16 to form the lead surrogate and the remaining
low 10-bits are added to DCOO l 6 to form the trail surrogate. few example
calculations will help to explain the conversion process.
It Both upper case "A" (code point U+0041) and the Greek letter pi "n" (code point
U+03CO) are in code plane 0 as they are less than U+lOOOO. Hence in UTF-16 they
are simply represented by their code point values 0041 16 and 03C0 16 respectively.
«I The Queen of Spades character is code point U+ 1FOAD. As U+ IFOAD is greater
than U+ 10000 we need to calculate surrogates.
- First we subtract 10000 16 from IFOAD 16 which leaves FOAD 16 .
We convert FOAD 16 into binary which gives us 111100001010110h
We need this as a 20-bit number so we add leading zeros resulting m
0000111100001010110h
- Split 000011110000 10 10 11 0 b into two to create the 10-bit numbers
00001111002 and OOlOlOllOh Which in hexadecimal is 03C 16 and OAD 16 .
Add 03C 16 to D800 16 to form the lead surrogate D83C 16.
- Add OAD 16 to DC00 16 to form the trail surrogate DCAD I6 .
- Therefore U+IFOAD is represented in UTF-16 by D83CDCAD 16 which
converts to the 32-bit binary number 1101100000111100 110111001010110h .

GROUP TASK Discussion

Code points U+D800 to U+DFFF in plane 0 are reserved and are never
to be used for nay characters. Can you explain why? Discuss.
-
GROUP TASK Practical Activity
Convert Unicode code points U+03Bl and U+1F692 into UTF-16. What
characters do these code points represent?

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 426 Chapter 10

.+.(l>( 24) + (1 X i) + (1 X2°) 6. the dec;imal nurilber255 is egll~l totlie

. ipbjn~as: he.l<~q~~itn~llJyt1lber: '
.FOf
n' Jll1
"', ,"~),;, ,

2.,

4.

5.

11. are'.i.isedtc,;.rei9re~lent nnjril'ij:Hthil1()olnptlflers~;w)lfifll~i:fiJ(ifge. siii1~!er iftneyuse4

~i~~f!c;l\1,~~"t:~al~()f~~'i\lV:l1~ c.Qmputel~Suls~ . lth~bA~IWlY nUmber/system :ratqe~;tpantlie

12.

13.

14.

15.

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 The interrelationship between software and hardware 427

INTEGER REPRESENTATION
Integers are whole numbers, both positive and Complex Numbers
negative. For example, 456, 12,0, -1 and -3965 are all
integers, 3V4, n, -2.995, 0.888... and -/2 are not Real Numbers
integers, rather they are real numbers. Integers form a
subset of the real numbers. Zero is a special integer; it
is neither positive nor negative.
We have already seen how positive integers and zero
Fig 10.12
can be represented using binary on computers. How
1ntegers are a subset of the real
do we represent negative integers using only zeros numbers, which in turn are a subset
and ones? We can't use a '-' sign directly as of the complex numbers.
computers can only work with zeros and ones. A
number of techniques have been developed. The aim of each technique is to provide a
system that allows accurate and efficient calculations to take place.
In this section, we examine two integer representation techniques:
.. Sign and modulus.
" Two's complement (and one's complement).
Sign and modulus
The sign and modulus method is perhaps the most obvious solution. We just add an
extra bit to the front of each number to represent the sign of the number. A zero is
used for positive numbers and a one for negative numbers. The modulus is the
magnitude of the number or the absolute value of the number. Mathematically the
absolute value of a number is the distance from the number to zero.
If we are using 7 bits for the modulus then the number 12 would be represented as
00001100 and -12 as 10001100. Using this system, zero can be represented in two
ways; either 10000000 or 00000000.

Consider the following:

Using the sign and modulus method, the sign of the number is not an integral part of
the number. This means that calculations must take account of the sign bit separately
to the actual calculation. This is essentially what we do when adding or subtracting
negative numbers by hand. For example, when adding say 12 and -7 we know that
adding a negative is the same as subtracting, so we perform the calculation 12 - 7 and
get the result 5. Computers find subtraction unnecessary and hence the sign and
modulus method is not generally used on modern computers.

GROUP TASK Discussion

The sign and modulus technique is difficult to implement on a computer
because computers are not real smart. They just like to add things, mind
you they can add at lighting speed, subtraction they find difficult and
unnecessary. Can you think of any integer subtractions that cannot be
rewritten as additions? Is subtraction really necessary? Discuss.

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428 Chapter 10

Two's complement (and one's complement)

Working out a method of representing integers where the sign of the number is
included as an integral part of the representation is solved using complements. Let us
discuss the thinking behind this method using the decimal system before we
implement it in binary.

Consider the following:

In primary school, you most likely used a number line, in

Year 7 this number line was extended to include negative
numbers. Mathematically the number line extends
infinitely in both positive and negative directions. For a I I I I I

moment, imagine we dispense with the negative or left o 250 500 750 1000

hand side of the number line and that our positive numbers o
are finite, say with a maximum value of 1000. Imagine we
join the ends of this finite number line to form a circle (see
750 250
Fig 10.13).
Now if we move in a positive or clockwise direction our
integers increase in value. If we move in a negative or 500
anti-clockwise direction our integers decrease in value, Fig 10.13
with one important exception, zero. Moving anti- Wrapping a finite positive
clockwise from zero we would like to decrease into the number line to form a circle.
negative numbers, -1, -2, -3 and so on, instead we reach
999, 998, 997 ... These numbers are complements of their positive equivalents, in our
example the ten's complement of 1 is 999, of 2 is 998, of 3 is 997 and so on. Each of
these pairs of numbers is the same distance from zero on our circular number line.
We cannot have 999 representing both -1 and 999 so we need to develop some rules.
Let us make sure there are an equal number of positive and negative integers.
Positive's run from 0 to 499 and negatives from 999 down to 500.
Now let us test our results using normal addition. For example -3 + -5, using our ten's
complement system this becomes 997 + 995 giving us a result of 1992. If we discard
the leading 1, we get the correct answer 992, which using our system is equivalent to
-8. Let us try -6 + 19, this becomes 994 + 19 resulting in 1013. Discarding the leading
1 gives us the correct result 13.

GROUP TASK Activity

Perform the following additions using our number system developed
above: 18 + -25, -100 + 109, -5 + 5 and -15 + -39. Make sure you
understand this system thoroughly before moving onto the next section.

GROUP TASK Discussion

Remember the aim was to develop a system where no sign is required for
negative numbers. How has this been achieved? Does the above number
system work with subtraction, multiplication and division?

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 The interrelationship between software and hardware 429

We now examine this system as it is applied to binary numbers. Generally, integers

are stored within computers using 16,32 or 64 bits. For our discussion, we will use 8
bits to help simplify the 00000000
mathematics. With 8 bits, we can 11111111 00000001
11111110 ~_--- __ 00000010
represent numbers from 00000000
up to 11111111. If we form a
circular number line using these Fig 10.14
numbers, we see that 11111111 Section ofan 8 bit circular number line.
should be used to represent -1. Fig
Positive Negative
10.14 shows the significant part of
Decimal Binary Decimal Binary
this circular number line on either side of zero. 1 00000001 -1 11111111
Let us examine pairs of positive and negative 2 00000010 -2 11111110
numbers using this system. Fig 10.15 shows the 3 00000011 -3 11111101
4 00000100 -4 11111100
first sixteen integers along with their two's
5 00000101 -5 11111011
complement. For example, the two's complement -6
6 00000110 11111010
of 0000000 1 is 11111111. 7 00000111 -7 11111001
A number ofpattems emerge. Firstly, each positive 8 00001000 -8 11111000
number commences with a 0 and each negative 9 00001001 -9 11110111
10 00001010 -10 11110110
with a 1. In fact, it turns out that this is always the
11 00001011 -11 11110101
case regardless of the number of bits used. 12 00001100 -12 11110100
Secondly, exchanging Is for Os and Os for Is 13 00001101 -13 11110011
almost results in the correct two's complement, in 14 00001110 -14 11110010
15 00001111 -15 11110001
fact the result is out by 1. For example, 7 is
16 00010000 -16 11110000
00000111, swapping Is and Os gives 11111000,
which has a value of -8. If we add 1 to this result, Fig 10.15
Two's complements for the first
we get the correct answer 11111001. sixteen integers.
This process of swapping 1s and Os results in the
one's complement of the number. Why is it called the one's complement? Because the
swapping of 1s and Os can be achieved by subtracting the number from a string of 1s.
For example, 11111111 - 00110111 results in 11001000, hence the name one's
complement. It is possible to perform arithmetic using ones complement numbers,
however the two's complement system proves to operate more efficiently.
Further analysis of our two's complement table in Fig 10.15 reveals another simpler
method of calculating two's complements. Begin reading the original binary number
from the right hand side moving one digit at a time to the left. As soon as a one is
encountered commence swapping Is and Os, just don't change the first one. For
example, if we wish to find the two's complement of 12, which is 00001100 in binary.
Scanning from the right hand side, we encounter a 1 in the third position from the
right. Leave this 1 and then swap all the 1s and Os to its left; the result is 11110100,
which is correct!
GROUP TASK Activity
Extend the table in Fig 10.15 to include all possible 8-bit integers that can
be represented. What is the range of integers represented using 8 bits?

GROUP TASK Activity

Write down ten 8-bit two's complement numbers, 5 positive and 5
negative. Convert each number to its two's complement. Confirm that the
system works to convert negatives to positives as well as positives to
negatives.

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430 Chapter 10

We mentioned above that all positive two's complement numbers commence with a
zero and all negatives with a one. This information is particularly useful if we wish to
convert a two's complement number into decimal.
Using our 8-bit two's complement system -12 is represented as 11110100. Each
binary digit has a place value, commencing from the right hand side with 20=1,2 1=2,
22=4 , 23=8 , 24=16 , 25=32 , 26=64 and the -128 64 32 16 8 4 2 1 Decima!
last or left hand bit has a place value of 1 1 1 1 0 1 0 0 -12
_27= -128. The bit on the left hand side is 0 1 0 1 1 0 1 0 90
1 0 0 0 0 1 0 1 -123
often called the 'highest order bit' or the 0 0 0 0 1 1 0 1 l3
'most significant bit'. We can write
64 64
11110100 as -128 + 64 + 32 + 16 + 0 + 4 32 16 8
+ 0 + 0 which equals -12. If we were 16 8 4 4
performing many of these conversions, it 4 2 1 1 Working
116 90 5 13
is convenient to draw up a table such as - 128 - 128
the one in Fig 10.16. Add up all the - 12 - 123
positive values first and, if necessary, Fig 10.16
subtract 128 at the end. Table for converting two's complement to decimal.

GROUP TASK Activity

Draw up a table, like the one in Fig 10. 16. Randomly fill in the table with
ones and zeros. Convert each number to its decimal equivalent.

GROUP TASK Discussion

Most computers use 16, 32 and/or 64-bit two's complement to represent
integers. What is the range of integers that can be represented using each
of these three representations?

REPRESENTATION OF FRACTIONS AND REAL NUMBERS

Computers cannot represent all the possible real numbers precisely. We have the same
problem when writing decimals; we cannot precisely write the fraction 1~ as a
decimal. However, we can write it as accurately as we wish. For example, 1·33333 is
a better approximation than 1·3. What we require is a system that will provide us with
a satisfactory level of accuracy for the majority of applications. Note that our two's
complement system is able to represent integers precisely, albeit within a limited
range.
There are two methods used for representing fractions; fixed-point and floating-point.
Both these methods are similar to the method we use to write decimal fractions. For
example, 475·382 means 4 hundreds, 7 tens, 5 units, 3 tenths, 8 hundredths and 2
thousandths. In expanded form, we write 475·382 as (4 x 102) + (7 X 101) + (5 x 100)
+ (3 x 10- 1) + (8 x 10-2) + (2 x 10-3). We can do the same with binary fractions. For
example, 101 ·1101 means 1 four, 0 twos, 1 unit, 1 half, 1 quarter, 0 eighths and 1
sixteenth or in expanded form as (1 x 22) + (0 X 21) + (1 x 20) + (1 X Z-1) + (1 X Z-2) +
:!
(0 x 2-3) + (1 x Z-4). This number in decimal is 4 + 1 + ~ + ~ + l~ = 5 = 5·8125.
Let us now examine the difference between fixed-point and floating-point
representations.

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 The interrelationship between software and hardware 431

Fixed-point
Fixed-point refers to the position of the decimal point. When using fIxed-point
numbers the decimal point remains in the same position for all numbers. For example,
a fIxed-point system using 16 bits may have 8 bits for the whole number part and 8
bits for the fractional part. The problem with such a system is that very large numbers
and very small numbers cannot be represented. The smallest positive number that can
be represented using two's complement and 16 bits is O.OOOOOOOlz = 0.00390625 10
and the largest is 01l11111.1111111lz = 127.9960937510.
Fixed-point numbers are not included as standard data types in most high-level
languages; rather, they are created by programmers using one of the integer data
types. Fixed-point representations are generally faster and more accurate than
floating-point, unfortunately for most applications their range is insuffIcient so
floating-point numbers are used. Many specialised applications where the range of
numbers is small yet accuracy is important will used fIxed-point representations. The
fIxed-point method is essentially the same as the two's complement system with the
decimal point shifted to an appropriate position for the particular application.
Floating-point
Floating-point numbers can be thought of as generalised fIxed-point numbers. The
position of the decimal point is encoded within the format. In this way, the decimal
point can be placed in a different position within the number. Essentially, the number
is stored using scientifIc notation. For example, in decimal 2345.678 can be written as
2.345678 x 103 , which is often written as +2.345678E+3. There are three essential
components to each number; the mantissa which in sign mantissa exponent
this case is 2.345678, the exponent which is 3 and the
sign of the number, in this case +. The value of the ~ ~ ~
exponent determines the position of the decimal point. +2.345678 X 10 3

The floating-point system allows us to represent a Fig 10.17

much larger range of numbers using less storage Three components necessary for
specifying a floating-point number.
space. For example, 0.000000000000000000000052
can be written as +5.2E-23.
Working with floating-point numbers, compared to integers, is a complicated and
processor intensive process. Today's microprocessors contain a special maths
coprocessor called a Floating-point Unit or FPU. The FPU is dedicated to the
processing of floating-point numbers.
The Institute of Electrical and Electronics Engineers (IEEE) has produced a standard
for representing binary numbers on computers using the floating-point system. IEEE
Standard 754 specifies two formats; single precision, using 32 bits, and double
precision, using 64 bits. All the major hardware and software developers have
accepted these standards.

GROUP TASK Discussion

Fixed-point calculations are supposedly less processor intensive that
floating-point calculations. Why do you think this is the case? Use decimal
examples to explain your answer.

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 432 Chapter 10

IEEE 754 single precisionjloating-point standard.

This standard requires 32 bits, the
1 11001010 11001000000000000000000
first bit is the sign bit, the next eight
bits are used to store the exponent and .tLyJ"
SIgnexponent
y
mantIssa
.)
the final twenty-three bits are the (I bit) (8 bits) (23 bits)
fractional part. Fig 10.18 shows the Fig 10.18
binary number -1.11001 x 2 1101 The IEEE single precision floating-point
represented using this standard. Let us standard uses 32 bits to represent each number.
examine each component in turn.
The sign bit is simply set to 0 if the number is positive and 1 if the number is
negative. As -1.11001 x 2 1101 is a negative number, the sign bit is set to 1.
The actual value of the exponent can be either negative or positive. This presents a
problem, how do we represent the sign of the exponent most efficiently? We could
use one bit of the 8 bit exponent to represent its sign, we could use the two's
complement system or is there a better way? The standard specifies that the exponent
is represented as the actual value plus 127. Because we have 8 bits for the exponent,
we can represent integer values from 0 to 255. Subtracting 127 gives us a more useful
actual range from -127 to 128. In our -1.11001 x 2 1101 example, the exponent is 110h
which in decimal has a value of 13. If we add 127 to 13 we get 140, 140 in binary is
110010102.
The mantissa is essentially the same as the original number with one modification.
Because we are working in binary, the first digit, to the left of the decimal point, will
always be a one. The IEEE standard specifies that a leading one is always assumed. In
our -1.11001 x 2 1101 example, the unsigned mantissa is 1.11001; we ignore the leading
1 so our mantissa becomes 11001.
Let us consider the range of numbers that can be represented. Initially, we would
assume the largest number to be represented by a zero followed by 31 ones and the
smallest negative using 32 ones. The IEEE 754 standard includes a number of special
cases, which give special meanings to numbers with exponents containing eight ones.
As a consequence, the largest exponent is 11111110. Let us calculate the decimal
equivalent of the range:
• Largest = 0 1111111 0 11111111111111111111111 (IEEE 7 54 Single)
• Smallest = 1 11111110 11111111111111111111111 (IEEE 754 Single)
• The exponent is made up of 7 ones and a zero, 11111110 is 254 in decimal. Now
254 - 127 is 127, the decimal exponent.
• The mantissa is a series of 23 ones, 11111111111111111111111. We need to add
the leading one, giving the binary fraction 1.11111111111111111111111. This
value is very close to the decimal number two.
• The largest number in decimal is therefore 2 x 2127 which is equivalent to 2 128 .
Using a calculator the largest number becomes approximately 3.4 x 1038 , therefore
the range of numbers that can be represented is approximately -3.4 x 1038 to
3.4 x 1038 .

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 The interrelationship between software and hardware 433

There are a number of mathematical operations that cannot be computed, for example
division by zero and finding the square root of negative numbers. We also require a
method for representing infinity and negative infinity. As a result of not including the
leading one III the
mantissa, we also require a Infinity o 11111111 00000000000000000000000
special case for zero. Negative Infinity 1 11111111 00000000000000000000000
These special cases have Zero o00000000 00000000000000000000000
been included in the IEEE Negative Zero 1 00000000 00000000000000000000000
754 standard. Fig 10.19
Not a Number x 11111111 xxxxxxxxxxxxxxxxxxxxxxx
shows the representations
for each of these cases. Fig 10.19
Special cases in the IEEE 754 floating-point standard.
The not a number case is
used for meaningless
operations such as division by zero and square roots of negative numbers. In these
cases, an error code is often coded into the mantissa part of the number. This allows
feedback to be returned to programmers on the nature of the meaningless operation.
IEEE 754 double precisionjloating-point standard.
This standard uses 64 bits to represent
1 110 1111111 0 11 00 10000 ... 00000000
each number. A sign bit, 11 bits for I "- m ... u) \.. ../
IV -----y-- Y
the exponent and 52 bits for the
sign exponent mantissa
mantissa. (I bits) (11 bits) (52 bits)

The extra exponent bits extend the Fig 10.20

The IEEE double precision floating-point
range of double precision numbers to standard uses 64 bits to represent each number.
approximately _10 308 to 10308 base 10.
Also, to enable the representation of negative exponents, we represent the exponent as
the actual value plus 1023. The extra mantissa bits increase the accuracy of
computations. Of course, these benefits require extra processing power. The
remainder of the IEEE 754 double precision standard is the same as the single
precision standard.

GROUP TASK Activity

Write down the smallest positive number using the IEEE 754 single
precision standard. Convert this number to a decimal. Perform the same
process using the smallest positive double precision number. Compare
these two results.

GROUP TASK Activity

Write down five single precision floating-point numbers. Convert each
number to its decimal equivalent.

GROUP TASK Discussion

1023 is added to the actual value of the exponent when using the IEEE
754 double precision format. Explain why this is the case?

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 434 Chapter 10

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The interrelationship between software and hardware 435

Software Design and Development - The HSC Course

 436 Chapter 10

BINARY ARITHMETIC
The four operations of addition, subtraction, mUltiplication and division can be
accomplished in binary using similar techniques as those used with decimals. Because
we have only two digits in binary, 1 and 0, these operations become simpler, we need
only know number facts involving 0 and 1. Unfortunately, performing operations on
large numbers becomes somewhat tedious, as binary numbers tend to be much longer
than their decimal equivalents.
In this section, we will examine the four arithmetic operations using two's
complement integers. Similar processes are involved when using fixed and floating-
point real numbers, however multiple computations are required. For example,
consider multiplying two decimal numbers written in scientific notation; the mantissas
are multiplied, the exponents are added, then the result is normalised so the mantissa
is between 0 and 10. Multiplication of floating-point numbers involves similar
processes.
Let us examine each of the four operations in tum:
Binary addition
When we first learnt addition in primary school, we were
-, --
taught all our basic number facts with numbers up to 10. + 0 I
For example, 5 + 3 = 8, 6 + 9 = 15, 0 + 5 = 5, etc ... ; 100
different number facts in alL In binary, we need only learn 0 0 1
a total of five number facts. In fact, the only binalY
addition number facts required are 0 + 0 = 0, 0 + 1 = 1, I 1 10
1 + 0 = 1, 1 + 1 = 10 and 1 + 1 + 1 = 11.
1+1+1=11
The method of performing addition in decimal can also be Fig 10.21
used for binary addition. Each column is added Binary addition numberfacts.
commencing with the right hand side. If the result is 10 or
11 then a 1 is carried to the next column.

Consider the following:

Using 8 bit twos complement perform the following additions:

1. 01010111 + 2. 01011101 + 3. 11 000000 +

00011100 01110100 01110000
1. Let us examine the working for this question in detail.
1 II I 1I 111
01010111 + 01010111 + 01010111 + 01010111 + 01010111 + 01010111 +
00011100 00011100 00011100 00011100 00011100 00011100
1 11 011 0011 10011 01110011
1+0=1 1+0=1 1+1=10 1+0+1=10 1+1+1=11 1+0+0=1,
write 0 carry 1 1+0= 1, 0+0=0
The method, or algorithm used to perform binary addition is the same as that used for
decimal addition. Remember that 102 is the same as the decimal value 2 and 1 h is the
same as the decimal value 3. The result 01110011 is positive, as the leading bit is a
zero.

Software Design and Development -The HSC Course

 The interrelationship between software and hardware

2. Applying the same technique used above we get the result 11111
01011101 +
437
!
11010001 (see Fig 10.22). This result is a negative number
01110100
in 8 bit two's complement, as the leading bit is a one. How
can this be when the numbers in the question are both 11010001
positive? Let us examine the question in decimal.
Fig 10.22
0101110lz = 9310 and 011101002 = 116 10, in decimal 93 + An overflow error occurs
116 = 209. 209 is outside the range of values available in 8 if the result is outside the
bit two's complement, so the result has wrapped around allowable range.
into the negatives. (8 bit two's complement has a range
from -128 to 127). If this situation occurs in source code, an overflow run time
error would result. Programmers need to be careful that the data type chosen is able
to contain the results of any calculations within their source code.
3. This question results in a carry in the final stage of the 11
11000000 +
addition (see Fig 10.23). As we have only 8 bits to work with,
01110000
we ignore this last carry. Ignoring the final carry, in this case,
effectively causes the result to wrap around past zero. As the 00110000
result is still within the range of our two's complement Fig 10.23
system no overflow error results and the correct answer is Ignore any final carry
calculated. In decimal, this question is the equivalent of -64 + when using the two's
112 = 48. complement system.

Let us summarise what we have learnt about two's complement No error

addition from Questions 2 and 3: ~

• Calculations that move through zero will not result in errors,
as the answer will still be within the allowable range. For
-64 64
example, -45 + 50 and 12 + -18.
• Calculations that result in values outside the range will
result in overflow errors. For example, -90 + -45 and 105 +
35. ~
Overflow error
• Carries occurring in the final stage of an addition can always Fig 10.24
be ignored. Two's complement
addition special cases.

GROUP TASK Activity

Perform each of the following binary additions:
1. 01011111 + 2. 01110101 + 3. 11010000 +
00001100 00110110 01100011
Assuming these numbers are expressed using 8 bit two's complement, will
any errors occur? Perform each addition in decimal to confirm your
results.

GROUP TASK Investigation

Examine the binary addition function available on your pocket calculator.
Determine whether two's complement is used. How many bits are used?
How are overflow errors reported?

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 438 Chapter 10

Binary subtraction
Although binary subtraction can be performed in a similar way as we perform decimal
subtraction, computers do not use it, rather we add the negative. For example 5 - 3 is
the equivalent of 5 + -3. This process can be used to convert all subtractions to
additions. When working with two's complement binary numbers we convert the
number being subtracted to its two's complement and then add.

Consider the following:

Using 8 bit twos complement perform the following subtractions:

L 01010111- 2. 00011001-
00011100 11111011
1. Let us examine the working for this question in detail. Firstly, we need to find the
two's complement of the number being subtracted. In this case the number,
00011100, is positive as the leading bit is a zero, so we Swap I s Leave the
expect the two's complement to be negative. We can find and Os first 1
the two's complement in two ways; find the one's Find the ~I
complement and add one or scan from right to left and negative 00011100
swap l' s and Os after the first 1 is encountered. 11100100
'--y----J
Two's complement
For this question, we will use the second method.
11 1
Scanning 000 III 00 from the right hand side, we 01010111 +
encounter a 1 in the third position, leave this 1 as is and then { 11100100
add
change all the other digits. Our result is 11100100, which
is negative as expected. 00111011

Performing our addition, 01010111 + 11100100, gives us Fig 10.25

Subtraction is performed
the result 00111011. In decimal, we have completed the
by adding the negative.
subtraction 87 - 28 = 87 + -28 = 59.
2. In this question, the number being subtracted is negative
as the leading bit is a 1. We need to convert this number, 11111 011, to its two's
complement, which will be positive. Let us find the one's complement and add 1.
The one's complement is found by swapping Is and Os. The one's complement of
11111011 is therefore 00000100. Adding 1 to this result gives us 00000101, which
is positive as expected.
Adding the two numbers 00011001 and 00000101 yields the result 00011110. In
decimal we have performed the subtraction 25 - -5 = 25 + 5 = 30.

GROUP TASK Activity

Perform each of the following 8 bit tvw's complement binary
subtractions:
1. 10010111- 2. 01110001- 3. 01010011-
00001101 00110110 11110011

GROUP TASK Discussion

Microprocessors are not hardwired to perform subtraction. Why do you
think this is the case?

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 The interrelationship between software and hardware 439

Binary multiplication
The method used to multiply in binary is the same as that used for decimal.
Fortunately, in binary we only have the two digits 0 and 1. Multiplying by 0 or 1 is
certainly an easier proposition than multiplying by 0, 1,2,3,4,5,6, 7, 8 or 9.
Let us consider a simple example: 1001 x 101, which in decimal 1001x
is 9 x 5. The working for this multiplication is shown in Fig 101
10.26. Notice that each row in our working either contains all
zeros or it contains the first number in the multiplication shifted 1001
zero or more places to the left. Binary multiplication is often 00000
called 'Shift and add'. In essence, a microprocessor need not 100100
ktlow how to multiply if it is able to shift bits to the left and it 101101
can add.
Fig 10.26
We examined a number of 8086 assembler instructions in Binary multiplication
chapter 5. 8086 assembler includes a SAL and a SAR statement, can be performed like
meaning 'Shift Arithmetic Left' and 'Shift Arithmetic Right', decimal multiplication.
used in conjunction with the addition instructions ADD
(Addition) and ADC (Addition with Carry) binary multiplication is accomplished. All
microprocessors have the equivalent of these instructions hardwired as part of their
micro-code instruction set.
When performing multiplication by hand we perform
all our sub-multiplications first and then add them all
up at the end. Computers perform a shift (the
equivalent of a sub-multiplication) and add the result
to a running total. They then perform another shift
and add the result to the total, this process continues
until the multiplication is complete. Fig 10.27 shows
an algorithm that could be used to complete this
process. Binary multiplication when performed on Is Numl not No
equal to O?
computers is often called "shift and add".

Consider the following:

No Is the right Yes
hand bit of
Let us perform a desk check of the algorithm in Fig
10.27 to illustrate the processes performed by the
CPU when multiplying binary numbers. Let us
assume we are working with an 8 bit processor.
Using 1101 and 1001 as the inputs:
Product Numl Nurn2
00000000 00001101 00001001
00001001 00000110 00010010
00000011 00100100
00101101 00000001 01001000
Fig 10.27
01110101 00000000 10010000
Algorithm describing binary
This is the equivalent of the decimal multiplication multiplication using shifts and adds.
13 x 9 = 117. In reality, the CPU multiplying process
requires various other processes apart from those described.

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 440 Chapter 10

GROUP TASK Activity

Perform each of the following binary multiplications using the same
method used for decimal multiplication:
1. 1010111 x 2. 1110001 x 3. 1010011 x
1101 1110 110011

GROUP TASK Activity

Using 16 bit two's complement multiply -20 and 27. Convert these
numbers to binary and then use the algorithm in Fig 10.27 to perform this
operation. Confum that your binary result is equivalent to -540.

Binary division
Division in binary can be perfonned using the same techniques used with decimals.
Let us examine one common technique with a decimal example. We will then emulate
this technique in binary.
Let us consider 6925 . .;- 7. The working for this division is shown in 989
Fig 10.2B. The result is 989 with a remainder of 2, for our purposes, 7)6925
we are interested in integer division so we will ignore the 63
remainder. 62
56
Firstly, we ask ourselves how many times 7 goes into 6, it doesn't, 65
we could write a 0 up the top. We then ask does 7 go into 69, yes, 9 63
times, so we write a nine up the top. In fact, what we are doing is
2
calculating the number of times 7 goes into 6900. The answer is
Fig 10.28
900, we write a 9 in the hundreds column. We then perfonn the Decimal division
subtraction 69 - 63, this equals 6. We then bring down the 2 from example.
above and ask how many times 7 goes into 62, which is really how
many times does 7 go into 620. The answer is 80 times so we write an 8 in the tens
column. The process continues in this way until all digits have been brought down
from above.
Now let us consider this technique with a binary example, 1001
111010...;- 110. Does 110 go into 1, no, does 110 go into 11, no. 110)111010
We now ask does 110 go into 111, yes it goes in once, in fact it 110
will either not go in or it will go in once. Because we are working 1010
in binary this is always the case. Subtracting 110 from 111 leaves 110
us with 1. Actually, we are perfonning the binary subtraction 100
111000 - 110000, which is perfonned by computers by adding the Fig 10.29
negative. We bring down the next digit, a zero, and so on until we Binary division
have a number greater than 110, namely 1010. Subtracting 110 example.
leaves a remainder of 100. In decimal, we have perfonned the
division 58 . .;- 6 = 9 remainder 4.

GROUP TASK Activity

Perform each of the following binary divisions using the method
described above:
1. 1010101...;- 2. 1110101...;- 3. 1010011...;-
1101 1010 101

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 The interrelationship between software and hardware 441

Let us now consider the processes used by computers to perform division. Division is
the most complex of the four basic arithmetic operations and there are many complex
ways of performing binary division.
One common, yet complex, method involves the use of partial fractions. Using this
method the division is viewed as a fraction. For example, 58 -;- 6 is equivalent to 58/6.
This fraction is broken down into a series of partial fractions with denominators that
are all powers of two e.g. 58/6 "" 58/8 + 58/32 + 58/128 + 58/512 + 58/2048 +
58/8192. Evaluating each of these partial fractions in binary is straightforward.
Dividing a binary number by 2 is accomplished by shifting 1 position to the right.
Dividing by 4, shift 2 positions, dividing by 8, shift 3 positions, and so on. Adding up
each of these partial results yields the answer to the original division. Calculating the
partial fractions is a mathematical process that is beyond the scope of this course.
Nevertheless, it is important to realise that this method exists and is often used.
Another common method of performing BEGIN BinaryDivision
binary division on computers emulates the Get Num 1,Num2
. d h' Divisor = Num2
technIques use on t e preVIOUS page to WHILE Left hand bit of divisor is 0
perform division by hand. Fig 10.30 describes Shift Divisor left
an algorithm that could be used to implement END WHILE
this technique. This technique is often called Remainder = Num 1
'shift and subtract'. Initially the divisor is Quotient = 0
WHILE Divisor:2 Num2
shifted to the left of the available bits. We Shift Quotient left
then progressively shift the divisor to the IF Remainder:2 Divisor THEN
right. After each shift, we compare its value Remainder = Remainder - Divisor
with the remainder. If the remainder is larger, Quotient = Quotient + 1
ENDIF
we subtract and record a one in the quotient. Shift Divisor right
Eventually, the divisor will hold a value ENDWHILE
smaller than the original Num2 input, END BinaryDivision
signifying the process is finished. Fig 10.30
Algorithm for binary division.
Fig 10.31 shows a desk check of this
algorithm using 1110 10 and 110 as the initial Initially Numl is set to 00111010 and
inputs. In other words, we are performing the Num2 to 00000110 if we use an 8 bit
decimal division 58 -;- 6 in binary. system.
Divisor Remainder Quotient
GROUP TASK
00000110
Activity
00001100
00011000
Perform a desk check of the 'shift and 00110000
subtract' algorithm shown in Fig 10.30 using
01100000
111100 and 101 as the inputs. This is the
equivalent of 60 -;- 5 in decimal. 11000000 00111010 00000000
01100000 00000000
00110000 00000000
GROUP TASK
00011000 00001010 00000001
Investigation
00001100 00000010
00000110 00000100
Dividing by powers of 2 is simple in binary. 00000011 00000100 00001001
Do you agree wiLli this statement? Explain
Fig 10.31
using a number of examples.
Desk check a/the 'shift and subtract'
binary division algorithm.

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 442 Chapter 10

HSC style questions:

Question 1.
A programming language defines the Byte data type as follows:
Byte Data Type
Unsigned 8-bit (I-byte) integer ranging in value from 0 through 255
The language also includes a HexO function defined as follows:
Hex Function
Returns a string representing the hexadecimal value of a number
The following code in this language is executed:
10 Define A, B, C as Byte data type
20 A = 180
30 B = 9
40 C = A I B
50 Println Hex(A} + " divided by" + Hex{B} + ({ equals" + Hex(C)
(a) Line 10, 20 and 30 have executed. Determine the binary numbers held in
memory representing the contents of variable A and variable B. Show an
working.
(b) Manually perform the binary division the CPU would carry out to execute line
40. Show all working.
(c) Determine the output printed when line 50 is executed. Show all working.
(d) A new version of the same programming language redefines the Byte data type
as follows:
Byte Data Type
8-bit (1-byte) signed two's complement integer
Discuss possible affects of this data type change when the code above IS
executed.
Question 2.
The Single data type in a language complies with the IEEE 754 32-bit Single Precision
Floating Point standard.
(a) A variable of type Single currently contains the decimal value 20. The memory
location associated with this variable contains the following 32 bits:
01000001101000000000000000000000
Explain how the bit pattern above represents the decimal value 20. Show all
working.
(b) The Integer data type in this language is defined as follows:
Integer Data Type
32-bit (4-bytes) signed two's complement integer
Compare the Single and Integer data types in terms of their precision, range and
efficiency of processing.

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 The interrelationship between software and hardware 443

Suggested solutions
Qu.estion 1.
(a) 'A' contains 180 which we 'B' contains 9 which we
convert into binary: convert into binary:
180 9
~
2 0 ~ 2 1
-- --
90 4
2 0 2 0
--
~

--
45 2
2 1 2 0
--
22 1
2 0 2 1
--
11 0
2 1
~

(Check: 8 + 1 = 9 ~)
5
2 1
--
2
2 0
--
1
~
2 1
--
0
(Check: 128 + 32 + 16 + 4 = 180 ~)
Therefore the content of variable A is represented in memory as 10110100 and
the content of variable 'B' is represented in memory as 00001001.
(b) 10100
1001 ) 10110100
1001
1001
1001
000

(Check: 16 + 4 = 20 = 180/ 9 ~)
(c) A= 1011 01002 = (8+2+1)(4) =B416
B = 0000 100h = (0) (8+1) = 9 16
C = 0001 0100 2 = (1) (4) = 14 16
Therefore the output from line 50 is "B4 divided by 9 equals 14".
(d) There are two possible consequences of the change from unsigned to signed
two's complement. Both problems are with the number 180 stored in variable A
within the code. 180 is within the range of an unsigned byte (0 to 255) but is
outside the range of a signed two's complement byte (-128 to 127).
During execution a runtime error may occur if the programming language
detects the now out of range assignment of 180 to the Byte variable A.
The language may allow 180 and let it overflow such that it will be interpreted
as a negative number. This means that A (which holds the binary number 1011
0100) will not be interpreted correctly as 180. Because the leftmost bit is a 1,
the value would be interpreted instead as a negative number. Using two's
complement the decimal value of 1011 0100 = -128 + 32 + 16 + 4 = -76. This
will have obvious processing consequences in the code~ since the intended
number is not being used.

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444 Chapter 10

Question 2.
(a) Sign = 0
Exponent = 1000 0011
Mantissa = 01000000000000
With a bias of 127, the exponent = (128 + 2 + 1) - 127 = 131 - 127 = 4
With normalisation (add the leading 1), the mantissa = 1.01
Therefore the binary value = 1.01 x 24 = 10100
Which in decimal = 16 + 4 = 20
(b) Integer values represented as 2's complement signed integers using 4 bytes (32
bits) can take values from _2 31 to 2 31 - 1. Because they are integer values, all
whole numbers in this range can be represented exactly as sums of powers of 2,
with no need for approximations.
On the other hand, the maximum value that can be represented in a 4 byte
floating point number is
=011111110111111. .... 1
= +2(254-127) x 1.1111111. .. 1
"'" 2127 x 2
"'" 2 128
2 128 is clearly significantly larger than the maximum value of 231 - 1 able to be
expressed using the integer representation.
If integer representation is used, only whole numbers can be represented, no
fractional values are possible. If floating point representation is used, then it is
possible to represent a whole range of fractional values.
However, if floating point representation is used, there are a whole range of
numbers that cannot be expressed exactly (such as 9.45). All of these numbers
are therefore expressed as an approximation using all 23 binary places available
in the mantissa to provide a value very close to that required.
This can give rise to some unexpected results when comparing integer and
floating values, where it cannot be assumed that the integer representation is
exactly equal to the floating point value, which may be an approximation to the
required value as a result of previous calculations.
In terms of processing time required, arithmetic using floating point numbers is
nowhere near as straightforward or as efficient as arithmetic using binary
integers. In fact floating point arithmetic is performed by a special co-processor
chip (or floating point unit) as the mantissa and exponent need to be considered
separately and processed differently.
Notes
• In question 1 (a) when using the divide by 2 conversion method the answer is read
from top to bottom. Of course, alternative methods of conversion are equally valid.
• The suggested solutions for questions 1 (a) and (b) includes a check to ensure
correctness. This is easy to achieve and hence well worth the time it takes,
particularly when the question is given in decimal.
• It is important to show all working for these type of questions as often marks will
be awarded for correct working and in addition, working often prevents trivial
errors being made.

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 The interrelationship between software and hardware 445

SET10C

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446 Chapter 10

ELECTRONIC CIRCUITS TO PERFORM STANDARD

SOFTWARE OPERATIONS
In the previous section, we examined the mathematics involved in the processing of
binary numbers. In this section, we examine how these processes are implemented
using electronic circuits. For instance, how can an electronic circuit perform binary
addition or how can it be used to store
binary digits? The answer to these Electronic circuit
questions will help you to understand the A circular path along which
basis oftoday's digital computers. electrons (electricity) can flow.
Logic gates are the basic building blocks The circuit must be complete
for the creation of microprocessors. Used for this to occur.
in various combinations logic gates are
able to perform all the functions carded
out by computers. Essentially, computers Logic gate
are simply a collection of logic gates. The An electronic circuit that
branch of mathematics known as Boolean transforms inputs into outputs
algebra can be used to assist in the based on strict logical rules.
efficient design of circuits. Integrated circuits are made up
of combinations of logic gates.
We firstly examine the six basic logic
gates and then consider the process of
combining these logic gates to perform specific tasks.
LOGIC GATES
There are six basic logic gates that are used in the construction of integrated circuits;
AND, OR, NOT, NAND, NOR and XOR. To assist in our discussion of each of these
gates, we will use a series of switches together with a battery and light globe. The
position of each switch, either off or on, provides the input and the light globe
provides the output. For our purposes, a A
switch in the up or off position is represented ~
A B
by 0 and in the down or on position by 1. 1\l1~ B Input Output
Similarly, if the light globe bums this is a 1 0 0
and if it doesn't then that is a o. 1 1
Fig 1032 describes a simple circuit using Fig 10.32
just one switch. The table to the right of the A simple circuit. When switch A is up (0)
the globe B is out (0). When switch A is
circuit is caned a truth table. Truth tables are
down (1) globe B burns (1).
used to summarise all the possible inputs and
their resulting outputs for a particular circuit. In this case, an input of 0 results in an
output of 0 and an input of 1 results in an output of 1, a useful circuit if you want to
turn on and off lights but not particularly useful for processing data. We require
circuits that transform the inputs into required outputs.
In reality, both the input to and the output from a logic gate is either a high or low
voltage representing 1 (true) or 0 (false). This allows the output from one logic gate to
be the input for another.

GROUP TASK Discussion

In chapter 5, we learnt about how the fetch-execute cycle is used to
implement machine code instructions. Logic gates are the hardware
circuits used to perform machine code instructions.
How is this knowledge relevant to software developers? Discuss.

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 The interrelationship between software and hardware 447

AND gate
This circuit emulates the logical AND
°
operator. If is false and 1 is true then both
inputs must be true for the resulting output to
A
0
0
B
0
1
C
0
0
be true. The two switches A and Bare 1 0 0
1 1 1
connected in series; as a result, both switches
must be down for the globe to bum. Fig 10.33
AND gate. Both A and B must
The truth table contains two inputs, A and B, be 1 for the light to burn.
as a result there are 4 possible combinations
resulting in 4 rows in the table. It is convenient to write down each row in a logical
sequence. The combination of columns A and B is written in ascending binary order;
namely 00,01, 10, 11 which is the decimal equivalent ofO, 1,2,3.
Each logic gate is represented on circuit diagrams as a symbol. lr--·-·_·_·
Input 1

AND gates use a rectangle with a rounded right hand side. For
most purposes, two inputs are sufficient, however it is possible to ; :AQ-':
~ ; C
, B ; ,
design AND circuits using any number of inputs; 2, 3 or 4 inputs
are common. Fig 10.34 shows the symbol used to represent AND Fig 10.34
The symbol for an
gates. The logical expression A AND B is written in Boolean AND gate.
algebra notation as A·B or just AB.
OR gate
Either A or B must be true for the output to be
true. The two switches are connected in
parallel, therefore if either switch is in the A B C
down or on position the globe will light. It is 0 0 0
0 1 1
possible to have more than two inputs into an
1 0 1
~D-c
OR gate. As long as one or more inputs are 1 1 1
true (l) the output will also be true (l ).
Fig 10.35
Conversely, if all the inputs are false (0) then
OR gate. Either A or B must be
the output will be false (0). The logical 1 for the light to burn.
expression A OR B is written in Boolean
algebra notation as A+B.
NOT gate
The NOT gate is used to reverse the input; as
a result NOT gates are often called inverters.
If the input is false (0) then the output will be B
true (l) and vice versa. It is only possible to
have one input into a NOT gate. Remember
that in our representation using switches,
§±§ o
1
B
1
0
battery and globe that a switch in the up A-{>o-B
position is off (0 or false) and a switch in the Fig 10.36
down position is on (1 or true). NOT(A) is NOT gate. When switch A is up (0) the
globe burns (1). When switch A is
written in Boolean algebra notation as A . down (1) the globe does not burn (0).
The symbol for a NOT gate is a small hollow
circle. The triangle preceding the circle is really a buffer. Buffers are used to
synchronise timing, often your circuit will need to wait for the next input. Buffers can
be used to accomplish this task. NOT gates require buffers to ensure correct timing.

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448 Chapter 10

NAND gate
NAND is short for NOT AND, in other words a NAND gate
is logically the same as an AND gate fonowed by a NOT ~O{>o-c
gate. The output from a two input NAND gate is the opposite Fig 10.37
of that from an AND gate, that is 1110 rather than 0001. The A NAND gate is the
ability to use the output from one logic gate as the input for equivalent of an AND gate
followed by a NOT gate.
another provides the ability to combine gates to perform new
and varied tasks. The symbol for a NAND gate A
is the AND symbol followed by the NOT
symbol or in Boolean algebra notation as AB.
c
A B C
In logic terms, the output from a NAND gate is
0 0 1
true if all inputs are not true. This logical 0 1 1
explanation holds true regardless of the 1 0 1
number of inputs into the NAND gate. Most
NAND gates contain 2,3 or 4 inputs.
~D-c 1 1 0
Fig 10.38
NAND gates are perhaps the most useful logic NAND gate. All other logic gates can
be simulated using NAND gates.
gate. It is possible to simulate all other logic
gates using combinations of NAND gates. As a
result, microprocessors could be designed
using NAND gates exclusively. Although this
is possible, it is not the most efficient method. c A B C
In the next section, we will attempt to create 0 0 1
0 1 0
each of the other logic gates using only NAND 1 0 0
gates. 1 1 0
NOR gate ~D-c
Fig 10.39
NOR means NOT OR, a NOR gate is NOR gate. Both A and B must
equivalent to an OR gate followed by a NOT be 0 for the light to burn.
gate. In Boolean algebra notation NOR is
written as A + B . Fig 10.39 shows a possible
circuit together with the truth table and symbol
for the NOR gate. All inputs must be false for c A B C
the output to be true. 0 0 0
0 1 1
XORgate 1 0 1
1 1 0
XOR is short for exclusive OR. This means
that precisely one input must be 1 (true) for the ~jD-c
Fig 10.40
output to be 1 (true). A XOR B is written in
XOR gate. Exactly one input must
Boolean algebra notation as A EB B. In some be true for the output to be true.
literature, XOR is called EOR; the terms are
interchangeable. In this text, we will use the
termXOR.

GROUP TASK Discussion

Often staircases have a switch to turn on and off the light at the bottom
of the stairs and another switch to turn the same light off and on at the
top of the stairs. Which of the above circuits could be used to wire this
light. Explain your answer.

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 The interrelationship between software and hardware 449

CIRCUIT DESIGN
Combinations of the above logic gates can be used to solve new problems. Problems
in circuit design are normally presented in the form of inputs and required outputs,
essentially a truth table. Computer Aided Design software is available to assist in the
design of circuits, in fact it would be impossible for today's microprocessors to have
been created without the use of computer aided circuit design tools!
The process of developing new circuit designs is cyclical in nature. As is the case with
software solutions, there are often many ways to solve the same problem. The aim is
to find the most efficient and elegant solution. This often involves a process of
evolutionary refmement. In this course, we need only consider the logical level of
electronic circuit design. Electrical engineers need to consider many other factors
when solving real world problems.

Consider the following:

Imagine you are designing a circuit for an electronics

project you are working on at home. You visit your
local electronics store and find that they only have
integrated circuits (ICs) containing NAND gates. Fig
Input lA 1.
10.41 shows the pin assignments for one of the
available chips. These chips contain 4 NAND gates
e.g. the result of inputs at pin lA and IB is output at Output lC

pin lC. Input2A

For your project you require AND, OR, NOT, NOR,

XOR and NAND gates. How can you simulate each
of these gates using only NAND integrated circuits?
NOT gate Fig 10.41
74HC series CMOS NAND integrated
Examining the truth table for NAND indicates that
circuit. Contains 4 NAND gates.
when both input A and B are the same i.e. both as or
both Is we effectively have a NOT gate. Logically
we perform (A NAND A). Therefore, if we connect I n P u t - D - Output
input A and B together to form a single input the result
Fig 10.42
is a simulated NOT gate e.g. connect pins 1 and 2 on
NOT gate produced
our IC. Fig 10.42 shows a circuit diagram achieving using a NAND gate.
this purpose.
AND gate InPutAD-O-
Output
Input B
The truth table for a NAND gate is the opposite of that
for an AND gate. Therefore, if we reverse a NAND
gate we should arrive back at an AND result. In
essence we are performing NOT(A NAND B) which is
accomplished using a NAND gate followed by a NOT
gate. Using our Ie we could connect pins 3, 4 and 5
together, our inputs would then be at pins 1 and 2 with
our AND result output at pin 6. Fig 10.43 shows a
circuit design together with the possible connections
required using our IC. Fig 10.43
AND gate produced
using 2 NAND gates.

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450 Chapter 10

OR gate
This gate requires a little more thought. Let us A B NAND OR
examine the truth tables for both the NAND and 0 0 1 0
OR gates side by side (see Fig 10.44). Inputs of 01 0 1 1 1
and 10 result in the same outputs of 1 from both 1 0 1 1
1 1 0 1
NAND and OR gates, however the outputs from
00 and 11 are reversed. If we can invert the inputs Fig 10.44
Truth table for NAND
before they reach the NAND gate, we may get the
and OR side-by-side.
result we desire.
In logical terms we perform (NOT(A)) NAND Input A
(NOT(B)). As we don't have any NOT gates we Output
substitute each NOT for our NAND equivalent, InputB
hence our logical statement becomes (A NAND
A) NAND (B NAND B). We require three NAND
gates to produce a single OR gate. Fig 10.45
shows the circuit diagram and pin connections
using our NAND IC.
XORgate
This gate is rather more difficult. Let us first
examine the truth table for the XOR gate, the
outputs are 0110. Similar in many ways to an OR
gate except 1 and 1 results in an output of 0 rather Hg 10.45
than 1. If we consider the last sentence and OR gate produced using 3 NAND gates.
attempt to write it as a logical statement we get
something like: A or B but not A and B. This can Input A
be written as (A OR B) AND NOT(A AND B). Input B _--+-1
Output
Now NOT(A AND B) is the opposite of an AND
gate, which fortunately is a NAND gate; our
statement becomes (A OR B) AND (A NAND B). Fig 10.46
XOR gate produced using
Fig 10.46 shows our progress as a circuit diagram.
3 different gates.
We could replace the OR and AND gate in this
solution with the NAND representations we developed above, this results in the
circuit design shown in Fig 10.47. Unfortunately, this solution requires 6 NAND
gates and each of our ICs
contains only 4 NAND gates. It InputA
would be convenient and more
Output
efficient to find a solution using Input B
just 4 NAND gates.
Boolean algebra provides a Fig 10.47
mathematical technique for XOR gate produced using 6 NAND gates.
simplifying and/or rearranging
circuit designs such as this. The following pages describe the basics of Boolean
algebra and how it can be used to optimise the design of circuits.

GROUP TASK Research

Research using the internet (or otherwise) the different chips available in
the 74xxxx series. Determine the function of each pin for each of the
chips you find.

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 The interrelationship between software and hardware 451

BOOLEAN ALGEBRA
Boolean algebra was fIrst developed by the English
mathematician George Boole around 1850. Coincidentally,
this was about the same time Charles Babbage was working
on his Analytical Engine, the forefather of today's
computers. Boolean algebra is used to describe logical
propositions where the outcome is either true or false. The
application of Boolean algebra to circuit design has enabled
the design of today's effIcient circuits containing many
millions of logic gates.
Fig 10.48
In Boolean algebra notation, variables can hold values of 0 George Boole (1815-64)
(false) or 1 (true). There are three operations NOT, OR and
AND. NOT A is denoted as A, A OR B is denoted A+B and A AND B is denoted
A· B or just AB. A further notation has been added for XOR, A XOR B is denoted
AE!3B.
Boole, along with one of his contemporaries, Augustus DeMorgan developed and
proved the following laws of Boolean algebra:
la. A+B=B+A 4a. A+A=A 7a. A +A=l
lb. AB=BA 4b. AA=A 7b. AA=O
2a. (A+B)+C=A+(B+C) 5a. O+A=A 8a. A+ A B=A+B
2b. (AB)C=A(BC) 5b. OA=O 8b. A( A +B)=AB
3a. A(B+C)=AB+AC 6a. I+A=l DeMorgan's Theorem
3b. A+(BC)=(A+B)(A+C) 6b. lA=A -- --
9a. (A+B)=A B
- - -
9b. (AB)=A + B
Let us use these laws to help simplify our XOR problem into a series of NAND gates.
At this stage it is not necessary to be able to reproduce such working rather it is
suffIcient to be able to follow each step in the working based on the above laws of
Boolean algebra. Initially we described XOR as A OR B AND NOT(A AND B):
A E!3 B = (A + B)AB (definition ofXOR gate)
= AB(A+B) (usinglaw1b.) InputApgo
output
= ABA + ABB (using law 3a.) Input B
- -
= AAB + BAB (using law 1b.)
Fig 10.49
= AAB + BAB (applying not twice). XOR gate using only 4 NAND gates.

= AAB BAB (using law 9a.) Input A ~_IT1~'J"'-n41

Input B --+l~
Implementing this Boolean expression as a
circuit diagram requires 4 NAND logic gates
1----1--1-- Output
(see Fig 10.49). As a result, we are able to
use a single IC; remember each of our ICs
contains 4 NAND gates. Fig 10.50 shows the
wiring for our IC.

Fig 10.50
XOR gate created using an Ie
containing 4 NAND gates.

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 452 Chapter 10

Let us examine the above laws of Boolean algebra in more detail. The first thing we
notice is that many of the laws are the same as regular algebra. In particular laws 1a,
1b, 2a, 2b, 3a, 5a, 5b and 6b. This leaves the following set of new laws to learn:
3b. A+(B C)=(A+B) (A+C)
4a. A+A=A
4b. AA=A
6a. l+A=l
7a. A+A=l
7b. AA=O
8a. A+AB=A+B
8b. A(A+B)=AB
- - --
9a. (A+B)=Ay
9b. (AB)=A+B
Let us briefly run through each of these laws commencing with the simpler laws first.
• 4a. A+A=A. In words this law means "A or A will equal A A A A+A
regardless of the value of A". Fig 10.51 shows the truth table 0 0 0
which confirms that when A=O then A+A also equals 0, and 1 1 1
when A is 1 then A+A also equals 1 based on our earlier OR Fig 10.51
gate description. In practice this rule is often extended in a Law 4a truth table
variety of ways such as, AB + AB = AB, A+A+A+A = A and
even in reverse when an extra term is needed such as replacing AB with AB + AB
within an expression.
A A AA
• 4b. AA=A. This law means "A and A always equals A 0 0 0
regardless of the value of A". The truth table in Fig 10.52 1 1 1
confirms this to be true based on our previous AND gate Fig 10.52
definition and truth table. Can also be extended so it is also true Law 4b truth table
to say that AAAAA = A or in combination with rule 1b it is true
1 A l+A
that ABBAABAB = AAAABBBB = AB.
1 0 1
• 6a. l+A=1. This means when 1 is 'OR'ed with anything the 1 1 1
result is always 1. This is a very useful rule as it often allows a Fig 10.53
whole string of complex terms to be reduced to 1. For example, Law 6a truth table
the expression AB+BD+AD+l = (AB+BD+AD)+l = 1.
A A A+A AA
• 7a. A +A=1. If two opposite Boolean values are 'OR'ed 0 1 1 0
the result is always 1 (true). 1 0 1 0
• 7b. A A=O. If two opposite Boolean values are Fig 10.54
'AND' ed the result is always 0 (false). Law 7a and 7b truth table

• 3b. A+(BC)=(A+B)(A+C). This is a very useful law and it is not immediately

obvious that it is true. The following mathematical proof shows the rule to be true
however a truth table could also be used to confirm the law.
RHS = (A+B)(A+C)
= AA+AC+BA+BC (expanding using law 3a)
- A+AC+AB+BC (as AA=A law4b)
- A(1 +C+B)+BC (factorising using law 3a)
- A(l)+BC (using law 6a)
- A+BC (as lA=A law 6b)
- LHS

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 The interrelationship between software and hardware 453

Il'l 8a. A+ A B=A+B. The fonowing mathematical proof and the truth table in Fig
10.55 shows the law to be true.
RHS = A+B
A+B(l) (as 1B=B law 6b) A B A AB A+AB A+B
0 0 1 0 0 0
A+B(A+ A) (using law 7a) 0 1 1 1 1 1
A+AB+ A B (expanding using law 3a) 1 0 0 0 1 1
1 1 0 0 1 1
A(l +B)+ A B (factoring using law 3a)
Fig 10.55
A(l)+ A B (using law 6a) Law 8a truth table
A+ A B (using law 6b)
LHS
* 8b. A( A +B)=AB. The following mathematical proof and the truth table in Fig
10.56 shows the law to be true. - -
A B A A+B A(A+B) AB
LHS = A(A +B) 0 0 1 1 0 0
AA +AB (expanding using law 3a) 0 1 1 1 0 0
O+AB (using law 7b) 1 0 0 0 0 0
1 1 0 1 1 1
AB (using law 5a)
Fig 10.56
RHS
Law 8b truth table
• 9a. (A + B )= A Band 9b. (AB)= A + B . These are DeMorgan' s theorems and are
the basis for the "Sum of Products" and "Products of Sums" techniques we
examine in the next section. In words theorem 9a means the reverse of 'OR'ing is
the same as reversing each value and then 'AND'ing them. And 9b means the
reverse of 'AND'ing is reversing then 'OR'ing. These theorems are useful when
you wish to convert OR gates to AND gates or vice versa. The following truth
tables in Fig 10.57 shows both theorems to be true.
A B A B A+B AB AB A+B
0 0 1 1 1 1 1 1
0 1 1 0 0 0 1 1
1 0 0 1 0 0 1 1
1 1 0 0 0 0 0 0
Fig 10.57
DeMorgan's Theorem 9a and 9b truth tables

GROUP TASK Activity

We neglected to construct the truth table to confirm law 3b.
Construct a suitable truth table.

GROUP TASK Activity

Each of the Boolean algebra laws can also be viewed as equivalent
circuits. In law 8a the circuit A +B is logically the same as the circuit
A + A B. Draw both circuit diagrams for both these circuits.

GROUP TASK Research

Boolean algebra is not just used when designing circuits it has a wide
variety of other applications. Research and describe some of these other
applications of Boolean algebra.

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454 Chapter 10

CONVERSION BETWEEN TRUTH TABLES, BOOLEAN EXPRESSIONS

AND CIRCUIT DIAGRAMS
Often problems present themselves in words which can readily be expressed as a truth
table. However to convert such truth tables into a circuit design is often a difficult
task. However if we can convert the truth table to an equivalent Boolean expression
then we can not only simplify the expression using Boolean algebra but it is also a
much simpler task to construct our circuit diagram from the final Boolean expression.
There are two strategies for deriving a Boolean equation from any truth table:
• Sum of Products (SoP) which uses all the truth table rows with a 1 output.
• Product of Sums (PoS) which uses all the truth table rows with a 0 output BUT
with each input reversed.
Usually the best strategy to use is the one with the least number of rows. So if there
are less Is than Os in the output column then use SoP and if there are less Os than Is
then use PoS.
A trivial example to introduce the SoP and PoS strategies. Say we
A B X
wish to develop an efficient circuit to implement the truth table in 0 0 1
Fig 10.58. In this case there are two inputs, namely A and B and a 0 1 1
single output X. If we inspect the truth table we can probably see 1 0 0
that that X is always equal to the opposite of A. In Boolean 1 1 0
algebra this is written X= A. This is the solution we are hoping to Fig 10.58
determine using SoP and also PoS. Remember this is a trivial Sample truth table
example; for more difficult cases it will not be possible to see the
solution by simply inspecting the truth table.
Check the output column to see whether there are less Is or less Os. In this case the
output or X column contains an equal number of Is and Os so it doesn't really matter
whether we choose SoP or PoS as our strategy (although SoP is often simpler in such
cases).
Using Sum of Products (SoP) we use only the rows with an output of 1 - the first two
rows in this case. The first row is A=0 and B=O which written as a product gives us
-- -
A B . The second row is A=O and B= 1 so our product from this row is A B. The sum
of these products is therefore A B + A B. So are final Boolean equation is
-- -
X = A B + A B which we can simplify using Boolean algebra as follows:
X=AB+AB
= A(B+B)
= A(I)
A
Now let us try using Products, of Sums (poS). This time we only use the rows with an
output of 0 which is the last two rows in Fig 10.58. The third row is A= 1 and B=O but
we need to reverse these values to form our first sum. Therefore the sum from row
three of the truth table is A +B. The fourth row is A=1 and B=1. Again reverse the
values and add to form the sum A + B. The product of these sums is therefore
- -- - --
(A +B)(A + B) and the final Boolean equation is X=(A +B)(A + B). Which using
Boolean algebra simplifies to X= A as expected. Note that in this trivial example the
input B is not required at all and the circuit diagram is simply a single NOT gate.

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 The interrelationship between software and hardware 455

GROUP TASK Activity

Use Boolean algebra to show that the equation X=(A +B)(A + B) does
indeed simplify down to X = A as expected.

- HSC style questions:

Question 1.
A student has designed the following two circuits.
Circuit 1. Circuit 2.

A --.,.--1 A
x
B
B x

(a) Complete truth tables to prove both the above circuits produce the same output.
Include each letter on the circuits as a column in the truth tables.
(b) Design a simpler circuit that produces the same output as the above circuits.
Question 2.
A B C Output
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Create a circuit diagram based on the above truth table.
Question 3.
The following circuit uses six NAND gates.
A
B
x
C-----l

(a) Construct a truth table for the above circuit.

(b) Design a new circuit using only AND, OR and/or NOT gates that efficiently
produces the same set of outputs.

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 456 Chapter 10

Suggested solutions
Question 1.
(a) Circuit 1. Circuit 2.
A B C D X A B E F G X
0 0 1 0 1 0 0 1 1 1 1
0 1 1 0 1 0 1 1 0 0 1
1 0 0 0 0 1 0 0 1 0 0
1 1 0 1 1 1 1 0 0 0 1

The X columns are the same therefore both circuits are logically the same as
they output the same values for the equivalent inputs.
(b) Using Boolean algebra and PoS (Product of Sums) with the 3rd line of the truth
table we get X = A + B. This circuit requires just 2 logic gates and is drawn as

Question 2.
As there are less rows with an output of 1 we will use SoP (Sum of Products) with
these three rows.
Output= ABC + AB C + ABC
-- -
C(A B +AB +AB)
-- -
C(A B +A(B + B))
C (A B + A(l»)
C(AB+A)
C (B + A)
Which is equivalent to the following circuit diagram.
A ----,

B--V~X
C ---------'-

Question 3.
-
(a) A B C AB X
0 0 0 1 1
0 0 1 1 0
0 1 0 1 1
0 1 1 1 0
1 0 0 1 1
1 0 1 1 0
1 1 0 0 1
1 1 1 0 1

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 The interrelationship between software and hardware 457

(b) As there are less rows with a 0 output we use PoS (Product of Sums). the rows
have inputs of 001, 011 and 101 which we reverse to fonn our PoS equation.

x = (A+B+C)(A+B+C) (A+B+C)
- - - - -
(A+B+C) (A+ B +C) (A +B+C)
(A+B+C) (O+AB+AC + A B +0+ B C + A C +BC +C)
- - -- -- -- --
(A+B+C) (AB+AC+A B+B C+A C+BC+C)
(A+B+C)(AB+A B+AC+B C+A C+BC+C)
- -- - - -
(A+B+C) (AB+ A B +C (A + B + A +B+l))
- -- -
(A+B+C )(AB+A B +C)
AAB+AA B+AC+BAB+BA B+BC+CAB+C A B+C C
AB+OB+AC+AB+OA+BC+CAB+C A B+C
- - - ----
AB+AB+AC+BC+CAB+C A B+C
- --
AB+C(A+B+AB+A B+l)
AB+C
Which is equivalent to the following circuit design.

Notes

~ In question 1 (a) the C, D and the E, G columns are required for full marks. As
the question indicates the outputs will be the same then these extra inputs are what
shows the processing performed within the circuit.
411 The 6 NAND circuit diagram in question 3 is not as complex as it first looks. A
NAND gate with a single input is logically a NOT gate. In this circuit there are two
places where 2 of these NOT gates follow each other which means they cancel
each other out and can be ignored. This greatly reduces the work to be done
constructing the truth table in part (a).
Oil Question 3 (b) is definitely a difficult problem to solve from the truth table using
Boolean algebra alone. It may have been simpler to attempt to find a solution by
inspecting the truth table. Looking at the C and X columns we can see that X is
pretty much the opposite of C. The only exception is the last row where A, Band C
are 1. Using this observation one could conceivably determine the answer X=
AB+ C directly.
@ Another alternative for question 3 (b) is to write the Boolean equation based on the
original 6 NAND circuit diagram and then simplifY" using Boolean algoebra.

x = ABC
ABC Removing the tvvo sets of double NOTs
AB + C Using 9b (DeMorgan's theorem)
«I To simplifY" writing Boolean expressions using word processors it is common in
some references to use an apostrophe as the symbol for NOT. That is, A' is the
- -- -
same as A, (A+B), is the same as A + Band (AB)' is the same as AB.

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458 Chapter 10

GROUP TASK Activity

Use SoP to answer questions 1 (b) and 3(b) above. And use PoS to answer
question 2. Check you get the same answers as above. Comment on the
relative difficulty compared to the suggested solutions above.

GROUP TASK Activity

Draw a truth table with three input columns A,B, C and an output
column X. Write random values in the X column. Use both SoP and PoS
to help create a circuit diagram.

SPECIALITY CIRCUITS
There are a number of circuits that are in such common usage they are available
packaged within ICs and are an integral part of modem CPUs. These circuits include
adders, flip-flops and shift registers. In this section, we examine the circuit designs
behind each of these specialty circuits.
Binary adders
Addition of binary digits is a crucial operation for most software products hence it
makes sense to provide standard circuits to carry out this task. Let us examine the
process of designing a circuit to perform 8 bit binary addition.
We commence by considering the truth table required In Jut Output
for the addition of two bits (see Fig 10.59). Ifwe can A B Carry Sum
develop a circuit for two bit addition perhaps we can 0 0 0 0
reproduce our design to extend the solution to 8 bits. 0 1 0 1
1 0 0 1
The carry column in the truth table is identical to an 1 1 1 0
AND gate truth table and the sum column is identical
Fig 10.59
to the XOR truth table. Our circuit design will Truth table for the addition of two bits.
therefore require an AND and an XOR gate. Using
Boolean algebra, Sum= A EB B and Carry = AB. The completed
circuit is shown in Fig 10.60. ~~D-sum
This circuit is great if we just wish to add two bits, however we
wish to extend our addition circuit to add 8 bits. There is a
problem with this circuit, as it does not take account of possible
Lb-carry
Fig 10.60
carries from the previous addition. In fact, this circuit does only Binary halfadder
halfthe job and is therefore called a 'half adder'.

GROUP TASK Activity

There are a number of methods of constructing half adder circuits. Can
you come up with two unique designs that are different to that shown in
Fig 10.60.

GROUP TASK Discussion

It is not necessary for microprocessors to contain subtraction circuitry.
Why do you think this is the case? Discuss.

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 The interrelationship between software and hardware 459

Let us now design a circuit that takes account of a previous carry. This circuit will
need 3 inputs; A, B and Carry In, together with outputs for the Sum and Carry Out. As
there are three inputs to this circuit, our truth table Input Ou:put
will require 23=8 rows (see Fig 10.61). The binary Carry Carry
A B Sum
addition of the inputs results in the outputs shown In Out
in the table. 0 0 0 0 0
0 0 1 0 1
Examining this truth table seems at first glance, to 0 1 0 0 1
indicate that the Carry Out behaves like an AND 0 1 1 1 0
gate when Carry In is 0 and like an OR gate when 1 0 0 0 1
the Carry In is 1. Similarly, the Sum behaves like 1 0 1 1 0
an XOR gate and a NOT(XOR) gate. On further 1 1 0 1 0
1 1 1 1 1
examination, we find that the sum can be obtained
by performing Carry In XOR (A XOR B) and the Fig 10.61
Carry Out is 1 if two or three of the inputs are 1s. Truth table for the addition of two bits
with carry in and carry out.
Comparing these observations with
the half adder circuit indicates we
can use two half adders to create a C¥1Y In -r-----.;.-;.--1~
A
full adder circuit. If either of the
B
half adders produces a carry then
there needs to be an output carry. Carry Out
As a result Carry Out is the result of
an OR gate between the carry Fig 10.62
outputs from the two half adders. Aftll adder combines two halfadders.
Fig 10.62 shows a full adder created
in this way. :'-j~p~t;-': r~tp~i~'1
i Carry : , - - - - - , ! sum :
We now have a circuit that successfully adds two binary Bit 0
{ 1 A;
digits allowing for a carry from a previous addition and .! B =."---.......--;J
sending a carry to the next addition. How can we use : Carry IT' ;:==:::;=t Sum
this circuit to add 8 bits? We need merely to daisy chain
Bitl { !; A
B
these full adders together. The Carry Out from one full : Carry CE==~ Sum
adder becoming the Carry In for the next. Rather than Bit 2 { : A
redraw all the detail of each full adder we can draw it as : B :;'1...--....I:]

a black box with just inputs and outputs shown. Fig

10.63 shows the final circuit design for adding two 8 bit
Bit3{i C~ ;
Sum

i B ;;-,- - - - ' ' T ]

numbers. The first number is input into the circuit via
the eight A inputs and the second via the eight B inputs. Bit4{1 C~ ;
Sum

The result is obtained from the eight Sum outputs. : B::r:=: :=jJ
i Carry 0:::;:::: Sum
{
Bit 5 : A!
GROUP TASK Activity : B :;'1...-_-'
Draw up a truth table, including intermediate
Sum
steps for the full adder shown in Fig 10.62.
Ensure the circuit works as intended.

GROUP TASK Discussion

How could the 8 bit adder in Fig 10.63 be Fig 10.63
used to create a 16 bit or 32 bit adder? What An 8 bit adder created using
is the significance of the final carry? 8 full adder circuits.

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 460 Chapter 10

Software Design and Development -The HSC Course

 The interrelationship between software and hardware 461

11. Simplify each of the following Boolean eXlllresisIortS'

f _~""_

(a) AS +AP +.;fB

(b)

12.

Software Design and Development - The HSC Course

 462 Chapter 10

Flip-flops as memory stores

Flip-flops are bistable circuits used to
store binary digits. Bistable means the Bistable
circuit is able to maintain or remember A stable device is able to hold
two different states, representing the or maintain a particular state. A
binary digits zero and one. Flip-flops are bistable device can maintain
the basis of most temporary memory two possible states.
within computers; this includes registers
within the CPU and some types of RAM chips.
There are various designs of flip-flop, each with its own advantages and
disadvantages for particular applications. All flip-flops have three basic components
included within their design, one or more latch components, a clocking component
and an edge trigger component. The latch components are the circuits that actually
store the data, the remaining two components are designed to control the timing and
ensure the integrity of the flip-flop.
Let us consider the design of a typical flip-flop by developing each of these three
components:
Latch component
A latch is a circuit that is able to store a binary digit. In the same way that a latch is
used to lock a gate, a latch circuit is used to lock a binary digit within a circuit. For a
°
particular state, either or 1, to be maintained within a circuit requires feedback.
Feedback is provided by connecting the outputs of two logic gates to each other's
inputs.
A simple latch could be constructed using two not gates or
inverters; Fig 10.64 depicts such a circuit. This circuit is able
to maintain two states. The first state occurs when Q is L If
A~:
this occurs then the feedback line to the bottom inverter B~Q
causes Q to be 0. As a consequence, the feedback line to the Fig 10,64
top inverter will cause Q to retain a value of 1, and so on. A simple latch constructed
The second state occurs when Q is 0, in this case Q will using two inverters.
maintain a value of zero and Q a value of 1. It is traditional
to name the outputs from latches and flip-flops Q and Q. Q
R
should always be the opposite of Q. Q
The problem with this NOT based latch is that unpredictable
results occur if the inputs are altered. To correct this problem
we can use one of the two input logic gates. It turns out that Q
S
either NOR or NAND gates are the best solution. The inputs
s
to these latches are named Rand S, meaning reset and set, as Q
a result these latches are named RS NOR and RS NAND
latches (see Fig 10.65). Some references refer to these
circuits as flip-flops, this is not strictly correct as flip-flops Q
R
require further circuitry to control timing and edge Fig 10,65
triggering. RS-NOR latch and
RS-NAND latch circuits.

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 The interrelationship between software and hardware 463

Let us examine the operation ofRS latches in more detail. Firstly, the normal holding
state for both R and Sis o. To alter the latch to store a 1 requires a 1 to be sent to the
set (S) input, similarly a 1 at the reset (R) input will store a 0 in the latch. Notice that
our RS-NAND latch circuit has inverted inputs,
Input Output
when working with this RS latch it is necessary to
invert the Rand S values before calculating the S R Q Q
outputs. Both the RS-NOR and RS-NAND latches -
0 0 LastQ Last Q Hold
have the same resultant truth table (see Fig 10.66).
0 I 0 I Reset
There are still problems with these latches. The first
being how do we control when a latch is allowed to I 0 I 0 Set
change state? We need to control this to allow
I I X X Illegal
synchronisation of multiple latches. This problem is
solved by adding a clock component to our circuit. Fig 10.66
The next section describes this process. Truth table for an RS latch.

GROUP TASK Discussion

Work through the operation of each of the RS latches. Ensure you
understand how each of these latches produces the truth table shown in
Fig 10.66. Discuss your fIndings.

Clocking component
Let us work with our RS-NAND latch, although we
could equally have worked with the RS-NOR latch.
When a number of latches are connected together, it is
vital that we can force all latches to change (or not Q
change) at the same time. By connecting a clock to our
circuit, we can achieve this aim. Essentially, a clock is
an extra input that changes state from 0 to 1 then back to Q
o when we wish to make changes to the attached
latches. When the clock input is at 1 then the latch is Fig 10.67
permitted to change state. When the clock input is at 0 Clocked RS-NAND latch circuit.
no change to the latches can occur.
The advantage of having chosen the RS- Input Output
NAND latch rather than the RS-NOR latch is S R CLK Q Q
that the clock circuitry reverses the inputs, -
0 0 1 LastQ Last Q Hold
hence we are now working with a hold state
of 00 (the original RS-NAND latch required 0 I 1 0 1 Reset
inverted inputs, see Fig 10.65). This is
I 0 1 I 0 Set
preferable as 0 really means low or no
voltage, whereas 1 means high voltage. 1 I 1 X X Illegal

Two problems remain, what happens if the S -

X X 0 LastQ Last Q Hold
or R inputs are both 1 when the clock (CLK)
is 1. Also it is possible for Sand R to change Fig 10.68
multiple times whilst CLK is 1. Truth table for a Clocked RS latch.

GROUP TASK Activity

Draw up a complete 8 row truth table for the Clocked RS Latch in Fig
10.67. Complete this table to ensure the correct operation of the circuit.
Make sure you understand this circuit before proceeding.

Software Design and Development - The HSC Course

 464 Chapter 10

Illegal inputs of 11
Let us examine the first problem of illegal inputs of 11. If we examine the truth table
for the clocked RS latch, we see that Sand R values that alter the value stored in the
latch are the inverse of each other. We can insert a not gate between the S input and
the R input and then dispense with the R input
altogether. This is only possible because of the D---I
inclusion of the clock circuitry. The hold Q
conditions now exist only when the clock is O. This CLK-+----I
revised latch design is known as a data latch, D-
type latch or merely a D latch. The D or data input Q
is now the same as the value stored within the latch
and output at Q. Often this circuit is called a D- Fig 10.69
type flip-flop, however this is not strictly correct, D latch circuit. The input at D
is stored and output at Q.
as it has no edge trigger component.
Edge trigger component
An edge trigger circuit is used to ensure the flip-flop only Positive Negative
edge edge
changes state once for each tick (1) of the clock input. The
clock changes state from a 0 to 1 and back to a 0, the aim is to \ I
perform the change of state within the flip-flop as the clock SLrLJLJL
o 1 0 1 0 1 0 1 0
changes state. Each change of state is called an edge, in other Clock ticks )
words the flip-flop is triggered by either an up or positive
Fig 10.70
edge or a down or negative edge. An edge is the point
Edge trigger components are used on all types of flip-flops. where the signal changes.
For this discussion, we will consider the addition of edge
trigger circuits to our D latch developed above. It is possible to design edge trigger
circuits that respond to either the positive or the negative edge of the clock signal. For
our discussion, we will examine a negative edge triggered D-type flip-flop.

._._.-.-._.-.-
,
Q

Q
Datan
Input
Clock
Input
D

-Q
Output

Inverted
CLK -~------I )0-----' Output
:... _. _. _. _._. _._. _. _. _. _._. _. _. _. _._. _. -. -,'
Fig 10.71 Fig 10.72
D-type flip-flop with negative edge trigger or more simply aD flip-flop. Symbol for a D flip-flop.

Edge triggered flip-flops consist of two latch circuits, a master and a slave.
(Sometimes these flip-flops' are called master-slave flip-flops). The inverter
connecting the clock inputs is the key to the edge trigger function. If the clock input is
o then data inputs at D will have no effect on the master latch. Consequently, there
will be no change in the input into the slave latch, hence the stored value and output
remains unchanged. This is precisely what is required when the clock sends a O.

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 The interrelationship between software and hardware 465

What about when a 1 is sent from the clock? In this case, the data input D into the
master latch becomes active, as a result the value stored in the master latch can be
altered to reflect the input. Whilst this is happening an inverted clock value of 0 has
entered the slave latch, hence the slave latch is disabled and does not accept the input
from the master latch. When the clock falls again to a 0 (the negative edge), the
master latch is again disabled, however the inverted clock input is now 1 so the slave
latch is active. Therefore, the output from the master latch can enter the slave latch
and alter its contents. The result being that both latches are now storing the new data
value D. As with the previous latch designs this value is output at Q.

GROUP TASK Investigation

Edge triggering is not a simple concept to grasp. There are various
software simulations available both on the web and as part of software
packages. Use one of these packages to investigate this concept.

GROUP TASK Discussion

The explanation above is relevant to negative edge triggered flip-flops.
Positive edge triggering can be accomplished by adding another inverter
at the initial clock input. Explain how this system would operate.

Other flipjlop designs

The D-type flip-flop is only one type of flip-flop. The RS flip-
flop is a similar design however it does not combine the reset
and set inputs into one, hence the illegal 11 input is possible.
Set
Clock
Input
OQ -Q
Output

Inverted
The JK flip-flop is a modification of the RS Flip-flop that uses R
ese!
R Output
a different system to overcome the illegal 11 problem.

DQ
Essentially, the JK flip-flop uses feedback from the outputs to RS Flip-flop
disable the input not being used.
Set Output
Other modified flip-flops have an input that causes the value Clock
stored to be returned to O. This is useful when a large number Input
- Inverted
of flip-flops need to be cleared simultaneously. In the next Reset K Q Output
section, we look at shift registers. The clear function is
JK Flip-flop
particularly useful when flip-flops are to be used as part of
registers within the cpu. Data
D Q Output
Input
Clock
Input
Inverted
GROUP TASK Investigation CLR Q Output

Collect catalogues from various electronics stores Clear

or access them on the web. Make a list of all the
D Flip-flop with clear
different types of flip-flop ICs available at these
stores. If possible, obtain the pin assignments and Fig 10.73
draw a diagram similar to the NAND IC diagram Symbols for popular
flip-flops
in Fig 10.41.

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 466 Chapter 10

Shift registers
Shift registers are used to store binary data. Registers are nonnally designed to store
data in multiples of 4 bits. All shift registers allow for data to be moved into or out of
the register. Designs are available to shift data left and/or right; these functions are
necessary to perfonn binary mUltiplication and division. A shift of one bit to the right
divides the contents by two; a shift of one bit to the left multiplies by two.
Essentially shift registers are groups of flip-flops connected together in a chain. The
whole group is controlled by a common clock. This means that data can be shifted
simultaneously throughout the register. If a clear function were present on the
component flip-flops, this would also be controlled by a common circuit.
There are a number of ways of connecting flip-flops to provide for particular
requirements. Some common arrangements include: Data
Input
D Q Output
• Serial in - serial out
Clock
• Serial in - parallel out Input
Inverted
• Parallel in - serial out CLR Q Output

• Parallel in - parallel out Clear

• Bi-directional Fig 10.74
• Counters D Flip-flop with clear

For our purposes, we will examine the Serial in - serial out, Parallel in - parallel out
and the Bi-directional shift register. In each case, we will use D flip-flops with clear
inputs, however similar designs could be created using the other common flip-flop
designs. For our discussion we will create four bit register designs but these designs
could easily be extended to any number of bits.
Serial in - serial out shift register
Flip-flop 3 Flip-flop 2 Flip-flop 1 Flip-flop 0
This register is populated Data Data
one bit at a time. To load Input
- D QI - - D QI-- D QI-- D Q I - - Output
4 bits requires 4 clock - t> -
,-- t> -
- t> -
- r> -
ticks. As a bit is input Q Q Q Q
CLR CLR CLR CLR
from the left all other bits I I I
are shifted to the right,
Clock
Clear 1 1 1 I
with the right hand bit Control
Fig 10.75
being lost out of the Serial in - serial out shift register
register.
To load the register with data requires activating Data Flip-flop
the clear control line. This is done by sending a Clock
Input 3 2 1 0
1; this sets all flip-flops to O. The input data is 0 1 0 0 0 0
then supplied to the data input line of flip-flop 3 1 1 0 0 0
one bit at a time. 1 bit enters the register for each 0 1
tick of the clock. A bit destined for the right 1 1 1 0 0
0 0
hand flip-flop (flip-flop 0) must travel through 1 0 1 I 0
all preceding flip-flops to reach its destination. 0 1
Fig 10. 76 is a desk check of this register I I 0 1 1
receiving the bit pattern 1011.
Fig 10.76
Desk check of the serial in - serial out
shift register using the data 1011.

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 The interrelationship between software and hardware 467

GROUP TASK Activity

Perform a desk check of the Serial in - serial out shift register. Assume
the register contains the data 1011 and that it needs to be shifted out of
the register and replaced by 0110.

Parallel in - parallel out shift register

This register receives and outputs data into and out of all its flip-flops simultaneously.
The same number of input data lines are required as the number of flip-flops within
the register, similarly for the data outputs. This is the normal structure for a storage
register that cannot perform any processing.
Once the clock sends aI, data Data Data Data Data
Input 3 Input 2 Input J Input 0
is stored in aU the flip-flops at
the same time. In other words, Flipjlop3 Flip-flop 2 Flip-flop 1 Flip-flop 0

one tick is required to fill the D Q D Q D Q D Q

register with new data. The
outputs from each flip-flop are > - t> - t> - t> -
available at all times. It is not CLR Q CLR Q CLR Q CLR Q
I I I
necessary to shift data out via
other flip-flops, as was the case
Clock
Clear 1 1 1 I
Control Data Data Data Data
with the serial out design. Output 3 Output 2 Output I Output 0

This register design is unable to Fig 10.77

alter the nature of its data as Parallel in - parallel out shift register
there is no link between the
data lines of each flip-flop. This makes the design suitable as a storage register rather
than a processing register. Because data can be clocked in and out of this register
during a single clock tick, it is particularly suitable where fast access to data is
required.

GROUP TASK Discussion

Describe the difference between serial and parallel transfer of data. Why
do you think parallel transfer of data is the preferred method within the
CPU? Explain.

GROUP TASK Activity

Study the two shift registers discussed above. Design a four bit shift
register that could be described as a Serial in - parallel out shift register.

GROUP TASK Discussion

Multiplexers are used to combine signals from multiple sources and send
them down a single line and vice versa. Do any of the following shift
registers perform this function? Explain your answers.
.. Serial in - serial out
'" Serial in - parallel out
.. Parallel in - serial out
" Parallel in - parallel out

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 468 Chapter 10

Bi-directional shift register

The above serial in - serial out register can only shift data to the right, each shift
effectively dividing the number by two, The Bi-directional shift register is able to
shift data in either direction to allow both multiplication and division to take place,
This register contains an extra control line (left/right control) used to indicate the
direction of shift If the control line is sent a 1 then the data is shifted one position to
the right, with the data input being placed into the left hand flip-flop, If the left/right
control is sent a 0 then the data is shift one position to the left, with the data input
being placed into the right hand flip-flop,
~ _ _ _ _ Left / Right
Control

Data
Q Output

CLR Q CLR Q CLR Q CLR Q

Clock---<e---+-----~-_+_----_*-__+-------'
Clear --4--------4-------l~---------l
Control
Data
Input-G>--------------------------------I
Fig 10,78
Bi-directional shift register,

The logic of this flip-flop is quite involved and requires intensive examination to
understand completely, Let us examine a left hand shift using this circuit. Firstly, the
left/right control is sent a 0, indicating a left shift This input is reversed by the
inverter on the second left/right control line, As a result, each set of 3 NAND gates,
controlling the inputs into each flip-flop, receives a 1 at the top NAND gate and a 0 at
their bottom NAND gate, Consider the bottom NAND gate preceding each flip-flop,
as it has received a 0 then its output must be a 1 regardless of the value in its other
input, effectively these gates have been disabled. The upper NAND gates, which
received a 1 from the left/right control, are enabled, A 1 from their other input will
result in a 0 output and a 0 results in a 1 output Following the source of the other
input to the upper NAND shows it comes from the output of the flip-flop to the right,
which is correct for a left hand shift The third NAND gate preceding each flip-flop
input effectively reverses the input back to its correct state for storage in the flip-flops,
Of course, all this can only occur ifthe clock has sent a 1 to each flip-flop, Notice that
the right hand flip-flop will gain its new data from the data input line,

GROUP TASK Discussion

The above paragraph describes a left shift of the above register, A right
shift occurs when the left-right control line sends a L Describe the
processing involved in a right shift,

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 The interrelationship between software and hardware 469

HSC style questions:

Question 1.
Consider the following binary half adder circuit:

A--+""""'D-
B ~>-+-I
Sum

Carry

(a) IdentifY the two logic gates used in the above half adder circuit.
(b) Construct a truth table for the above half adder circuit.
(c) Create a circuit for a full adder.
(d) Explain how a circuit to add two 8-bit binary numbers could be constructed.
Question 2.
Describe the essential feature of flip-flops that allows them to store binary digits.
Suggested solutions
Question 1.

(a) 0 is an AND gate and)D is the symbol for an XOR gate.

(b) A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
(c) Carry In - - - - - - / I------Sum
A
Carry Out
B

(d) When we add any 2 single bits from a number which has multiple bits, there can
be a carry which needs to be carried forward to be included in the addition of
the next 2 bits in the number. In effect three bits are input and added resulting in
2 bits being output.
This circuit requires that the carry from the previous addition of the lower order
bits in the two 8-bit numbers is carried forward into the addition of the next 2
equivalent bits. As there are 8 pairs of bits then 8 full adders must be connected
together - the carry out from each full adder connecting to the carry in of the
full adder for the next higher significant bits.
Question 2.
The latch component of the flip-flop. This component contains two gates with the
output of each linked back to one of the inputs of the other. This provides feedback to
the gates so that the latch is able to remain in a stable state. There are two possible
states representing the binary digits 0 and 1.

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 The interrelationship between software and hardware 471

PROGRAMMING OF :HARDWARE DEVICES

Computer systems require input from outside sources. This input may be acquired
from traditional input devices such as the keyboard, mouse or CD-ROM or it may
come from external sensors that can react to changes in the environment such as light,
temperature, flow, pressure or movement.
Similarly, output from the computer Sensor
system requires conversion into forms that Any device that converts input
are understandable by the output device. from the environment into a
Most computer systems include monitors, digital signal. This signal is
printers and sound output. Other systems interpreted by the software.
include actuators that cause some
mechanical action e.g. moving a robotic
arm or unlocking a door.
Actuator
Software developers must be able to send An output device that
and receive data to and from these input performs a mechanical action.
and output hardware devices. In this Actuators receive digital signals
section, we examine the data streams that from software.
are required for the control of hardware
devices by software.
Input and output data streams from and to sensor and other devices
The data stream received from input devices and sent to output devices include two
types of information; the· actual dat<.l together with information to ensure its correct
delivery. The format commences with header information fonowed by the data itself
and concluding with trailer information. Both the header and trailer information are
used to ensure the data is deliver(;;d correctly.
Manufacturers of hardware devices produce specifications detailing the precise nature
and format of the data streams sent to and from their products. Similarly, hardware
specifications detail the of the data required to control these devices. It is the
responsibility of the sotl:ware developer to interpret and create these data streams
correctly.

Consider an old(~r PS2 ball mouse:

Separate
sensor for
There are two dHJerenttyp.~§ .. ofsensor built each button
into a mouse; sensors to detect motion and
sensors to detecbthcstate of the huttons. A
typical mouse wiihtwo ortll~'c~buttons would Integrated
have a separatesel)~prt()r~.~~ll button together circuit
with sensorsfqr movement. Today the
movement §!ens()I'S arccssentialty small yet
complex digital camcr~s which J.ietect changes
in the image to~~~s~motion.Older designs
Y direction
used mechanicaI~:9tafing sensors in conjunction mechanical
with a rubber ball ti) detcctmovement in both sensor

X and Y directions· (seeP/l.f 10.79). We will

X direction
consider 0110 . . th~se,61der .. designs which mechanical
connect to thecmIlPu~erusil1ga PS2 serial port sensor
(rather than USB) $sthe da,tastream sent from Fig 10.79
the mouse simpierto understand. Underside of mouse showing input sensors.

---,._........_..._................................... ,......._ . . _----=---=-------:-------------

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 472 Chapter 10

Mouse buttons are simple switches; either they are up or down. The sensors for X and
Y direction detect and send a series of Is and Os to the mouse's Ie. The Ie converts
the signals from the switches and X and Y direction sensors into coded form, which is
sent to the computer via a PS2 serial port.

GROUP TASK Practical Activity

Remove the cover from an old mouse (not necessarily a ball mouse).
Identify each of the sensors within the mouse. Can you identify any of the
other components within the mouse?

On old IBM compatible computers, a PS2 port was used to

receive data from the mouse. The PS2 port was developed to 6 5
free up valuable serial ports prior to the widespread acceptance 4 3

of USB. PS2 ports receive synchronous data. This means the 2 1

rate of data transmission occurs in time with the clock signal,
one bit is sent from the mouse for each tick of the clock. Fig Pinna. Name
1 Data
10.80 shows the pin assignments for PS2 connectors; pin 1 is
2 Reserved
used for data and pin 5 for the clock signal. 3 Ground
Let us now examine the format and nature of the data stream 4 Power
sent from the mouse. When a mouse sends information, it sends 5 Clock
three consecutive data packets. These data packets contain 6 Reserved
information about the state of each button and the movement Fig 10.80
that has occurred in both X and Y direction since the last PS2 female connector
transmission. Different brands of mouse may use different and pin assignments.
formats or include additional data packets to Packet Bit number
allow the inclusion of added features. For No. 7 6 5 4 3 2 1 0
our discussion, we will examine the input 1 Yv Xv Yd Xd 1 0 BI Br
data stream from a standard two button PS2 2 X7 X6 X5 X4 X3 X2 Xl YO
mouse. 3 Y7 Y6 Y5 Y4 Y3 Y2 YI YO
Yv Overflow in Y direction.
Each packet of data is eleven bits in length Xv Overflow in X direction.
containing a start bit, eight data bits, an odd Y d Direction of movement in Y direction
parity bit and fmally a stop bit. As there are (1 means left, 0 means right).
three data packets, a total of 33 bits are Xd Direction of movement in X direction
(l means up, 0 means down).
required for each transmission. The format Bl Left button state (1 means down, 0 up).
of the data is shown in Fig 10.81. Br Right button state (1 means down, 0
Movement in each direction is sent using 8 up).
bits. Values in the range 0 to 255 are XO-X7 Number of bits moved in X direction
possible. If the mouse has been moved since last transmission.
YO-Y7 Number of bits moved in Y direction
exceptionally fast then an overflow can since last transmission.
occur in which case the appropriate
Fig 10.81
overflow bit is set to 1. Data format for a two button PS2 mouse.
Fig 10.82 shows the
Data packet 1 Data packet 2 Data packet 3
input stream from a r__--~A-_ _-.'\ r__--~A-_ _-.'\ r__--~A...._ _-.'\
typical transmission.
F or this mouse the
o001 01 01 0 01 0 00011 000 11 0 011 0011 0 10
start bits are always
Start
iI. Da:bits /
Odd
\
Stop
zeros and the stop bits bit parity bit bit Fig 10.82
are always ones. Data stream for a typical PS2 mouse transmission.

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 The interrelationship between software and hardware 473

GROUP TASK Discussion

Examine the example input data stream in Fig 10.82. What can you say
about the state of the mouse buttons? Describe the movement of the
mouse?

All data packets are made up of three distinct components; header information, data
and trailer information. The data will often contain control characters used to cause
some predefined action by the hardware e.g. moving a robotic arm or moving a printer
head to the left hand side. Let us consider each of these three components in detail.
Header information
The information preceding the data is known as the header. For communication with
hardware devices within the computer system or connected directly to one of its ports,
the header is often just a single start bit. This bit signals to the receiving device that a
new data packet is commencing.
Data characters
The actual data being sent. This is the stream of data that is used by the receiving
device. Often control characters are included within this data stream. For example, a
modem requires control sequences to activate its internal functions, such as
instructions to go off-hook or dial a number.
Trailer information
The information following the data is known as the trailer. Trailer information
includes error checking bits and stop bits. There are various error checking techniques
that can be used, often a simple parity bit is used. A stop bit is often used to indicate
the end of the data packet.
Processing of the data stream
Once a data stream has been received from a hardware device it will requrre
processing by the computer. The software used to perform this function must be able
to understand the precise format of the data stream. Control characters will need to be
isolated and acted upon and strings of data will need to be interpreted into forms that
can be used by the system. The processing required is dependant on the particular
hardware device.

Consider the following:

PABX systems are used to control the telephone systems

in large organizations with multiple lines and extensions.
In large hotels, the PABX is used for many
administrative functions. For example, housekeeping
staff are able to indicate when a room has been cleaned
Fig 10.83
using the telephone system, guests can activate do not fABXs are used to control the
disturb status, etc. The hotel's computerised property operation oftelephone systems.
management system (PMS) interfaces with the PABX.
Different PABX systems use different formats for messages. Software developers
need to create interfaces that are able to accept messages from all the commonly
available models of PABX. Let us examine the format of a typical data stream
between the PMS and a fictitious model PABX we'll call the PEC201O. The PEC2010
is connected to the PMS computer via a serial port.

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474 Chapter 10

The PEC20 lOuses the same general format for both STX
messages it sends to the PMS and messages it receives PABXmodel
from the PMS. Each message is comprised entirely of (2 char)
ASCII characters. The header commences with the STX PABX Version
or start of text character, which is followed by two Function code
characters indicating the model of the PABX, in this (2 char)
case, P2, and a single digit indicating the version; for Message length
hotel systems the version is always a 5. Hence the header (3 char)
for all messages within the hotel will be STX P25 which Data
Function sub-code
translates to the ASCII values 2805053.
Following the header information the data to be Data
processed commences. This data commences with a two
character function code, followed by three digits
Checksum
indicating the length of the message in characters, Trailer {
ETX
followed by a function sub-code; a total of six characters.
The message length is the length of the message Fig 10.84
General message format for
including the header but excluding the initial STX the PEC2010 PABX
character and final ETX character.
The trailer information for each message contains a 1 STX
byte checksum followed by the ETX or end of text character 2 P
3 2
which has an ASCII value of 3. After each message has been
sent, the receiver sends an ACK (acknowledge) if the 4 5
5 2
message was received correctly or a NAK (negative 6 4
acknowledge) if an error was detected. If a NAK is received 7 0
then the message is resent. 8 5
9 4
Let us now examine the format for a particular function:
10 4
Guests need to be charged for calls they make according to II
the length of the call and the destination of the call, these 12 Extension
13 number
messages are transmitted from the PABX to the PMS for 14
inclusion on the guest's account. This function is called the 15
'Call Detail' function and is assigned the function code 24. 16 Line number
17
Within this function there are a number of sub-codes to deal 18
Called number
with internal calls, operated assisted calls and normal direct 37 (Space padded)
calls. The function sub-code we require is coded as a 4. Fig 38
10.85 describes the message format of "Call Detail" function 39 Call start time
40
24 sub-code 4. Each character is coded and sent using ASCII 41
(Hours, min,
including the value of the checksum. 42 sec)
43
Let us examine an example message coded using the 44
45
specification described in Fig 10.85. Mr Bloggs in room 305 46 Call duration
makes a call to 0291234567 at 17 minutes and 23 seconds 47 (seconds)
48
after 6pm, the call lasts 256 seconds. In this particular hotel 49
there are no metered pulses and the extension numbers are 50
51
the same as the room numBers. The message sent would be 52 Metered pulses
as follows: [STX] P2 5 24 0544 0305 006 0291234567 [10 53
54
spaces] 181723 000256 00000 [Checksum] [ETX]. When 55 Checksum
converted to ASCII codes, we get the data stream: 2 80 50 53 56 ETX
50 52 48 53 52 52 48 51 48 53 48 48 54 48 50 57 49 50 51
Fig 10.85
52 53 54 55 32 32 32 32 32 32 32 32 32 32 49 56 49 55 50
Call detail message format
514848485053 544848484848 [Checksum] 3. for the PEC2010 PABX

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 The interrelationship between software and hardware 475

The PMS software must be able to interpret this message. To do this requires a
procedure or function that firstly is able to ensure the message was received correctly
and secondly is able to extract each field from within the data stream. Imagine the
data stream is stored as a string in the variable InStream, Fig 10.86 describes a
possible algorithm for checking the input data stream has been received correctly.

BEGIN Checklnstream(lnStream,OKFlag)
Set OKFlag to False
Set LenStream to length of InStream - 2
Check message {
length is correct
Set MesLength to value of chars 7 to 9 in InStream
IF LenStream = MesLength THEN
Set Checksum to 0
Set CharCount to 2
WHILE CharCount <= MesLength
Ensure Checksum Add ASCII value of character in position Charcount to Checksum
is correct Increment CharCount
ENDWHILE
Set CheckStream to ASCII value of second last char in InStream
Set Checksum to last two digits of hex value of Checksum
IF CheckStream = Checksum THEN
Ifboth length ~ Set OKFlag to True
and checksum ENDIF
are correct ENDIF
END Checklnstream
Fig 10.86
Algorithm to check the length and Checksum of an input message.

GROUP TASK Discussion

Examine the algorithm in Fzg 10.86. Describe how the Checksum is
calculated. Why do you think the last two hexadecimal digits are used
rather than the first two digits?

For this particular 'Call Detai1' function the PMS software requires the extension
number, called number, time the call was made and the length of the call. The PMS
must also calculate and store the call charge. All this data will eventually be stored in
the guest's account. An algorithm to perform this processing is reproduced below.
BEGIN ProcessCaIiDetail(instream,CaIiRecord)
CaliRecord.Room = Value of chars 11 to 14 of Instream
CaliRecord.Phone = Value of chars 18 to 37 of Instream
CaIiRecord.Start.Hour = Chars 38 to 39 of Instream
CaIiRecord.Start.Min = Chars 40 to 41 of Instream
CaliRecordDuration = Value of chars 44 to 49 of Instream
CaliRecord.Charge = CaIiCharge(CaIiRecord.Phone,CaIiRecordDuration)
END ProcessCaliDetaii
Fig 10.87
Algorithm to extract the call details from the input data stream.

GROUP TASK Discussion

Examine the algorithm in Fig 10.87. What type of data structure is the
CaliRecord variable; describe this structure? What do you think the
CaliCharge function does? Could the ProcessCaliDetaii procedure have
been written as a function?

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476 Chapter 10

Control systems
A control system is made up of sensors that obtain data from the environment and
actuators that are able to perform output functions under the direction of a controller.
In this course, we are concerned with control systems where the controller is a
computer system. The sensors provide the input into the
system, the controller performs the processing and as a
consequence directs the actuators to perform some - . 'I
physical task. There are two broad categories of control
system; open control systems and closed control systems. •••••
An open control system is not able to react to its
environment. For example, in many hotel rooms the lock •
on each room is activated using a magnetic stripe card. The
card is encoded with details of the guest's arrival and
departure time together with a unique code particular to the
room. A sensor in the lock reads the magnetic stripe. The Fig 10.88
Hotel door locks are examples
details are processed by a controller within the lock. If of open control systems.
they are correct, an actuator unlocks the door. There is no
feedback to the controller, and in this case, none is
required.
A closed loop system is able to react to its environment. In
other words, the sensors provide feedback so that the
controller can cause the actuators to react to changes in the
environment. For example, the antilock braking system on
a car senses when a wheel has locked (stopped turning)
and causes the brake on that wheel to be momentarily
disengaged. The actuators, in this case, are a series of
valves that release hydraulic pressure in the system. A
closed loop exists between the sensors and the actuators.
Production lines that use robots to perform repetitive tasks Fig 10.89
Antilock brake systems are
utilise both open and closed control systems depending on
closed control systems.
the application. Sensors that are able to detect movement,
light and motion provide the input into these systems.
Often the actuators are electric motors that cause movement of portions of the robot.
Robots that are part of a closed system are often called intelligent robots as they able
to react to their environment. Robots that are part of an open system are known as
dumb robots as they will continue to carry out their task regardless of changes in their
environment.

GROUP TASK Discussion

Many household appliances are control systems. Discuss the operation of
a number of household appliances. What sensors and actuators are
present in these appliances? Classify each system as either an open or
closed loop system.

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 The interrelationship between software and hardware 477

HSC style questions:

Question 1.
On many major Sydney roads there are electronic messages. The EDI model 2411 is a
particular model of scrolling electronic marquee that is 200rnm high and is able to
accommodate up to 24 characters.

You are currently in the process of writing a software application to communicate

simultaneously with a set of EDI 2411 scrolling marquees and hence you need to
understand the technical aspects of the data stream required by the unit.
Refer to the EDI 2411 technical information in Fig 10.90 on the following page to
assist when answering the following.
(a) Create a data stream to display the words "HELLO WORLD" on all the
displays, the word "HELLO" should be flashing. The message is to appear from
the top of the displays, pause for two seconds, and then scroll off the bottom of
each display.
(b) A series of text messages are stored in an array called Messages. The last item
in the array is a sentinel, namely "ZZZ". Write an algorithm that creates a data
stream to display all of these messages, in the order they are stored, on all the
EDI 2411 displays.
Suggested solutions

Qu.estion 1.
(a) <CTRL-D><CTRL-G> "000" <CTRL-J> "01" <CTRL-N> <CTRL-O> "HELLO" <CTRL-O>
"WORLD" <CTRL-R>
(b) BEGIN Displaymessages
Index=l
Stream=""
Message=Messages(lndex)
WHILE Message :;f:. "ZZZ"
Stream = stream & <CTRL-D><CTRL-G> "000" <CTRL-J>
Stream = Stream & Integer part of Index /10
Stream = Stream & Remainder of Index /10
stream = Stream & Messages (Index)
Stream = Stream & <CTRL-R>
Index = Index + 1
Message = Messages(lndex)
ENDWHILE
Send stream to displays
END

GROUP TASK Activity

There are 10 EDT 2411 s along a freeway with addresses 001 to 010. Write
an algorithm which cause each marquee to cycle through an array of 10
messages such that every marquee is displaying a different message.

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 478 Chapter 10

Message P:rotocol:
<start-of-msg> <addr> <msg no> <text> <end-of-msg>
where

ITEM VALUE 1 FUNCTION

(DECIMAL)
<start-of- 4 Standard ASCII character 'EOT', also known as a 'control D', this character must be
msg> the first character of each message.
<addr> 7 Standard ASCII character 'BEL', also known as a 'control G', followed by three
48-50 standard ASCII decimal digits representing the address of the display as set on the
48-57 display from '001' to '255'. The 'BEL' character must always be the second
48-57 character of each message. The address must always be a three digit number (use
leading zero's if needed). Ifaddress '000' is entered, all marquees will display the
message.
<msgno> 10 Standard ASCII character 'LF', also known as a 'control J', followed by two
48-51 standard ASCII decimal digits representing the message number from '01' to '32'.
48-57 The 'LF' must always appear immediately after the address and the message number
must always be a two digit number (use a leading zero if needed).
<text> 01-126 Alpha/Numeric data to be displayed in ASCII 'printable' characters and ASCII
control characters to specify display options (see below).
<end-of-msg> 18 Standard ASCII character for 'DC2', also known as a control R, this character must
be the last character of each message.

'BLOCK' Commands for Moving Marqu.ees:

These commands should be placed at the beginning of a block of text. All of these commands consist of a single ASCII
'Control' character. They are used to control the visual effect of the entire block of text. lfno block command is used the
text will scroll onto the display from left to right, pause for two seconds then scroll off to the right.

'BLOCK' VALUE 2 FUNCTION

COMMAND (DECIMAL
)
'Control I' 9 This command causes the text that follows to 'JUMP' onto the display where the
«TAB» entire message appears at once. The message will then pause for two seconds and
then clisappear at once.
'Control K' 11 This command causes the text that follows to scroll rapidly 'UP' onto the display
«VT» from the bottom. The message will then pause for two seconds and then scroll
rapidly 'UP' off ofthe display.
'Control N' 15 This command causes the text that follows to scroll rapidly 'DOWN' onto the
«SO» display from the top. The message will then pause for two seconds and then scroll
rapidly 'DOWN' off of the display.
'Control ]' 29 This 'BLINK' command causes the text that follows to appear starting with the
«GS» middle horizontal row and build rapidly onto the display towards both the top and
bottom. The message will then pause for two seconds and then disappear rapidly in
reverse order.

'TOGGLE' Commands for Moving Marqu.ees:

These commands should be placed at the beginning and at the end of a block or portion of a block of text. All of these
commands consist of a single ASCII 'Control' character. They are used to control the visual effect of the block of text that
is between them.

'TOGGLE' VALUE 3 FUNCTION

COMMAND (DECIMAL
)
'Control 0' 15 This pair of commands causes the text between them to 'FLASH' on and off at
«81» approximately n second on and n second off.
'Control \' 28 This pair of commands causes the text between them to appear in double 'WIDE'
«FS» format.

Fig 10.90
Abridged extract from the technical manual for the EDl 2411 scrolling marquee.

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 The interrelationship between software and hardware 479

Question 2.
A model helicopter is controlled via RF signals from a remote control
transmitter/receiver. Within the remote control all messages are represented and
processed as ASCII characters.
The helicopter has 3 motors, one controls its forward speed, one causes it to rotate
either left or right and another causes it to either climb or dive. A series of commands
can be combined into a single data stream. Each data stream commences with an STX
or start of transmission character (ASCII code 2), followed by the total number of
characters in the command sequence, and then the actual command sequence. After
the commands an ETX or end of transmission character (ASCII code 3) terminates the
data stream.
The motors respond to the following commands sent from the remote control.
Command Description
RO Rotate left
R1 Rotate right
R Stop rotation
AO Altitude up, meaning helicopter will climb.
Ai Altitude down, meaning helicopter will dive.
A Maintain altitude.
Sn Speed where n is an integer from 0 (stop motor) to 9 (full speed)
For example the data stream <STX>6ROA 1S3<ETX> causes the helicopter to rotate left
and dive at a speed of 3.
The helicopter transmits a data stream specifYing its position every second using data
collected from its sensors. There are always 9 characters of data. The first 3 characters
represent the current bearing from 000 to 359 degrees. The second 3 represent the
altitude from 000 to 999 metres. And the final 3 characters represent the distance
travelled in the previous second from 000 to 999 metres. This data is preceded by an
STX character and is terminated with an ETX character. Hence each transmission
received by the remote control is 11 characters long. For example the data stream
<STX>180010020<ETX> means the helicopter is flying due south at a height of 10
metres and travelled 20 metres in the last second.
Wind conditions alter continuously and have a significant effect on the helicopter's
bearing, speed and altitude. As a consequence the three motors need to be constantly
altered in order for the helicopter to maintain steady flight.

GROUP TASK Activity

Assuming there is no wind or other air currents describe a likely sequence
of data streams which will cause the helicopter to rise to an altitude of 20
metres and then return smoothly to ground level and stop.

GROUP TASK Discussion

Discuss how the three motors can be used to keep the helicopter flying
on a particular course and at a particular altitude in windy conditions.

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 480 Chapter 10

An algorithm is being developed to maintain the helicopter on a constant bearing, and

at a constant altitude and speed. The main program has been written and is reproduced
below.
BEGIN ControlChopper
Get ConstBearing in degrees, ConstAltitude in metres, ConstSpeed in metres/sec
LastSpeed =5
WHILE Chopper is in the air
REPEAT
Wait
UNTIL stream arrives from chopper
Receive data stream into InStream
ConvertlnStream(lnStream, Bearing, Altitude, Distance)
OutStream =RotationCommand(ConstBearing, Bearing)
OutStream =Outstream & AltitudeCommand(ConstAltitude, Altitude)
OutStream =Outstream & SpeedCommand(ConstSpeed, Distance, LastSpeed)
Outstream =<STX> &length of Outstream &Outstream &<ETX>
Transmit OutStream to chopper
ENDWHILE
END ControlChopper
(a) Create an algorithm for the ConvertlnStream routine.
(b) Assume the helicopter is to be maintained on a constant bearing of 90 degrees,
an altitude of 30 metres and a speed of 20 metres per second.
Write down a suitable data stream to be transmitted to the helicopter after each
of the following data stream sequences. Justify your responses.
I. Transmit to helicopter: <STX>6ROAOS5<ETX>
Receive from helicopter: <STX>100035020<ETX>
II. Transmit to helicopter: <STX>6R1AOS2<ETX>
Receive from helicopter: <STX>265030015<ETX>
(c) Create an algorithm for each of the following routines.
(i) Speed Command
(ii) RotationCommand
(iii) AltitudeCommand
Suggested solutions
Question 2.
(a) BEGIN ConvertlnStream(lnStream, Bearing, Altitude, Distance)
Bearing = value of chars in position 2-4 of InStream
Altitude =value or-chars in position 5-7 of InStream
Distance =value of chars in position 8-10 of InStream
END ConvertlnStream
(b) I. <STX>2A1<ETX>. The helicopter is already turning left so no need for a
rotation command. The helicopter is too high so need to dive (AI). The current
speed is perfect so no need to alter the engine speed of the speed motor. There
are two characters in the data stream, so commence with 2.

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 The interrelationship between software and hardware 481

II. <STX>5ROAS3<ETX>. As 265 degrees is closer anti-clockwise to 90, we rotate

left (RO). The altitude is perfect so maintain altitude (A). The chopper is flying
slow, so increase engine speed by 1 from S2 to S3. There are 5 characters within
the stream so commence with 5.
(c) (i) BEGIN SpeedCommand(ConstSpeed, Distance, LastSpeed)
IF ConstSpeed = Distance THEN
SpeedCommand = 'Oll

ELSEIF ConstSpeed > Distance THEN

IF LastSpeed<9 THEN
Add 1 to LastSpeed
Speed Command = "S" & LastSpeed
ENDIF
ELSE
IF LastSpeed >0 THEN
Subtract 1 from LastSpeed
SpeedCommand = "S" & LastSpeed
ENDIF
ENDIF
END SpeedCommand
(ii) BEGIN RotationCommand(ConstBearing, Bearing)
IF ConstBearing = Bearing THEN
RotationCommand = "R"
ELSE
Temp =ConstBearing - Bearing
IF Temp < -180 THEN
Add 360 to Temp
ELSEIF Temp> 180 THEN
Subtract 360 from Temp
ENDIF
IF Temp> 0 THEN
RotationCommand "R1"=
ELSE
RotationCommand = "RO"
ENDIF
END RotationCommand
(iii) BEGIN AltitudeCommand(ConstAltitude, Altitude)
IF ConstAltitude =Altitude THEN
AltitudeCommand ::: "A"
ELSEIF ConstAltitude > Altitude THEN
AltitudeCommand ::: "AO"
ELSE
AltitudeCommand = "A1"
ENDIF
END AltitudeCommand

GROUP TASK Discussion

Work through the operation of the ControlChopper algorithm including
the subroutine calls and suggest suitable methods of testing the system.

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 484 Chapter 10

My computer teacher

If only ALL teachers

could be as clever as
my computer teacher.

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Software Design and Development - The HSC Course

486 Chapter 10

Software Design and Development -The HSC Course