Digital IC-Tester PDF
Digital IC-Tester PDF
DIGITAL
I.C. TESTER
JOE FARR
Let a PIC and a PC check the health of are used by IC2’s internal circuitry to con-
vert the supplied voltage from 5V to ±12V.
your digital logic chips. Connection to the PC is via a 9-pin female
D-type connector, SK2.
To test the functionality of a digital logic
i.c., a known set of logic levels must be
D
presented on each pin and the resulting
URING project construction, many
hobbyists must have wondered if
CIRCUIT DESCRIPTION responses received back from the i.c. then
The complete circuit diagram for the analysed.
the reason their masterpiece wasn’t Digital I.C. Tester is shown in Fig.1. When
working was due to a faulty i.c., or if the
i.c. they’ve just removed from an old board
power is supplied to the board, it first pass- I/O PINS
es through bridge rectifier REC1. If the The PIC16F877 has a total of 33 I/O
actually works. The project described here input supply input is a.c., REC1 converts it
provides a simple way to quickly test the (input/output) pins. Of these, 24 are used
to d.c. If the input is already d.c. it ensures to connect the PIC to the i.c. under test.
operation of most TTL and CMOS digital that the polarity is correct for IC1, which
i.c.s. Each of the 24 I/O pins is connected to a
then regulates the voltage down to approx- pin on the i.c. test socket (SK3) via a 1009
imately 5V. Capacitors C1 to C4 plus C11
HOW IT WORKS provide smoothing.
resistor, within resistor modules RM1 to
RM3. These resistors act as current lim-
To explain how the Digital I.C. Tester A PIC16F877-20 microcontroller, des-
works, let’s examine the humble 7400 TTL iters to protect the PIC and the device
ignated as IC3, is used as the core of the under test. The danger is that an output of
NAND gate device as an example. The circuit and is run at its maximum speed of
datasheet says the package contains four the test i.c. could become connected to a
20MHz, as defined by crystal X1. Since PIC I/O pin also designated as an output.
logic gates, each one having two inputs this design uses RS232 protocol to inter-
and one output, which behave according to Each pin on the i.c. test socket is biassed
face to a serial port on a PC, a voltage level to the +5V test power rail via a 4k79 resis-
the truth table in Table 1. converter is employed to convert the PIC’s tor (within resistor modules RM4 to RM6).
5V logic levels to the ±12V levels required This is to force unused pins on the test
Table 1. Truth table for a 2-input by the RS232 standard (many PCs do not
NAND gate socket to a known logic level, and also
actually require this higher voltage for ser- enables open collector TTL i.c.s that have
Input 1 Input 2 Output ial comms input and will accept +5V/0V their outputs either floating or pulled to
L L H inputs. Ed). ground to be tested.
L H H This is accomplished by IC2, a During the test cycle, the PIC sends a
H L H MAX232 line driver. Capacitors C5 to C8 low logic level to the base of transistor
H H L
+
COM
TR1
SK1 R1 R3 BC213
+ + 470Ω 4k7 e
C1 C4 R2 b
REC1
220µ 220µ 1k
a POWER
C2 C3 C11 D1 c
- a
100n 100n 100n D2
POWER k
IN 1N4148
k
TB1 RM4
4 4k7
0V
3 TP1
MCLR
2
DATA +5V PATCH PIN
1
CLK
11 32
RM1 1
+VE +VE
100Ω MCLR RM2
100Ω
1 16 2
RA0/AN0 40 1 16
3 PGDA/RB7
RA1/AN1 39
4 PGCLK/RB6
RA2/AN2/VREF- 38
5 RB5
RA3/AN3/VREF+ 37
6 RB4
NC RA4/TOCK1 36
7 PGM/RB3
RA5/AN4/SS 35
8 RB2
RE0/AN5/RD 34
9 RB1
RE1/AN6/WR 33
10 INT/RB0
RE2/AN7/CS
C9
IC3
PIC16F877-20P
10p RM3
13 100Ω
OSC1/CLKIN
30 1 16
PSP7/RD7
R6 X1 R4 R5 29
470Ω C10 20MHz 2k2 2k2 PSP6/RD6
10p 28
14 PSP5/RD5
OSC2/CLKOUT 27
PSP4/RD4
15 26
T1OSO/T1CKI/RC0 RX/DT/RC7
16 25
T1OSI/CCP2/RC1 TX/CK/RC6
17 24
TP6 TP5 CCP1/RC2 SDO/RC5 NC
TEST 18 23
+5V TP3
* TP4
SCK/SCL/RC3 SDI/SDA/RC4 NC
19 22
ON PSP0/RD0 PSP3/RD3
a a 20 21
PSP1/RD1 PSP2/RD2
D3 D4
k k
COMMS
GND GND
R7
12 31
470Ω
*SEE TEXT
TR1 via resistor R3, which in turn applies A power supply unit capable of supply- required. If a turned pin socket is not avail-
power to the i.c. under test, via either the ing around 100mA and between 9V to 12V able, two rows of turned pin socket strips
power patch pin (TP1) or via the dual-in- should be ideal. If the input voltage can be used instead.
line (d.i.l.) switch module S1. exceeds this, then it might be necessary to Provision has been made on the p.c.b. to
Transistor TR1 also supplies +5V to the fit a larger heatsink to IC1. The prototype accommodate two pairs of turned pin
common pins of the pull-up resistors within draws approximately 30mA when in socket strips, one pair of 10 pins (within
modules RM4 to RM6. As soon as testing is standby, rising when testing. The exact the SK3 area), and one pair of 12 pins
complete, TR1 is switched off automatical- current drawn will depend on the i.c. being (TB2 and TB3) which may be used if it is
ly, disconnecting power from the test i.c. tested. decided not to use a ZIF socket. This
Capacitor C12 provides smoothing of the allows narrow i.c. packages of up to 20
switched +5V rail from TR1. TEST SOCKET pins or the wider packages of up to 24 pins
With power applied to the board and There are several possible choices for the to be tested. Though not as convenient as a
TR1 off (non-test mode), the PIC’s RB6 method that will be used to connect i.c.s to ZIF, this does make a cheaper option.
and RB7 pins are available to allow an the tester via socket SK3. The preferred
external programmer access to the PIC. method is a ZIF (Zero Insertion Force) sock- D.I.L. SWITCH
et. They are available in different sizes and OPTIONS
POWER SUPPLY formats but one should be chosen that Power can be applied to the i.c. under
It is expected that when in service the accepts i.c.s of up to 24 pins and different test either via the jumper patch pins (TP1
project will be powered from a sealed package widths (a “universal” type). and TP2), or predefined power configura-
plug-in mains power supply adaptor. The ZIF socket can be mounted directly tions can be selected from the 4-way d.i.l.
Either an a.c. or d.c. power supply unit can on the board, or a 24-pin turned socket can switch bank, S1. This switch allows a
be used and the connections to the printed be fitted first and then the ZIF pushed GND (0V) connection to be made to pin
circuit board (p.c.b.) are not polarity firmly into that. This allows the ZIF to be 12 of the test socket and a +5V connection
sensitive. easily removed and used elsewhere if to be made to pins 19, 20 and 22, as
718 Everyday Practical Electronics, October 2002
RM5 RM6
4k7 4k7
+
1 2
C1+ V+
3
C1
6
C7
1µ
IC2 V
SERIAL CABLE LINKS
MAX232 (SEE TEXT)
+
4
C2+
5 SK2
C2
11 14 TP7 TP8
T1 IN T1 OUT 1
10 7
NC T2 IN T2 OUT NC 2
12 13 TP9 TP10
R1 OUT R1 IN 3
9 8
NC R2 OUT R2 IN NC 4
GND 5
15 6
7
C8 8
1µ +
9
COMPONENTS C5 to C8
C9, C10
1m radial elect. 50V
(4 off)
10p ceramic disc, 5mm
SK1
SK2
power connector
(see text)
9-way D-type sub-min.
pitch (2 off) connector, female,
Resistors See C12 10m radial elect. 16V p.c.b. mounting
SHOP
R1, R6, R7 470W (3 off) SK3 24-pin universal ZIF
R2 1k Semiconductors socket (see text)
R3
R4, R5
4k7
2k2 (2 off)
TALK REC1
D1, D3
bridge rectifier 50V 1A
green l.e.d., 3mm (2 off)
TB1 4-way terminal pin
strip
page D2 1N4148 signal diode TB2, TB3 turned pin socket strip
RM1 to
RM3 100W 8 x D4 red l.e.d., 3mm (2 x 12-way) (see text)
individual resistors d.i.l. TR1 BC213 pnp transistor
module (3 off) (or similar) Printed circuit board, available from the
RM4 to IC1 7805 +5V 1A voltage EPE PCB Service, code 371; p.c.b.
RM6 4k7 8 x commoned regulator supports (4 off); 40-pin d.i.l. socket; 16-pin
resistors s.i.l. module IC2 MAX232 RS232 line d.i.l. socket (4 off); heatsink 21°C/W for
(3 off) driver IC1 and mounting hardware; solid insulat-
All 0·25W 5% carbon film or better except IC3 PIC16F877-20P ed wire for jumper links; solder, etc.
RM1 to RM6. microcontroller,
preprogrammed
Capacitors (see text)
C1, C4 220m radial elect. 25V
£25
(2 off) Miscellaneous
X1 20MHz crystal Approx. Cost
C2, C3, C11 100n ceramic disc, Guidance Only
5mm pitch (3 off) S1 4-way s.p.s.t. d.i.l. switch,
p.c.b. mounting (see text) excl. connectors
SK1
*SEE TEXT
HEATSINK
D1 SK2
TP7 TP8
a k
IC1 R
C5
*
1
REC1
COM IC2 TP9 TP10
C1 IN OUT
+
+ C4 +
+ + C12 e b c
+ +
4 3 2 1 C2 C3 C8 TP1
C6 C7
TB1 + R
k a RM4 TP2 RM6 TR1 3
D2
TB2 TB3
*S1
RM2
R 5 4
RM1 3
2 *SK3 6
7 2
IC3 8 1
C11
R C9
6 R
7 RM3
C10 X1
TP3
TP4
R5
TP6
R4
D4
TP5 * RM5
a k
D3
a k
6.05in (153.7mm)
4.025in (102.2mm)
371
Fig.2. Printed circuit board component layout and full size copper foil master track pattern.
TEST PROCEDURE
When ready, click the Start button.
Because this is the first time you have test-
ed an i.c. with this power pin configuration,
a dialogue box is displayed (see Photo 6).
The picture shows how to correctly apply
power to the i.c. under test. Also, it shows
you how the i.c. should be inserted in the
socket.
Notice that in this case, no power patch
wires are required as this i.c. package is
supported by the on-board d.i.l. switches.
So, set d.i.l. switches S1/3 and S1/4 to the
ON position, as indicated.
Press OK to start the test. All being well,
after a couple of seconds you should have
a display similar to that in Photo 7.
Select Window from the top menu and
then Tile Vertically to get the software to
arrange everything neatly for you on the
screen.
In the case of the i.c. represented in Photo 7. Typical screen display during testing, on this occasion showing that the i.c.
Photo 7, it actually failed during the testing is faulty (see text).
process. The right hand panel shows that
the problem occurred with pattern 11, the logic level dropped from high to
sequences 0007 and 0008. Sequence 0007 low before it was expected. Another
shows what the Digital IC Tester sent to the option available is GND, located directly
i.c. Sequence 0008 shows what the device under the Diff option. Enabling GND
profile says should be the response from forces a dotted line showing where the
the i.c. The next line shows what the low logic level for each pin would be on
response from the i.c. actually is. An “X” the display. This makes a useful trace
means Don’t Care about the logic level. separator when the screen starts looking
Whilst this is helpful, it is not too clear crowded.
exactly what the problem is. The trace on
the left hand side of the screen shows the
logic levels present on each pin of the i.c.
CREATING PROFILES Photo 10. Creating an i.c. test proce-
dure profile.
Since the number of i.c. devices on the
during the test. The trace is updated after market is constantly changing, the tester
each Read operation is performed. would soon become obsolete if the user did repeatedly clicking on each pin in the
The display has four yellow traces which not have the ability to add new profiles as usage column. Additionally, you can create
are the outputs of each of the four NAND required. To create a new profile, select short tags (descriptions) for each pin,
gates. Since they should all behave the Create IC Profile on the main Tools menu, which are displayed along with the pin
same, it’s quite clear that there is a problem see Photo 9. numbers on the Logic Trace screen. When
with the gate whose output is on pin 11. In You will need to enter the i.c.’s type ready, click the Next button.
some cases, though, the actual problem number and a brief description about the
might not be clear, especially if the i.c.
only contains one or two gate arrays. If you
device. Next select how many pins the TEST EXAMPLE
device has, and specify which pins are des- You must now tell the Tester what logic
select Diff on the Pin Logic Trace, the trace ignated as inputs, outputs, power or have levels to send to the i.c. and what the
display will change and look similar to that no internal connection. You do this by expected results will be (see Photo 10).
in Photo 8. To test a 7400 quad 2-input NAND gate,
The dotted line indicates what the pro- for example, 10 instructions are required:
file is expecting back as a response from
the i.c. under test. As can be seen with pin Sequence 1 – Reset. This sends a Reset
command to the PIC and should always be
included unless there is a specific reason
not to. You can include as many Reset com-
mands as required and at any location with-
in the script.
Sequence 2 – +VE On. This switches
on the +5V supply to the i.c. under test. It
also applies +5V via transistor TR1 to the
three commons of the pull-up s.i.l. resistor
modules, RM4 to RM6.
Sequence 3 – Send. Here, we are send-
ing low logic levels to pins 1, 2, 4, 5, 9, 10,
12 and 13. These pins were defined on the
Photo 8. Test screen in “difference” Photo 9. Creating an i.c. pin function previous screen as inputs. You can only
highlighting mode. profile. send logic levels to pins defined as inputs.
Sequence 4 – Read. We now read back under Tools, Configuration (see Photo 2
the logic levels from the i.c. being tested. earlier). When selected, there are five
We expect pins 1, 2, 4, 5, 9, 10, 12 and 13 groups of configuration settings that can be
to be low since we have set them low in changed.
the previous instruction. However, we The first group deals with the serial
must now indicate which logic levels are interface characteristics. The COM port
expected on each output pin. According and interface speed are changed here. At
to the truth table we looked at for a the bottom of the screen there is a Timing
NAND gate earlier, all gates should Adjustment button. In certain circum-
return a high logic level. We now contin- stances, it is possible to under-run the PC’s
ue sending logic levels to the i.c. being serial buffer. Increasing this value forces
tested and then reading back the actual the PC software to wait longer for incom-
logic levels from it. ing data, the drawback being that the soft-
There is no need to send a Config com- ware will run slightly slower.
mand in the above sequence since the PC To check that this setting is correct,
software sends the required configuration insert a known good i.c. into the tester and
based on the profile information you spec- set for continuous testing. If after the
ified on the first screen during the profile default 999 tests no failures have been
creation. reported then the setting is correct. If any
failures are detected then this value should
MULTIPLEXED PINS be increased by a value of 1 and the test
performed again.
Some i.c.s, however, have pins that can be
either an input or an output, depending on The next group allows the information
the logic level of some other pins, and the display colours to be changed. Clicking
74245 is an example of this (see Photo 11). any of the coloured panels brings up the
At Sequence 7, a Config command has colour picker dialogue.
been inserted. This enables the tester to be The Paths groups allows the default
reconfigured and specify which pins are location of the Data Models (i.c. types)
inputs or outputs. Testing resumes from storage path to be specified. Clicking the
Sequence 8. ellipsis button on the right (the one
Select the Reset command and click Add with . . .) allows you to explore the avail-
Instruction. A new line will be added to the able disk drives and folders and locate the Photo 12. Logic analyser experimental
display. Do the same for +VE On. Next, location of the data model files. screen.
insert a Send command. This is the binary The settings groups allow some display
pattern we want to present to the i.c. under options and the DIP switch type and usage
to be specified. The Show Tool Bar and It is worth noting that, in most cases,
test. Logic levels are changed by clicking holding the mouse pointer over a control or
the cell on the new line that you want to Show Status Bar options allow the Tool
and Status bars to be shown or hidden, button will provide some additional infor-
change. mation on its use.
Normally, after a Send command, you which is useful if screen real estate is
scarce.
will perform a Read. But this is not always
In some cases, the software attempts to EXTERNAL LOGIC
the case. For the Read, you can specify that
a pin designated as an output should have gain the user’s attention by flashing mes- ANALYSING
sages on the screen. The option Allow An additional feature was added to the
either a High or Low logic level or that it software to experiment with displaying
doesn’t matter (“X”). Flashing Text controls whether these mes-
sages flash or are static. logic states for i.c.s running in-circuit on
Once the required instructions have been other p.c.b.s, and this has been left in the
created, press OK to save the profile. The option Always Warn About Test IC
Power Pin Configuration controls how the published software for reader’s own exper-
The up and down arrow buttons allow imentation purposes (see Photo 12).
lines to be moved up and down in the exe- software warns the operator about the power
pin configuration of the i.c. under test. If A test connector, consisting of an i.c. test
cution order. The Delete Line button allows clip, connected to a piece of ribbon cable
instruction lines to be removed from the On, the software always issues a warning. If
Off, the software only issues a warning and terminated with a 24-pin i.c. header
profile. plug, allows the Digital I.C. Tester to be
when either the first i.c. of the session is to
be tested or a new i.c. type has been select- connected to the in-circuit i.c. Once con-
CONFIGURATION ed that has a different power configuration nected the Logic Analyser function can be
OPTIONS from the previous type tested. selected from the Tools menu.
The configuration options can be select- The DIP Type options control the look The Logic Analyser monitors and
ed from the main menu and are located of the graphic used for showing the d.i.l. reports the logic levels on between 1 and
724 Everyday Practical Electronics, October 2002
optional trigger pattern can be specified if times. This means that when changing and compare them with its technical specifi-
required. A “tick” indicates a high logic logic levels are trying to be captured, there cation. Perhaps when a PIC is available with
state and the absence of a tick indicates a is a possibility of inconsistent or unexpect- 24 onboard analogue-to-digital converters,
low logic state. When all monitored pins ed results being displayed. the author will revisit the design.
have the specified trigger pattern, the Also, no matter what settings you
Analyser is triggered. select, the PIC frantically transfers data ACKNOWLEDGEMENT
There are two primary modes of operation as fast as it can to the PC and does not The author would like to thank his brother
for the Analyser. The mode Only Detect store any of the results internally. This Peter for supplying a large selection of “test
Pattern Changes displays each new logic pat- means that the capture speed is limited to subjects”, most of which looked like they
tern as it changes. Free Running grabs the the maximum speed of the serial inter- belong in the Science Museum!
logic levels as fast as possible. If Free face, making it quite slow in relation to
Running is selected, an optional delay can be today’s computer speeds. RESOURCES
specified from 0 to 9999ms between each All software for this project is available
sample being made. Update Pin Display and CONCLUSION for free download from the EPE ftp site, or
Logic Display work as previously discussed. The Digital I.C. Tester has successfully on CD-ROM (for which a charge applies)
The Activate Device Pull-Ups controls tested a variety of i.c.s without any prob- from the EPE Editorial office, see the EPE
whether the s.i.l. pull-up resistor modules lem, including 74, 74F, 74LS, 74HC and PCB Service page for details. The PIC pro-
(RM4 to RM6) have their common connec- CMOS 4000 series. The only slight excep- gram software is supplied in MPASM for-
tions powered or not. tion to this was with the HC series. These mat (.ASM and .HEX). See this month’s
When the logic analyser starts, it refused to test correctly with the original Shoptalk page for details of obtaining pre-
instructs the PIC to “grab” logic level sta- prototype which used 3309 buffer resistor programmed PICs.
tus information as fast as possible and modules (RM1 to RM3). These were The datasheet for the MAX232 is avail-
transmit this to the PC. The PC then swapped for 1009 ones, as specified for able from the Maxim website at
attempts to process and display this infor- this published version, and then the offend- www.maxim-ic.com.
mation. Because of this, the analyser has ing i.c.s tested fine. Datasheets for the majority of TTL i.c.s
several practical limitations. The design aims to give a go/no-go logic can be found on Texas Instruments web
Firstly, due to the hardware design and report on the i.c. being tested. It is beyond site at www.ti.com. 6