EXPERIMENT 5

Title: Write VHDL code for the logic gates and simulate it.
Write VHDL code for the following combinational circuits and simulate it.
1. Half adder
2. Multiplexer (4:1)
Software: Xilinx ISE 14.7
Theory:
Introduction to VHDL:
VHDL stands for Very High-Speed Integrated Circuit Hardware Description Language.
A language for describing the structural, physical and behavioral characteristics of digital
systems.
Execution of a VHDL program results in a simulation of the digital system.
o Allows us to validate the design prior to fabrication.
o The definition of the VHDL language provides a range of
features that support simulation of digital systems.
 
VHDL supports both structural and behavioral descriptions of a system at multiple levels of
abstraction.
Structure and behavior are complementary ways of describing systems.
o A description of the behavior of a system says nothing about
the structure or the components that make up the system.
o There are many ways in which you can build a system to provide
the same behavior.
 
Basic Language Concepts
Signals: Like variables in a programming language such as C, signals can be assigned values,
e.g., 0, 1, Z.
 
However, signals also have an associated time value.
A signal receives a value at a specific point in time and retains that value until it receives a new
value at a future point in time.
 
The sequence of values assigned to a signal over time is the waveform of the signal.
 
A variable always has one current value.
At any instant in time, a signal may be associated with several time-value pairs.

VHDL code Structure: 1.Library 2.Entity 3.Architecture

Library Clause

Formal Definition

A library clause defines logical names for design libraries in the host environment.

Simplified Syntax

library library_name;

Description

The library clause defines the logical names of design libraries, which are used by the design
units. A library is a storage facility for previously analysed design units. In practice, this relates
mostly to packages.

When a package is to be used in a design, it has to be made visible to the design. In order to
specify it, the library clause (making the library visible) and use clause (making particular
declarations visible) must be used. See use clause for more details.

There are two predefined libraries, which are used implicitly in every design: STD and WORK.
The first of them contains standard packages STANDARD and TEXTIO. The other is a working
library, where all user-created and analysed design units are stored.

User-specified packages are stored in the working library WORK.

Examples

library IEEE;
use IEEE.Std_Logic_1164.all;

 
Such declarations as in the above example must precede each design entity, which uses any of
the declarations in the package Std_Logic_1164.

Entity-Architecture
Design entity: A component of a system whose behavior is to be described and simulated.
 
Two components to the description:
 The interface to the design: entity declaration.
 The internal behavior of the design: architecture construct.
  Entity

Formal Definition

Entity is the description of the interface between a design and its external environment. It may
also specify the declarations and statements that are part of the design entity. A given entity
declaration may be shared by many design entities, each of which has a different architecture.
Thus, an entity declaration can potentially represent a class of design entities, each having the
same interface.

Simplified Syntax

entity entity_name is

      generic (generic_list);

      port (port_list);]

end entity entity_name;

Description

An entity specifies the interface between the specified design (formally called a design entity)
and the environment in which it operates. On the other hand, an architecture is a description of
the inner design operation and it must be assigned to an entity. The architecture can be assigned
to one entity only but one entity may be assigned to a number of architectures.

The entity statement declares the design name (the identifier item in the Syntax example). In

addition, it defines generic parameters (see generic) and ports (see port) of the design entity.
Generic parameters provide static information (like timing parameters or bus width) to a design.
Ports provide communication channels between the design and its environment. For each port, its
mode (i.e. data flow) and type are defined.

Optionally, an entity may contain a declarative part. Any subprograms, types, subtypes, and
constants can be declared here.

Declarations which are defined in an entity are visible to all architectures assigned to this entity.

An entity may contain its own statements, declared after the begin keyword. The statements here
must be passive, which means they cannot alter values of any signals; Passive processes,
concurrent assertion statements and passive concurrent procedure calls can be used here.

The entity declaration may be preceded by the library and use clauses. This way all declarations

defined in a package will be visible for the entity and all architectures assigned to it.
  Architecture

Formal Definition

A body associated with an entity declaration to describe the internal organization or operation of
a design entity. An architecture body is used to describe the behavior, data flow, or structure of a
design entity.

Simplified Syntax

architecture architecture_name of entity_name is

  architecture_declarations

begin

  concurrent_statements

end [ architecture ] [ architecture_name ];

Description

Architecture assigned to an entity describes internal relationship between input and output ports
of the entity. It consists of two parts: declarations and concurrent statements.

First (declarative) part of an architecture may contain declarations of types, signals, constants,

subprograms (functions and procedures), components, and groups. See respective topics for
details.

Concurrent statements in the architecture body define the relationship between inputs and

outputs. This relationship can be specified using different types of statements: concurrent signal
assignment, process statement, component instantiation, concurrent procedure call, generate
statement, concurrent assertion statement and block statement. It can be written in different
styles: structural, dataflow, behavioral (functional) or mixed.

The description of a structural body is based on component

instantiation and generate statements. It allows to create hierarchical projects, from simple gates
to very complex components, describing entire subsystems. The connections among components
are realized through ports. Example 1 illustrates this concept for a BCD decoder.

The Dataflow description is built with concurrent signal assignment statements. Each of the

statements can be activated when any of its input signals changes its value. While these
statements describe the behavior of the circuit, a lot of information about its structure can be
extracted form the description as well. Example 2 contains this type of description for the same
BCD decoder as in the previous example.
The architecture body describes only the expected functionality (behavior) of the circuit,
without any direct indication as to the hardware implementation. Such description consists only
of one or more processes, each of which contains sequential statements (Example 3).

The architecture body may contain statements that define both behavior and structure of the
circuit at the same time.

Behaviroal

Entity example for half adder:

 half_adder is the name given to the design entity.

 
 The input and outputs signals; a , b , sum and carry , are referred to as ports .

Entity-Architecture
 Each port has a type, bit and bit_vector can assume values of 0 and 1.
 Each port has a mode; in , out or inout (bidirectional signals).
 
 Bit vectors are specified as:

 A and B are 32 bits long with the most significant bit as 31.

 
A more general definition
of bit and bit_vector are std_logic and std_logic_vector , which can assume
more than just 0 and 1.
Entity-Architecture
 Architecture construct:
 

Modeling Behavior, Processes

 Processes are used:

 For describing component behavior when they cannot be simply modeled as delay
elements.

 To model systems at high levels of abstraction.

o Process incorporate conventional programming language constructs.

o A process is a sequentially executed block of code, which contains.

 arrays and queues.

 Variable assignments, e.g., x := y , which, unlike signals, take effect immediately.

 if-then-else and loop statements to control flow.

 Signal assignments to external signals.

o Processes contain sensitivity lists in which signals are listed, which determine

when the process executes.

Procedure: Write steps for creating project using Xilinx ISE14.7, create Testbench VHDL
program for source code and simulation steps. (Copy from your practical notebook)

Conclusion:

Note: attached printout with this write up (vhdl code,RTL/Technology schematic,Testbench

code and waveforms)