Introduction to

1
VLSI Design
Lecture# 01
VLSI Design

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

2 Course Introduction
 Course Title: VLSI Design
 Course Code:EEE434
 Class: EEE-6
 Text Book
 Introduction to VLSI Circuits and Systems
 By John P. Uyemura

 Reference Books
 VLSI Design
 Debaprasad Das
 CMOS VLSI Design
 Neil H. E. Weste and David Money Harris

 Course Assessment
 Quizzes (Announced)
 Assignments (A lot)
 Exams
COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi
3 Instructor and Content
 Course / Lab Instructor: Dr. Sohaib Ayyaz Qazi
 Contact me at
 [email protected] (please be careful
with spellings)
 Course Material / Announcements will be available at
http://saqazi.com/vlsidesign
 Office 213, Faculty Block 1, CU Islamabad

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

4 Course Grading
 Theory

Module Marks Remarks

Sessional – I 10
Sessional – II 15
Quizes 15 4 Quizes Announced
Assignments 10 A lot of them
Terminal 50
 Lab

Module Marks Remarks

Lab Sessional – I 10 Within Labs, Tasks to be done
Lab Sessional – II 15 alone

Lab Assignment 25 Your cumulative performance in

all Labs
Terminal 50 Semester Project
COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi
5 Some Rules to Remember
 Attend classes regularly
 Three late attendance will be marked as one absent
 Students who are facing low grades or on prob, start studying
hard from DAY1.
 Be attentive in class, you will get lecture slides but not the notes
written on Board
 Any type of COPY in all evaluations will get straight ZERO for
both
 Please come in lab with completed Pre-lab tasks.
 If you don’t complete lab, you will not get full marks.

CR, Be active or you will be replaced soon

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

6 Course Learning Outcomes (CLOs)

 Understand and explain the importance of VLSI, design hierarchy,

design metrics, IC fabrication materials and IC fabrication processes.
(C2-PLO1)

 Implement and analyze complex logic circuits and layout (physical

design) using static CMOS logic and transmission gates. (C4-PLO2)

 Design electrically and geometrically individual MOSFETs,

interconnects and other layers as well as logic gates, modules and
complete circuits in a CMOS IC. (C4-PLO3)

 Apply advanced techniques in CMOS logic circuits (dynamic, dual-

rail and domino etc.) and explain reliability of ICs. (C3-PLO1)

 Use CAD tools to implement and verify behavioral, RTL, circuit and
layout level designs. (A3-PLO5)

 Present and analyze data with effective report writing skills.

(A2-PLO10)

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

7 Course Contents
Week # Lecture Topics
Week 01 Introduction and design metrics
Week 02 Logic design using MOSFETs
Week 03 Physical structure of CMOS ICs
Week 04 CMOS layers, designing MOSFET arrays (logic gates) in layout
Week 05 Fabrication process of CMOS ICs, lithography and design rules
Week 06 Elements of physical design
Week 07 Electrical characteristics of MOSFETs
Week 08 Electronic analysis of CMOS Logic Gates
Week 09 Advances techniques CMOS logic circuits
Week 10 System specifications using VHDL or Verilog
Week 11 General VLSI system components (multiplexors, latches and registers etc.)
Week 12 Arithmetic circuits in CMOS VLSI (Adders and multipliers etc.)
Week 13 Memories architectures and core design

Week 14 System level physical design (delays, crosstalk, scaling & power consumption)

Week 15 Reliability, testing and Design for Test (DFT)

Week 16 Revision

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

8 Introduction to VLSI (1/2)
 VLSI is an acronym for Very Large Scale Integration
 Very dense electronic Integrated Circuits (ICs)
 Large number of switching devices (transistor) per unit area
 The number of transistors has exceeded 1 billion per chip (IC)1
 Nowadays up to tens of billions2

Year Era Level of Integration

1958 Single Transistor -

1960 Monolithic IC 1
1962 Multi-function 2-4
1964 Complex function 5-20
1967 Medium scale integration (MSI) 20-200
1972 Large scale integration (LSI) 200-2000
1978 Very large scale integration (VLSI) 2000-20,000

1989 Ultra large scale integration (ULSI) Above 20,000

1Peter Clarke, EE Times, “Intel enters billion-transistor processor era”, 14 October 2005
2Antone Gonsalves, EE Times, "Samsung begins production of 16-Gb flash", 30 April 2007

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

9 Introduction to VLSI (2/2)
 In order to achieve higher integration density
 Transistor sizes are being decreased (scaling)
 Transistor scaling is usually referred by channel length
 Transistor scaling has also raised some issues along with
the benefits
 Power density
 Velocity saturation
 Other short channel effects

Parameter Trends Transistor scaling

Number of transistors per IC Increasing and operating
Transistor size Decreasing frequency
reaching its limits.
Operating frequency (speed) Increasing
New solutions are
Operating voltage Decreasing (to decrease power being adopted.
consumption)

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

10 Moore’s Law

 Gordon Moore suggested that the number of

transistors in an IC
 Will double every 18 to 24 months
 So far, the Moore’s law is holding, some what
 But it is also struggling
 As Gordon Moore himself said in 2015 1
 “I guess I see Moore’s law dying here in the next decade or
so, but that’s not surprising.”

1Moore, Gordon. “Gordon Moore: The Man Whose Name Means Progress, The visionary engineer reflects on 50
years of Moore’s Law”, March 30, 2015
2Image courtesy http://www.cringely.com/2013/10/15/breaking-moores-law/ 2016-02-09 at 1100 hrs

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

11 VLSI Complexity and Design (1/2)

 As the integration density increases

 It also increases design complexity

Engineers
 So, it is required to have Sand
Marketing
 Design team Idea
 Design hierarchy $$$$$$$

Super chip

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

12 VLSI Complexity and Design (2/2)
 Mostly top-down approach
 Bottom-up is only feasible for small projects

Top
design System Specifications Initial concept
level

Abstract high-level model System design

VHDL, Verilog HDL and verification

Logic design
Logic Synthesis and verification

CMOS design
Circuit Design and verification
Bottom
design Physical Design Silicon logic design
level and verification

Mass production,
Manufacturing testing &
packaging

Finished VLSI Chip Marketing

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

13 Comparison of Approaches

Top - Down Bottom – Up

 Theoretical  Starts at Silicon

 Abstract Level Definitions  Builds Primitives
 No Direct Connection with  Combined to get
Silicon complex logic blocks
 Suitable for Complex  Suitable for small projects
Circuits (Almost each
design today)

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

14 VLSI Chip Types
 Full Custom
 Every circuit is custom designed
 Time consuming, high initial cost
 Suitable for mass-production
 Application Specific Integrated Circuits
(ASICs)
 ICs for a particular application
 Designers use CAD tools to translate
higher level design to create layout
 No access over low-level electronics
design
 Suitable for low-production and
prototyping
 May involve using IP cores
 Semi-Custom
 Hybrid of the above two
 Using standard cells and custom
designed circuit

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

15 Design Metrics (1/2)

 The design quality is measured in terms of the following design

metrics
 Functionality
 What operations it can perform on number of I/Os etc.

 Cost (non-recurring and recurring)

 NRE (Non-Recurrent Engineering) costs
 One time cost factor, like, design time, design effort etc.

 R&D, Infrastructure building, training, manufacturing equipment, VLSI CAD

tools

 Recurrent Costs
 Proportional to volume, chip area

 Silicon processing, packaging, testing

 Reliability
 noise margin/immunity

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

16 Design Metrics (2/2)
 Power dissipation (speed, power, energy)
 Peak and average power dissipation,
 Energy

 Speed (delay, operating frequency)

 Delays between process input and output
 Maximum operating frequency

 Time-to-market
 An integrated circuit must be designed, verified, and finally
implemented
 As quick as possible to become available first in the market
to beat the competitors.

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

 17 Design Domains (Y-chart)

 The IC design can be described in the

following three domains:
Processor
 Behavioral
Register Algorithm
 Circuit is described by its behavior Gate Register Transfer Language
Transistor Boolean Expression
 And not physical implementation or
Differential equation
structure

 Structural Transistor

 Circuit is described by components and Cell

interconnections

Physical
Module
 Physical
Floorplan
 Deals with actual geometry
 Described by shape, size and location of Gajski−Kuhn Y-chart
components

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

18 Computer Aided Design (CAD)
 Since the technology has allowed to reach todays integration
levels
 We need to use CAD tools to cope with the design complexity
 A simple three loop circuit calculation requires three equations to be
solved
 Imagine the analysis/design complexity for millions and billions of
transistors
 CAD tools, fully or partly automate the VLSI design steps

Implementation Tools Verification Tools

Logic and Physical Synthesis Simulation
Design for Test (DFT) Timing analysis
Full custom layout Formal Verification
Floor planning Power Analysis
Place and route DRC and LVS

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

 Logic Design using
19
MOSFETS – Part 1
Lecture# 01
VLSI Design
20 Logic Design Using MOSFETs

➢ Ideal Switches

 Assert-high controlled switch

𝐴=0 𝐴=1

𝑥 𝑦 𝑥 𝑦

Open Closed 𝑦 = 𝑥. 𝐴
if and only if 𝐴 = 1
 Assert-low controlled switch

𝐴=0 𝐴=1

𝑥 𝑦=x 𝑥 𝑦
Closed Open 𝑦=𝑥
if and only if 𝐴 = 0

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

21 Ideal Switches (Assert High)
➢ Logic Gates

 AND gate (switches in series)

𝑎 𝑏

𝑔 = 𝑎⋅𝑏
1 𝑔 =𝑎⋅𝑏
a.1 𝑎⋅1 ⋅𝑏 if and only if 𝑎 = 𝑏 = 1
Input Output

 OR Gate (switches in parallel)

𝑎

𝑎⋅1

𝑏 + 𝑓 =𝑎+𝑏
if and only if 𝑎 = 1 or 𝑏 = 1
1 𝑓 =𝑎+𝑏
𝑏⋅1

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

22 Ideal Switches (Assert High)
➢ Important points to remember

 1 means high signal or high voltage.

 0 means low signal or low voltage.
 No direct relationship between input and output when
switches are in open state
 Have we achieved the goal of logic gates ?
 The output appears to be in logic 0 state but in real
case it is undefined state.

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

23 Ideal Switches (Assert Low)
➢ Logic Gates

 NOR gate
𝑎 𝑏

1 ℎ = 𝑎ത ⋅ 𝑏ത = 𝑎 + 𝑏
Input 𝑎ത ⋅ 1 𝑎ത ⋅ 1 ⋅ 𝑏ത Output

 NAND gate
𝑎

𝑎ത ⋅ 1

𝑏 +

1 𝑗 = 𝑎ത + 𝑏ത = 𝑎 ⋅ 𝑏
𝑏ത ⋅ 1

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

24 Ideal Switches
➢ Logic Gates
 NOT gate

𝑎ത ⋅ 1
1

Inputs 𝑎 + 𝑦 = 𝑎ത ⋅ 1 + 𝑎 ⋅ 0 = 𝑎ത
Output
0
𝑎⋅0

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi

25 Ideal Switches
➢ Important points to remember

 Using switches with opposite characteristics allows us

to build a network with well defined results.
 Multiplexer based designs.

COMSATS University Islamabad Dr. Sohaib Ayyaz Qazi