'Roll Number:

Thapar University, Patiala

Department of Computer Science and Engineering
END SEMESTER EXAMINATION
B. E. (Third Year): Semester-VI
(COE/CAG/CML/SEM) Course Code: UCS614
May 08, 2017 Course Name: Embedded Sys ems Design
Monday, 14.00 —17.00 Hrs
Time: 3 Hours, M. Marks: 100
Name of Faculty: AA, ASG, S, SR
Note: Attempt all parts of one question at one place.
Assume missing data, if any, uitably.

Q.1 (a) What is Embedded System? Discuss the general characteristics and significanc of Embedded [5]
Systems.

Q.1(b) List the names of five serial ADCs and discuss the data interface of each of them.
[5]
Q.2 (a) Why are mobile cells found to be hexagonal? Explain.
[2]
Q.2(b) Write short notes on following topics.
i) Robotic Soccer [8]
ii) Humanoid robots and their future
iii) Industrial robots
iv) Robots for military applications
Q.3(a) Consider the following C function to convert a decimal number to binary number. Id
tify and w
the line nuiabers having errors and also write the correct function code after removin the errors. rite [5]
1. long ttecimalToBinary . (long n)
2.
3. int remainder;
4. long binary =0, i = 0;
5. while(n != 0)
6. remainder = n%2;
7. n = n%2;
8. binary= binary + (remainder*i);
9. i = i*100; }
10. return remainder;
11. }

What will be the output of the rectified function code for n=208?

Q.3(b) Differentiate between packed BCD and unpacked BCD representation. Convert the de imal numbers [5
45 and 27 into packed BCD representation and perform their addition. ]

Q.4(a) Write the full forms of the following

i) EEPROM ii) ASIP [3]
iii)DDR
Q.4(b) Write the name of the following
1. [5]
This type of memory uses capacitoFi for storing bits in the form of charge.
2.
It is a signal to the processor emitted by hardware or software indicating.an event • at needs
immediate attention
3.
A type of memory in which memory cell is made from floating gate MOSFETS.
4. Memo, y which is used as On chip RAM in MCUs
5. A
that detects and responds to some type of input from the physical environment.
Q.4(c) Draw a neat and clean internal diagram of a DRAM chip.
[2]

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Q.5(a) State whether the following statements are TRUE or FALSE. Justify your answer. [6]
1. A hard real-time application consists of only hard real-time tasks.
2. Every safety-critical real-time system contains a fail-safe state.
3. A good lalgoritlun for scheduling of hard real-time tasks tries to complete each task in the
shortest possible time.
4. Soft real4time tasks do not have any associated time bounds.
5. For a non pre-emptive operating system, RMA is an optimal static priority scheduling algorithm
I
for a set of piiddic real-time tasks. — -
6. The upper bound on achievable utilization improves as the number of tasks in the system being
developal increases when Rate Monotonic (RM) Algorithm is used for scheduling a set of hard
real-timeiperiodic tasks.
Q.5(b) Differentiate between (with reference to Real Time tasks):
[3]
i) Tardiness and Laxity
ii) Hard Real-time Task and Finn Real-time Task
iii) Aperiodic Tasks and Sporadic Tasks
Q.5(c) For the task it given in following table, what is the CPU utilization? Is it schedulable using [11]
i) Rate Monotonic (RM) algorithm
ii) Earliest Deadline First algorithm
Show the Ga*tt charts if it is schedulable.
Tasks Period CPU Burst
T1 8 1
! T2 1 0 2
I T3 15 3
T4 24 4
T5 12 3
Q.6(a) How does thel Super Harvard architecture contribute to increased memory bandwidth?
[3]
Q.6(b) "Many DSP processors boast of Zero-overhead Loops". What do you mean by this? [2]
Q.6(c) Discuss four characteristics of Very Long Instruction Word (VLIW) architecture used in DSP [5]
processors. Distinguish between VLIW and superscalar architectures.
Q.7(a) Compare anti-fuse and SRAM FPGA in terms of performance. [2]
Q.7(b) Distinguish between simulation and synthesis with example. [4]
Q.7(c) What is the significance of HDL and FILL is ASIC design. [4]
Q.8(a) Why are FSI s popular in Embedded Systems Design? Draw and explain an FSM for a traffic [2+4]
signalling sysiem.
Q.8(b) Draw a data4v graph of the following: [2+2]
i) START:
if {caiel } {outcomel }
else i {case2} {outcome2}
else { utcome3}
END:

ii) ax2+bxle=z
Q.9(a) Address the Salability and Security/Privacy issues associated with IoT. [5]
Q.9(b) What is the difference between Web of Things and Internet of Things? Why does IoT require stable [5]
and scalable rtriddleware solulons? Explain the working principle of middleware solution.

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