8086 Interrupts

Harpreet Singh
Lecturer
CSED
TIET
PRESENTED BY: HARPREET SINGH 1
 Interrupts

• Interrupt Types
– Hardware Interrupts: External event
– Software Interrupts: Internal event (Software generated)
– Maskable and non-maskable interrupts
– Interrupt priority
• Interrupt Vectors and Interrupt Handlers
• Interrupt Controllers

PRESENTED BY: HARPREET SINGH 2

 The Purpose of Interrupts
• Interrupts are useful when interfacing I/O devices with low data-
transfer rates, like a keyboard or a mouse.
• The peripheral interrupts the normal application execution,
requesting to send or receive data.
• The processor jumps to a special program called Interrupt Service
Routine to service the peripheral
• After the processor services the peripheral, the execution of the
interrupted program continues.

Main Program Main Program Main Program Main Program

Printer Interrupt Modem Interrupt Modem Interrupt

PRESENTED BY: HARPREET SINGH 3

 BASIC INTERRUPT TERMINOLOGY
• Interrupt pins: Set of pins used in hardware interrupts
• Interrupt Service Routine (ISR) or Interrupt handler: code used for handling a specific
interrupt
• Interrupt priority: In systems with more than one interrupt inputs, some interrupts have a
higher priority than other
– They are serviced first if multiple interrupts are triggered simultaneously
• Interrupt vector: Code loaded on the bus by the interrupting device that contains the
Address (segment and offset) of specific interrupt service routine
• Interrupt Masking: Ignoring (disabling) an interrupt
• Non-Maskable Interrupt: Interrupt that cannot be ignored (power-down)

PRESENTED BY: HARPREET SINGH 4

 CAUSES OF INTERRUPT
• External devices(H/w interrupt).
• Internal abnormal conditions
-- overflow
-- / by 0.
• By inserting INT instruction by programmer(at the desired pt. in program)(S/W int.).

PRESENTED BY: HARPREET SINGH 5

Interrupt processing flow
Main program

Interrupt N
Req

Accept N
Interrupt

Get interrupt
vector

Jump to ISR
Save PC

Load PC

PRESENTED BY: HARPREET SINGH 6

 Hardware Interrupts – Interrupt pins and timing
• x86 Interrupt Pins
– INTR: Interrupt Request. Activated by a peripheral device to interrupt the processor.
• Level triggered. Activated with a logic 1.
– /INTA: Interrupt Acknowledge. Activated by the processor to inform the interrupting device that the
interrupt request (INTR) is accepted.
• Level triggered. Activated with a logic 0.
– NMI: Non-Maskable Interrupt. Used for major system faults such as parity errors and power
failures.
• Edge triggered. Activated with a positive edge (0 to 1) transition.
• Must remain at logic 1, until it is accepted by the processor.
• Before the 0 to 1 transition, NMI must be at logic 0 for at least 2 clock cycles.
• No need for interrupt acknowledgement.

INTR

INTA΄

D7-D0 Vector

PRESENTED BY: HARPREET SINGH 7

 Interrupt Vectors
• The processor uses the interrupt vector to determine the address of the
ISR of the interrupting device.
• In the 8088/8086 processor as well as in the 80386/80486/Pentium
processors operating in Real Mode (16-bit operation), the interrupt
vector is a pointer to the Interrupt Vector Table.
– The Interrupt Vector Table occupies the address range from 00000H
to 003FFH (the first 1024 bytes in the memory map).
– Each entry in the Interrupt Vector Table is 4 bytes long:
• The first two represent the offset address and the last two the
segment address of the ISR.
– The first 5 vectors are reserved by Intel to be used by the processor.
• The vectors 5 to 255 are free to be used by the user.

PRESENTED BY: HARPREET SINGH 8

 Interrupt Masking
• Special interrupt mask bit :-The processor can inhibit certain types of interrupts by use
of a special interrupt mask bit.

• This mask bit is part of the flags/condition code register, or a special interrupt register.

• If this bit is clear, and an interrupt request occurs on the Interrupt Request input, it is
ignored.

• NMI cannot be masked

PRESENTED BY: HARPREET SINGH 9

 Interrupt Processing
• Save state
– Disable interrupts for the duration of the ISR or allow it to be interrupted too?
– Save program counter
– Save flags
– Save register values
• Jump to interrupt service routine
– Location obtained by interrupt vector
• Process interrupt
• Restore state
– Load PC, flags, registers etc.

PRESENTED BY: HARPREET SINGH 10

 Interrupt Processing on the 8086 Microprocessor
• 1. External interface sends an interrupt signal, to the Interrupt Request (INTR)
pin, (or an internal interrupt occurs.)
• 2. The CPU finishes the present instruction (for a hardware interrupt) and checks
the INTR pin.
• If IF=0 the processor ignores the interrupt, else sends Interrupt Acknowledge
(INTA) to hardware interface.
• 3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus
from the hardware interface.
• 4. The contents of the flag registers are pushed onto the stack.
• 5. Both the interrupt (IF – FR bit 9) and (TF – FR bit 8) flags are cleared. This
disables the INTR pin and the trap or single-step feature.
• 6. The contents of the code segment register (CS) are pushed onto the Stack.
• 7. The contents of the instruction pointer (IP) are pushed onto the Stack.
• 8. The interrupt vector contents are fetched, from (4 x N) and then placed into the
IP and from (4 x N +2) into the CS so that the next instruction executes at the
interrupt service procedure addressed by the interrupt vector.
• 9. While returning from the interrupt-service routine by the Interrupt Return
(IRET) instruction, the IP, CS and Flag registers are popped from the Stack and
return to their state prior to the interrupt.
PRESENTED BY: HARPREET SINGH 11
What happen when interrupt is occurred?

PRESENTED BY: HARPREET SINGH 12

 The Intel x86 Interrupt Software Instructions
• All x86 processors provide the following instructions related to interrupts:
– INT nn: Interrupt. Run the ISR pointed by vector nn.
• INT 0 is reserved for the Divide Error
• INT 1 is reserved for Single Step operation
• INT 2 is reserved for the NMI pin
• INT 3 is reserved for setting a Breakpoint
• INT 4 is reserved for Overflow (Same as the INTO (Interrupt on overflow) instruction.
– CLI: Clear Interrupt Flag. IF is set to 0, thus interrupts are disabled.
– STI: Set Interrupt Flag. IF is set to 1, thus interrupts are enabled.
– IRET: Return from interrupt. This is the last instruction in the ISR (Real Mode only). It
pops from the stack the Flag register, the IP and the CS.
• After returning from an ISR the interrupts are enabled, since the initial value of the flag
register is poped from the stack.
– IRETD: Return from interrupt. This is the last instruction in the ISR (Protected Mode
only). It pops from the stack the Flag register, the EIP and the CS.

PRESENTED BY: HARPREET SINGH 13

 Interrupts
• TYPE 0 to TYPE 4  specific interrupts

• TYPE 5 to TYPE 31(27 interrupts)  kept reserved for

other advanced microprocessors of Intel Corp.

-- However, can use by computer designers for some

special interrupts in 8086 based system.

• TYPE 32 to TYPE 255(244 interrupts)  available to

users for h/w nd s/w interrupts.
PRESENTED BY: HARPREET SINGH 14
 Interrupt Vectors
• The Interrupt Vector contains the address of the interrupt service routine
• The Interrupt Vector Table is located in the first 1024 bytes of memory at address
000000H-0003FFH.
• It contains 256 different 4-byte interrupt vectors, grouped in 18 types
– 000H: Type 0 (Divide error)
•030H: Type 12 (Stack segment
– 004H: Type 1 (Single-step) overrun)
– 008H: Type 2 (NMI) •034H: Type 13 (General
– 00CH: Type 3 (1-byte breakpoint) protection)
– 010H: Type 4 (Overflow) •038H: Type 14 (Page fault)
•03CH: Type 15 (Unassigned)
– 014H: Type 5 (BOUND)
•040H: Type 16 (Coprocessor
– 018H: Type 6 (Undefined opcode) error)
– 01CH: Type 7 (Coprocessor not available) •044H-07CH: Type 14-31
– 020H: Type 8 (Double fault) (Reserved)
– 024H: Type 9 (Coprocessor segment overrun) •080H: Type 32-255 (User)
– 028H: Type 10 (Invlid task state segment)
– 02CH: Type 11 (Segment not present)

PRESENTED BY: HARPREET SINGH 15

 Interrupt Types
• Type 0: Divide error – Division overflow or division by zero
• Type 1: Single step or Trap – After the execution of each instruction when trap flag set
• Type 2: NMI Hardware Interrupt – ‘1’ in the NMI pin
• Type 3: One-byte Interrupt – INT3 instruction (used for breakpoints)
• Type 4: Overflow – INTO instruction with an overflow flag
• Type 5: BOUND – Register contents out-of-bounds
• Type 6: Invalid Opcode – Undefined opcode occurred in program
• Type 7: Coprocessor not available – MSW indicates a coprocessor
• Type 8: Double Fault – Two separate interrupts occur during the same instruction
• Type 9: Coprocessor Segment Overrun – Coprocessor call operand exceeds FFFFH
• Type 10: Invalid Task State Segment – TSS invalid (probably not initialized)
• Type 11: Segment not present – Descriptor P bit indicates segment not present or invalid
• Type 12: Stack Segment Overrun – Stack segment not present or exceeded
• Type 13: General Protection – Protection violation in 286 (general protection fault)
• Type 14: Page Fault – 80386 and above
• Type 16: Coprocessor Error – ERROR΄ = ‘0’ (80386 and above)
• Type 17: Alignment Check – Word/Doubleword data addressed at odd location (486 and above)
• Type 18: Machine Check – Memory Management interrupt (Pentium and above)
PRESENTED BY: HARPREET SINGH 16
 Real Mode Interrupt
• When current instruction execution completes, the processor checks:
1. Instruction executions
2. Single-step
3. NMI
4. Coprocessor segment overrun
5. INTR
6. INT instruction

• When there is a pending interrupt:

1. The contents of the flag register are pushed onto the stack
2. IF and TF are cleared, disabling the INTR pin
3. CS is pushed to the stack
4. IP is pushed onto the stack
5. Interrupt Vector contents are fetched and placed into IP and CS, so the next instruction is the
Interrupt Service Routine indicated by the Interrupt Vector

PRESENTED BY: HARPREET SINGH 17

 INTR

PRESENTED BY: HARPREET SINGH 18

PRESENTED BY: HARPREET SINGH 19
 H/w Interrupts
• NMI  to handle emergency conditions.
-- eg. Used to save prog. and data in case of power
failure.
-- in case of a.c. power failure, D.C. supply can
maintained for short period,(50 ms using suitable
capacitors in filter circuits).
• This time is sufficient to save.

• Type 2 int. save program after power failure in some

RAM provided with battery backup.

PRESENTED BY: HARPREET SINGH 20

 H/w Interrupts
• INTR  maskable. Enabled ,disabled using IF.

• With receive of INTR from external device, 8086

acknowledge through INTA signal.

• It executes two consecutive interrupt acknowledgement

bus cycles.
-- first INTA signal to inform the external device to get
ready.
• Ext. deivce sends interrupt type through the low order
data lines.
PRESENTED BY: HARPREET SINGH 21
 H/w Interrupts
• INTR  Intr. Type is * by 4 to get staring add. Of
IVT.
• LOCK(low active) goes low from T2 of the first ack.
cycle until T2 of the 2nd ack. cycle.

• HOLD req. is not honoured till the end of 2nd bus cycle.

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 Thanks

PRESENTED BY: HARPREET SINGH 23