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Burn-in & Test

Socket Workshop
March 6-9, 2005
Hilton Phoenix East / Mesa Hotel
Mesa, Arizona

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 Burn-in & Test
tm
Socket Workshop Technical Program

BiTS Tutorial
Sunday 3/06/05 1:00PM

“Signal Integrity of Sockets – Simplified!”

Eric Bogatin
Chief Technical Officer
Synergetix
Signal Integrity of Sockets-Simplified Slide - 1

Signal Integrity of Sockets- Simplified!

Dr. Eric Bogatin

CTO, Synergetix
Kansas City, KS
[email protected]

2005 Burn-in and Test Socket Workshop

March 6 - 9, 2005

Burn-in & Test

Socket Workshop

© Eric Bogatin 2005 www.BeTheSignal.com

Signal Integrity of Sockets-Simplified Slide - 2

Outline

9 Who cares?
9 What’s important: signal integrity, power integrity
9 Common vocabulary
9 Insertion loss: what is and is not important?
9 Loop inductance: what is and is not important?

“It is better to uncover a little than to cover a lot”

- Francis Low

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 3

Electrical Performance in
Perspective
Constraints:
• Performance • Vendors
9 Compliance • Corporate Culture
• Compatibility: Industry, Legacy
9 Pitch
9 Cycle lifetime
9 Time between cleaning Cost:
9 Electrical $$$, TCOO,
– DC resistance Schedule, Risk
– Hi Frequency
– Signal Integrity
» Bandwidth Partitioning:
» Insertion loss • Pin electronics
» Return loss
» SPICE models
• Wiring/cabling
– Power integrity • Loadboards
» Loop inductance • Sockets

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 4

Signal Integrity and

Interconnect Design
How the electrical properties of the
interconnects screw up the beautiful,
pristine signals from the chips

Simulated with HyperLynx

Signal integrity problems occur when the

interconnects are no longer electrically transparent

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 5

Signal Integrity Problems

TERMINATIONS LINE DELAY

PARASITICS CAPACITANCE
EMISSIONS
GROUND BOUNCE
EMI/EMC LOADED LINES
ATTENUATION POWER AND
NON-MONOTONIC EDGES RETURN LOSS
GROUND DISTRIBUTION
GROUND BOUNCE CRITICAL NET
SUSCEPTABILITY
SKIN DEPTH SIGNAL INTEGRITY
LOOP INDUCTANCE LOSSY LINES IR DROP
INDUCTANCE
INSERTION LOSS RINGING RISE TIME DEGRADATION CROSSTALK
STUB LENGTHS
MODE CONVERSION RETURN CURRENT PATH
GAPS IN PLANES
IMPEDANCE DISCONTINUITIES
TRANSMISSION LINES
DELTA I NOISE REFLECTIONS
UNDERSHOOT, OVERSHOOT RC DELAY DISPERSION

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 6

Four Families of Signal Integrity

Problems
1. Signal quality of one net: reflections and
distortions from impedance discontinuities
in the signal or return path

2. Cross talk between multiple nets: mutual

C and mutual L coupling

3. Power integrity: noise in the power

distribution system (PDS): voltage drop
across impedance in the pwr/gnd
network

4. EMI from a component or the system

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 7

The Socket as a Component

• Purpose of an interconnect: “to transport a signal

from one point to another with an acceptable level of
distortion”

What’s important to know? Simulated with HyperLynx

1. Will the system work?
2. Is the socket “good enough?”
3. How do you know before you build it and test it?

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 8

Build it and Test It

• Good news:
9 Always the final test
9 100% certainty for that situation

• Bad news
9 What about the next socket?
9 What do you tell your supplier?
9 How does supplier evaluate quality?
9 If it doesn’t work, where do you look to re-design?
9 Can you afford the time for multiple iterations?

• “Build it and test it” works when the interconnects are

electrically transparent
9 Other specification methods are required for f > ~ 500 MHz
9 Everything except “build it and test it” is a compromise

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 9

2nd Best Solution

• The only way to know if the system will work before building and
testing is system level simulation with accurate component
models

Model, simulation, evaluate

Lpower

Lpower

Lpin PCB #1 Lconn Backplane Lconn PCB #2 Lpin

τ τ τ

Gate1 Zo, D Zo, D Zo, D

Clk1 Gate2

Cconn Cconn
Cpin
Cpin

model
Lgnd

simulate
Lgnd

Clk1

• Needed: an accurate model of the socket which can be used in

the SPICE level simulation:
9 SPICE model
9 Behavior model: S parameter model

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 10

3rd Best Alternative

• Specify values of model parameters
9 Z0
9 TD
9 L
9 C
9 Insertion loss
9 Return loss

• Specifications based on assumptions of the rest of the system

• Specifications are a pre-arranged compromise- sometimes based on:

9 System level simulation balancing cost-performance-constraints- (really hard!)
9 A guess
9 Because it worked in the last design
9 Enough margin for designer to sleep at night
9 Assuming performance is free
9 Incorrect assumptions
9 Information that was passed from engineer to engineer to engineer to engineer…(only
one of whom might have an idea of what they want)

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 11

Universally used metric to define

“goodness” of a socket:

-1 dB insertion loss bandwidth

• Bandwidth
• Insertion loss
• dB
• Why -1 dB
• What design features influence this performance

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 12

Is this acceptable?

Sometimes the frequency domain

offers an easier path to the answer
No new information in the frequency domain

The only reason we’d ever leave the time

domain to go to the frequency domain:
To get to the answer faster.

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 13

Two World Views

Time domain view

Frequency domain view

incident amplitude
phase
transmitted

Up to the highest sine wave frequency that is significant

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 14

Bandwidth

Bandwidth: the highest sine wave

frequency that is significant

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 15

Bandwidth and the 10-90 Rise Time

(see OLL-101 Bandwidth of Signals with SPICE)

The rule of thumb:

0.35
BW = BW = bandwidth in GHz
RT = 10%Æ 90% rise time in nsec
RT
100

10
Bandwidth (GHz)

0.1
.

0.01
0.01 0.1 1 10
10% to 90% Rise Time
(nsec)

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 16

Clock Frequency and

Bandwidth
RT≈ 7 % T (a little aggressive, i.e., conservative estimate)
0.35
Tperiod = 15 x RT RT =
BW

0.35 5 1
Tperiod = 15 ≈ Tperiod =
BW BW Fclock

If you don’t know the rise time: BW = 5 x F clock As a rough rule

of thumb

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 17

Bandwidth and Bit Rate in high

speed serial links ( > 2 Gbps)
0 1 0 1 0 1 0 1 0 1 0 1 BR = bit rate
BW = bandwidth

For most high speed serial links:

Repeat frequency = ½ x BR
(for the 1010101010 pattern)

• For the highest BR high speed

serial links:
9 signal is almost a sine wave
9 BW ~ 1st harmonic of the repeat
frequency
9 BW = ½ BR

3,125 Gbps, Altera Stratix GX driver signal,

after 42 inches on FR4 courtesy of Altera The rule of thumb: BW ~ ½ x BR

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 18

Key Assumptions

• Bandwidth is the highest sine wave frequency

component that is significant

• Bandwidth is inherently only a rough approximate

term- if an accurate frequency value is important,
can’t use the bandwidth

• If the socket meets performance spec for frequencies

up to the bandwidth, it is “good enough”

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 19

Transmitted Signals in the

Frequency Domain
What are signals in the frequency domain?

only sine waves

incident

transmitted
reflected
amplitude amplitude
phase phase

Everything you ever wanted to know about the performance of a socket is

contained in the reflected and transmitted signals

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 20

Terminology

incident

transmitted

Vtransmitted
What’s important: at each frequency
Vincident
• Also called:
9 Insertion loss
9 S21
9 Transfer function
There is a magnitude and a phase at each frequency

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 21

Most Important Caveat

Source Termination
impedance impedance
= 50 Ohms = 50 Ohms

incident

transmitted

• The source impedance and the load impedance when defining

S21 is always 50 Ohms.

• Insertion loss has significance if the end use environment is 50

Ohms

© Eric Bogatin 2005

 Signal Integrity of Sockets-Simplified Slide - 22

Good and Bad Insertion Loss

1.0
Insertion Loss (magnitude)

0.9 good
0.8
0.7
0.6
0.5
0.4 Is this good?
0.3
1.0

Insertion Loss (magnitude)

0.2
0.1
bad 0.9
0.8
0.0
0.7
0 2 4 6 8 10 12 14 16 18 20
0.6
freq, GHz 0.5
0.4
0.3
Simulated with Agilent ADS 0.2
0.1
0.0
0 2 4 6 8 10 12 14 16 18 20

freq, GHz
• Is there a difference between
9 good
9 good enough
9 better ?

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 23

Insertion Loss of the System

100% ?

Insertion 100% x 100% x 100% x 50% = 50%

losses:
100% x 90% x 90% x 50% = 40%

91% x 95% x 89% x 95% = 73%

Using magnitudes, insertion losses multiply

If we used the log of the insertion loss, we could just add

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 24

The deciBel and Powers

Formalism: log of the ratio of two powers is in Bels

0.1 watt
⎛ Pb ⎞ = 10 −1 = −10 dB
ratio[Bels ] = log⎜⎜ ⎟⎟ 1 watt
⎝ Pa ⎠
0.001 watt
10 deciBel = 1 Bels
= 10 −3 = −30 dB
1 watt

⎛ Pb ⎞
ratio[dB ] = 10 x log⎜⎜ ⎟⎟ 0.000001 watt
= 10 −6 = −60 dB
⎝ Pa ⎠ 1 watt
If we have the ratio of the powers, take the exponent of the power 10 and multiple by 10
to get the dB

If we have the number of dB, divide by 10 and put to the power of 10 and this is the ratio
of the powers
-10 dB = 0.1 -20 dB = 0.01 -40 dB = 0.01%

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 25

The deciBel and Ratio of Voltages

When using dB to measure a ratio of amplitudes, the dB ALWAYS refers to

the ratio of the powers in the wave

V
P ~ V2

⎛ Pb ⎞ ⎛ Vb2 ⎞ ⎛V ⎞ ⎛V ⎞
ratio[dB ] = 10 x log⎜⎜ ⎟⎟ = 10 x log⎜⎜ 2 ⎟⎟ = 10 x 2 x log⎜⎜ b ⎟⎟ = 20 x log⎜⎜ b ⎟⎟
⎝ Pa ⎠ ⎝ Va ⎠ ⎝ Va ⎠ ⎝ Va ⎠
⎛ Vb ⎞
ratio[dB ] = 20 x log⎜⎜ ⎟⎟ When measuring the ratio of voltages, we use a 20
⎝ Va ⎠ When measuring the ratio of powers, we use a 10

Insertion loss is the ratio of amplitudes

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 26

From deciBel to Insertion Loss magnitude

If we have the number of dB,

ratio [dB ]
⎛ Vout ⎞
1. divide by 20 ⎜⎜ ⎟⎟ = 10 20
2.
3.
put to the power of 10
this is the ratio of the amplitudes
⎝ Vin ⎠

0.1
-20 dB = _________ 0.95
-0.5 dB = ______
0.01
-40 dB = _________ -1 dB = _______
0.90
0.001
-60 dB = _________ 0.80
-2 dB = _______
-80 dB = _________
0.0001 0.70
-3 dB = _______ When dB is small,
Magnitude ~1 + dB/10
1
0 dB = __________
0.3
-10 dB = _________
-25 dB = _________
0.05

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 27

From magnitude to dB
If we have the ratio of the amplitudes,
⎛ Vout ⎞
1. Write it to the power of 10 ratio[dB ] = 20 x log⎜⎜ ⎟⎟
2. Take the exponent (or take the log of the number) ⎝ Vin ⎠
3. Multiply by 20
4. This is the dB

10% = ________
-20 dB
-40 dB
1% = _________
0.1 volt
= 10 −1 = −20 dB -60 dB
0.001 = ________
1 volt

0.01 volt -1 dB
90% = _________
= 10 −2 = −40 dB When magnitude is close to 1,
1 volt 80% = _________
-2 dB dB ~ (mag – 1) x 10
-0.2 dB
98% = _________

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 28

dB and Extreme Insertion Loss

• All the signal transmits: S21 = 1= 100 = 0 dB

9 S21 = 0 dB everything is transmitted
9 Transparent interconnect

• Very little signal transmits: S21 = 0.0001 = 10-4 = -80 dB

9 S21 = really big, negative number, no signal at the far end
9 Really poor interconnect

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 29

Insertion Loss (dB) of the System

100% ?

Insertion 0 dB + 0 dB + 0 dB + -6 dB = -6 dB
losses:
0 dB + -1 dB + -1 dB + -6 dB = -8 dB

-1 dB + -0.5 dB + -1.2 dB + -0.5 dB = -3.2 dB

If we use the log of the insertion loss (dB), we just add

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 30

What’s a good value of Insertion Loss?

• Ideal total system insertion loss budget

9 At least 70% the amplitude of the signal at 2x the signal bandwidth
9 -3 dB at 2 x BW
9 If 100 MHz clock, BW ~ 500 MHz, 2x BW = 1 GHz: -3 dB @ 1 GHz
9 If 500 MHz clock, BW ~ 2.5 GHz, 2x BW = 5 GHz: -3 dB @ 5 GHz

• Practical total system insertion loss budget

9 -3 dB at signal BW

• Typical allocation of insertion loss to the socket

9 ~ -1 dB for socket
9 ~ -1 dB for load board
9 ~ -1 dB for tower pins and cables

• In rf applications, stability of insertion loss is critical

9 ~ -1 dB for socket, at carrier frequency is also a good metric

• If insertion loss < -1 dB at the application bandwidth, is this a

guarantee system will work?

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 31

Value of -1 dB Insertion Loss

Bandwidth as a Metric
• Relative comparison
• First pass screening
• Rough, rule of thumb for usable operating frequency
• Should not be used to sign off on a design
9 too approximate
9 too much margin? Too little?
9 Too many assumptions

• Multiple approximations:
9 Bandwidth of the signal
9 Is the system a 50 Ohm system?
9 Total system budget
9 Allocation to the socket

• A better approach (and much more expensive):

9 Model and simulate

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 32

What Affects Insertion Loss of a Socket?

1. Matched Impedance
2. Controlled impedance
3. Discontinuities of load board
4. Length
5. Dielectric loss
6. Conductor loss
7. DC contact resistance

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 33

The Simplest Model of a

Transmission Line
Microstrip

A "-1" order model:

Any two conductors with length

Length

Lead frame of an IC Package

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 34

Labeling the Conductors

Signal path

GROUND
Return path

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 35

The Signal

Vsignal
V

Signal path
Vin V
Return path
GROUND

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 36

How fast does a signal move down

a line?
v

signal
ε
return

in air: v = 186,000 miles per sec v = 12 inches/nsec

12 inches 12 inches
v= n sec
= n sec
= 6 inches
n sec
4 2

© Eric Bogatin 2005

 Signal Integrity of Sockets-Simplified Slide - 37

Instantaneous Impedance

Vsignal
V

Signal path

Return path

• Signal sees an “instantaneous impedance” each step along the path

• Instantaneous impedance depends on the geometry of signal and return path
• A controlled impedance when instantaneous impedance is constant
• One impedance that characterizes the interconnect:

• Characteristic impedance

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 38

Characteristic Impedance and

Capacitance per Length
capacitance per length
decreases, the characteristic
increase h impedance increases

w = 10 mils

h = 5 mils

50 Ohm PCB cross section

the capacitance per length
increases, characteristic
increase w impedance decreases

1
Z0 ~
CL

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 39

Most Important Features of

Characteristic Impedance

• Characteristic impedance is not about the signal path

• Characteristic impedance is not about the return path
• Characteristic impedance will depend both signal and return
path, inseparably
• There is no such thing as the characteristic impedance of a
single pin
• Change the return path configuration, you change the
characteristic impedance
• (Obviously, the same goes for insertion loss!)

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 40

Fundamental Property of Signals on

Transmission Lines: Reflections

Z1 Z2
Z is instantaneous impedance

V incident V reflected V
transmitted

Vreflected Z2 − Z1 Vreflected Z2 − 50Ω

S11 = = S11 = =
Vincident Z2 + Z1 Vincident Z2 + 50Ω

1. Reflections from an open?

2. Reflections from a short?
3. Reflections from a "matched" load?

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 41

Fundamental Property of Signals on

Transmission Lines: Transmission

Z1 Z2
Vtransmitted 2 x Z2
S21 = =
Vincident Z2 + Z1
V incident V reflected V
transmitted

Vtransmitted 2 x Z2
S21 = =
Vincident Z2 + 50Ω

S21 for 50 Ohms?

S21 for 40 Ohms?

© Eric Bogatin 2005

 Signal Integrity of Sockets-Simplified Slide - 42

Insertion Loss
Magnitude
and phase
Detector

DUT Z0 = 50Ω
50Ω Z 0 = 50Ω
V
~ magnitude/
source 50Ω phase
detector

50 Ω source impedance 50 Ω input impedance

+
+
S21 ~ Z0 sinh ( γ x len)

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 43

Insertion Loss and Transmission Lines

• Depends on:
9 Change in characteristic
Vtransmitted 2 x Z2
S21 = =
impedance from 50 Ohms
9 Time Delay
9 Highest frequency Vincident Z2 + Z1

1st order approximation:

Z2 1st order:

2 x Z2 2 x 50 200 x Z2
IL = x =
50 + Z2 50 + Z2 (50 + Z 2 )2

IL1 IL2
2st order: x 2 to account for the second reflection
2 x Z2 2 x 50
IL1 = IL2 =
Z2 + 50 50 + Z2
© Eric Bogatin 2005
 Signal Integrity of Sockets-Simplified Slide - 44

Rough Estimates
0
-1 1st order
-2 2nd order Estimates
Insertion Loss (dB)

-3 Z0 Insertion Loss
-4 70 Ohms -0.5 dB
-5
-6 30 Ohms -1 dB
-7 20 Ohms -3.2 dB
-8 2nd order
-9
-10
0
0 10 20 30 40 50 60 70 80 90 100
Impedance (Ohms)

Insertion Loss, dB
-1

-2

-3
2nd order estimate: for > -1 dB insertion loss,
keep 30 Ohms < Z0 < 80 Ohms -4

-5
0 2 4 6 8 10 12 14 16 18 20

Simulated with Agilent ADS freq, GHz

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 45

Minimizing Insertion Loss Principle #1:

Match Impedance to 50 Ohms
1. Uniform impedance interconnect
2. Match socket to 50 Ohms
3. Keep: 30 Ohms < Z0 < 80 Ohms and insertion loss will never be
greater than -1 dB
0

Z0 = 80 Ohms
Insertion Loss, dB

-1
Z0 = 30 Ohms
Z0 = 20 Ohms
-2

-3

-4
Simulated with Agilent ADS
-5
0 2 4 6 8 10 12 14 16 18 20

freq, GHz

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 46

What if the Impedance is not Controlled?

0
Insertion Loss, dB

-1

-2
Total length = 0.2 inches
-3 30Ω 80Ω

-4

-5
0 2 4 6 8 10 12 14 16 18 20

freq, GHz
• Low frequency behavior is related to ~ average impedance- can be better than either one
• Highest insertion loss can be much worse than either discontinuity (> 3x)

© Eric Bogatin 2005

 Signal Integrity of Sockets-Simplified Slide - 47

Three Impedance Discontinuities

0
-1
Insertion Loss, dB

-2
-3 30Ω 80Ω

-4
Total length = 0.2 inches
-5
-6
-7 30Ω 80Ω 30Ω
-8
0 2 4 6 8 10 12 14 16 18 20

freq, GHz

• Low frequency behavior is related to ~ average impedance- can be better than either one
• Highest insertion loss can be much worse than either discontinuity (> 7x)

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 48

Minimizing Insertion Loss Principle #2:

Use a controlled impedance interconnect

• Match average impedance to 50 Ohms

• Design for controlled impedance- uniform

cross section

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 49

Time Domain Impact from C, L

Discontinuities
50 psec/div
L

20 psec RT, no discontinuity

1 pF C discontinuity Simulated with Hyperlynx

2.5 nH L discontinuity

Rise Time Degradation

10%-90% RT = 2.2 x RC = 2.2 x ½ x Z0 x C ~ Z0 x C = 50 x 1 pF ~ 50 psec

10%-90% RT = 2.2 x L/R = 2.2 x L/(2 x Z0) ~ L/Z0 = 2.5 nH/50 ~ 50 psec

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 50

Insertion Loss from Pad

Capacitance
Term C Term
Term1 C1 Term2
Num=1 C=0.5 pF Num=2
Z=50 Ohm Z=50 Ohm

0
-1
C = 0.5 pF
Insertion Loss, dB

-2
-3
-4
-5
C = 1 pF
-6
-7
-8
-9
Simulated with Agilent ADS
-10
0 2 4 6 8 10 12 14 16 18 20

freq, GHz

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 51

Impact from 0.5 pF Pads on Either Side of

50 Ohm, lossless, Ideal Socket

Z0 = 50 Ohms wo caps
Z0 = 50 Ohms w caps
0
-1

Insertion Loss, dB
-2
-3
-4
-5
-6
-7
-8
-9 Simulated with Agilent ADS
-10
0 2 4 6 8 10 12 14 16 18 20
• Pad capacitance can easily dominate freq, GHz
insertion loss measurements
• For matched socket, best performance
is with no pad capacitance

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 52

Non matched socket and 0.5 pF

Pad Capacitance

0
Insertion Loss, dB

-1
Z0 = 30 Ohms wo caps
Z0 = 80 Ohms w caps
Z0 = 50 Ohms w caps
-2 Z0 = 30 Ohms w caps

Simulated with Agilent ADS

-3
0 2 4 6 8 10 12 14 16 18 20

freq, GHz
• Lower the socket impedance, the greater the impact from pad capacitance
• An optimized socket will be degraded by pad capacitance

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 53

Uncontrolled Impedance and Pad Capacitance

0
-1
Insertion Loss, dB

-2
-3
-4
-5
-6
-7
-8
-9 Simulated with Agilent ADS
-10
0 2 4 6 8 10 12 14 16 18 20

freq, GHz

Impedance discontinuities can be disastrous

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 54

Minimizing Insertion Loss Principle #3:

Minimize Pad Stack up Capacitance

• Pad stack up capacitance on test fixture/load board can and

often does dominate insertion loss performance
• To first order, always try to minimize pad capacitance
• For best performance, optimize load board discontinuities to
compensate: requires load board-socket-package co-design
9 Use 3D full wave solver
9 Use multiple test board launch designs to optimize pad stack up
9 Change socket and compensation may be off
9 When socket is well matched, performance is all about the load board

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 55

Time Delay and Length

• Speed of signal ~ 6 inches/nsec = 150 mm/nsec in torlon, most polymers

• TD ~ Length / v = Len / 6 inches/nsec = Len x 160 psec/inch = Len x 6.7

psec/mm

• Len = 100 mils, TD = 16 psec

• Len = 3 mm, TD = 20 psec

TD ~ 160 psec/inch
TD ~ 6.7 psec/mm

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 56

Insertion Loss and TD

Insertion Loss, dB
-1

-2

-3

-4

-5

• When Len << ¼ λ 0 2 4 6 8 10 12 14 16 18 20

9 Reflections from front and back, 180 deg out of phase freq, GHz
9 No reflection Simulated with Agilent ADS
9 All transmitted waves in phase and add
9 Max transmission

• When Len = ¼ λ
9 Reflected waves from front and back add
9 Maximum reflected signal
9 Transmitted waves 180 deg out of phase
9 Minimum transmitted signal

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 57

Same Impedance, changing Time Delay

Z0 = 20 Ohms
Len = 10 mils (0.25 mm), 100 mils (2.5 mm), 500 mils (12.5 mm)

0
Insertion Loss, dB

-1

-2 If Len << ¼ λ,
-1 dB insertion loss BW will
-3 be higher

-4

Simulated with Agilent ADS

-5
0 2 4 6 8 10 12 14 16 18 20

freq, GHz

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 58

Minimizing Insertion Loss:

Principle #4

Try to keep length shorter than ¼ λ at 1 .5 Len in inches

Len << BW in GHz
the highest bandwidth BW
@ 1 GHz, ¼ λ = 1.50 inches, 38 mm 38
@ 10 GHz, ¼ λ = 150 mils, 3.8 mm
Len << Len in mm
BW in GHz
BW
@ 20 GHz, ¼ λ = 75 mils, 1.9 mm

• If worst case insertion loss is less than -1 dB, TD may not be important
• If worst case insertion loss is greater than -1 dB, keep length << ¼ λ
• Minimize insertion loss by keeping length << ¼ λ
• Shorter is better, but long may be good enough

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 59

Attenuation from Dielectric Loss

⎛ RL ⎞ GL = ω tan( δ)C
α = - 4.34⎜⎝ + G LZ 0⎟⎠ dB/length
Z0 1
Conductor Dielectric Z0 =
loss loss vel C
ω tan( δ)
GL Z 0 =
vel
Independent of geometry!

α dielectric ≈ − 2.3f tan(δ ) εeff dB/in

S21 ~ - 2.3 x 0.02 x 2 x f = - 0.1 x f dB/inch, f in GHz

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 60

Insertion Loss From Dielectric Loss

Rule of thumb: lossy materials, tan(δ) = 0.02: α ~ - 0.1 dB/inch/GHz

S21 ~ -0.1 dB/inch x f ( f in GHz)
Estimate: 0.2 inches, 10 GHz
S21 = -0.1 x 0.2 x 10 ~ -0.2 dB

0.0
-0.2
Insertion Loss, dB

-0.4
50 Ohms, tan(δ) = 0.02
-0.6
-0.8
30 Ohms, tan(δ) =0
-1.0 30 Ohms, tan(δ) = 0.02
-1.2
-1.4
-1.6
-1.8
Simulated with Agilent ADS
-2.0
0 2 4 6 8 10 12 14 16 18 20

freq, GHz

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 61

Minimizing Insertion Loss:

Principle #5

• If impedance is matched, dielectric loss is only a

problem for very long interconnects (Len > 0.5 inches)

• If impedance is not matched, dielectric loss has small

impact

• Shorter is always better, but long be good enough

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 62

Current Distributions
signal

return

• At DC, what is the current distribution?

• Current distributes to minimize the impedance
• Impedance is R + iωL
• As frequency goes up, minimizing loop L is more dominant
• To minimize loop L, two opposing forces:
9 Within each conductor, current will move as far apart as possible
(minimize partial self inductance- skin effect)

9 Signal current will move as close as possible to return current

(maximize partial mutual inductance- proximity effect)

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 63

Current Distributions Calculated

with Ansoft 2D Field Solver
Microstrip:
@ 10 MHz 50 Ohm, FR4
30µ εr = 4.2
h = 38 µ
t = 30 µ (1 oz)
w = 75 µ

Above 10 MHz, all resistance

@ 100 MHz is skin depth limited

1 1
δ= = 2µ f in GHz
σπµ0µr f f
in copper
@ 1000 MHz

Skin depth in copper ~ 2 microns @ 1 GHz

© Eric Bogatin 2005

 Signal Integrity of Sockets-Simplified Slide - 64

Conductor Loss
⎛ RL ⎞
α = - 4.34⎜⎝ + G LZ 0⎟⎠ dB/length
Z0
Conductor Dielectric
α in dB/in loss loss
f in GHz
w is perimeter in mils OD = 10 mils
Z0 in Ohms w = 3 x 10 = 30 mils

Simple first order model : S21 ~ -0.02 dB/inch @ 1 GHz

(10% the insertion loss from dielectric loss)

-22 f
α conductor ≈ dB/in @ 10 GHz, 0.1 inch long
Z0 w S21 ~ -0.02 dB/inch x 0.1 inch x 3 = ~-0.01 dB

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 65

Minimizing Insertion Loss:

Principle #6

• Current distributions above 1 GHz are all skin depth

limited

• Series resistance from skin depth has no impact on

insertion loss for most structures with OD > 1 mils

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 66

Impact from DC contact resistance

⎛ RL ⎞
α = - 4.34⎜⎝ + G LZ 0⎟⎠ dB/length S 21 ~ −4.34 x
Rdc
~−
Rdc
Z0 50 10
Conductor Dielectric
loss loss

If Rdc = 0.1 Ohms, S21 ~ -0.01 dB

If Rdc = 1 Ohms, S21 ~ -0.1 dB
0.0
-0.1
Insertion Loss, dB

-0.2
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9 Simulated with Agilent ADS
-1.0
0 2 4 6 8 10 12 14 16 18 20

freq, GHz

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 67

Minimizing Insertion Loss:

Principle #7

• If contact resistance is so large that it affects insertion

loss, you have a potential open problem, not an
insertion loss problem

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 68

7 Principles of Socket Design for

Optimized Insertion Loss

1. match characteristic impedance of socket to 50 Ohms

2. Keep the impedance constant through socket
3. Optimize (minimize) pad stack up capacitance
4. Keep socket short
5. Dielectric loss of socket not critical
6. Conductor loss of socket not critical
7. Contact resistance of socket not critical

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 69

Power Integrity

power

To
regulator Cdecoupling

ground

• Goal: keep the voltage across the power pins constant, even with
current surges
• Strategy: minimize the impedance of the power distribution
• At high frequency, Z = R + iωL
• L is the loop inductance of the power and ground return path

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 70

What is inductance?

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 71

Inductance Principles -1

wire carrying a current

1. Magnetic field lines are

around all current
carrying conductors

photo source: Halliday and Resnick, Physics, 1962

Right hand rule

What influences the number of field lines?

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 72

Counting Magnetic Field Lines

How many field lines completely surround

this section of the wire?

Current

section of wire
length, d
Right hand rule
# of field lines ~ current in the wire determines
direction

A Weber of field lines

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 73

Inductance Principles -2

2. Inductance is related to the number of field lines

around the conductor, per amp of current through it

L = # of field lines around conductor, per amp of current

Units: Webers/amp = Henry
nH more common

Many flavors of inductance:

self - mutual
loop - partial
total, net or effective

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 74

Loop Inductance

La

L meter Lab I

Second wire is return path Lb

Lloop = La + Lb − 2Lab

To reduce Lloop, what

do we want to do to:
La
Lb
Lab
How?

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 75

Four principles for minimizing

Loop Inductance

1. Short lengths
2. Wide conductors
3. Closely spaced return path
4. Multiple power-return
conductors in parallel

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 76

Estimating Loop Inductance from

Characteristic Impedance

• For any controlled impedance interconnect, by definition:

9 Lloop = TD x Z0
9 Example 1: 50 Ohms, TD ~ 20 psec, Lloop = 1 nH

• Lloop ~ 170 psec/inch x Z0 x Len = 6.8 psec/mm x Z0 x Len

• Examples:
9 Z0 = 50 Ohms, Len = 3 mm Lloop = 6.8 x 50 x 3 = 1 nH
9 Z0 = 50 Ohms, Len = 1.5 mm Lloop = 6.8 x 50 x 3 = 0.5 nH
9 Z0 = 20 Ohms, Len = 3 mm Lloop = 6.8 x 20 x 3 = 0.4 nH
9 Z0 = 50 Ohms, Len = 0.1 mm Lloop = 170 x 50 x 0.1 = 0.8 nH
9 Z0 = 70 Ohms, Len = 0.15 mm Lloop = 170 70 x 0.15 = 1.8 nH

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 77

How to minimize Loop Inductance

• How to minimize loop inductance:

9 Shorter socket
9 Lower impedance- close spacing, larger diameter pins, multiple
return paths

• Use 2D or 3D field solver to estimate loop inductance

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 78

Signal Integrity of Sockets: Topics

• What does it mean to “work”?

• Signal integrity
9 Insertion loss
9 Bandwidth
9 Characteristic impedance
9 Time delay
9 Dielectric loss
9 Conductor loss

• Power integrity
9 Loop inductance

• Other:
9 Return loss
9 Differential impedance
9 Cross talk
9 Ground bounce

© Eric Bogatin 2005

Signal Integrity of Sockets-Simplified Slide - 79

The End

Thanks for
listening!

© Eric Bogatin 2005 www.BeTheSignal.com

Signal Integrity of Sockets-Simplified Slide - 80

For More Information on Signal Integrity

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Published by Prentice Hall, 2004

© Eric Bogatin 2005