Am29F010B

1 Megabit (128 K x 8-bit)

CMOS 5.0 Volt-only, Uniform Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation ■ Embedded Algorithms
— 5.0 V ± 10% for read, erase, and program operations — Embedded Erase algorithm automatically
— Simplifies system-level power requirements pre-programs and erases the chip or any
combination of designated sector
■ Manufactured on 0.32 µm process technology
— Embedded Program algorithm automatically
— Compatible with Am29F010 and Am29F010A
programs and verifies data at specified address
device
■ Erase Suspend/Resume
■ High performance
— Supports reading data from a sector not
— 45 ns maximum access time
being erased
■ Low power consumption ■ Minimum 1 million erase cycles guaranteed per
— 12 mA typical active read current sector
— 30 mA typical program/erase current ■ 20-year data retention at 125°C
— <1 µA typical standby current — Reliable operation for the life of the system
■ Flexible sector architecture ■ Package options
— Eight 16 Kbyte sectors — 32-pin PLCC
— Any combination of sectors can be erased — 32-pin TSOP
— Supports full chip erase — 32-pin PDIP

■ Sector protection ■ Compatible with JEDEC standards

— Hardware-based feature that disables/re- — Pinout and software compatible with
enables program and erase operations in any single-power-supply flash
combination of sectors — Superior inadvertent write protection
— Sector protection/unprotection can be ■ Data# Polling and Toggle Bits
implemented using standard PROM
— Provides a software method of detecting
programming equipment
program or erase cycle completion

This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Publication# 22336 Rev: C Amendment/0
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Issue Date: November 28, 2000
GENERAL DESCRIPTION
The Am29F010B is a 1 Mbit, 5.0 Volt-only Flash automatically times the program pulse widths and
memory organized as 131,072 bytes. The Am29F010B verifies proper cell margin.
is offered in 32-pin PDIP, PLCC and TSOP packages.
Device erasure occurs by executing the erase com-
The byte-wide data appears on DQ0-DQ7. The de-
mand sequence. This invokes the Embedded Erase
vice is designed to be programmed in-system with the
algorithm—an internal algorithm that automatically
standard system 5.0 Volt VCC supply. A 12.0 volt VPP is not
preprograms the array (if it is not already programmed)
required for program or erase operations. The device can
before executing the erase operation. During erase, the
also be programmed or erased in standard EPROM
device automatically times the erase pulse widths and
programmers.
verifies proper cell margin.
This device is manufactured using AMD’s 0.32 µm pro-
The host system can detect whether a program or
cess technology, and offers all the features and benefits
erase operation is complete by reading the DQ7 (Data#
of the Am29F010 and Am29F010A.
Polling) and DQ6 (toggle) status bits. After a program
The standard device offers access times of 45, 55, 70, or erase cycle has been completed, the device is ready
90, and 120 ns, allowing high-speed microprocessors to read array data or accept another command.
to operate without wait states. To eliminate bus conten-
The sector erase architecture allows memory sectors
tion the device has separate chip enable (CE#), write
to be erased and reprogrammed without affecting the
enable (WE#) and output enable (OE#) controls.
data contents of other sectors. The device is erased
The device requires only a single 5.0 volt power sup- when shipped from the factory.
ply for both read and write functions. Internally
The hardware data protection measures include a
generated and regulated voltages are provided for the
low VCC detector automatically inhibits write operations
program and erase operations.
during power transitions. The hardware sector protec-
The device is entirely command set compatible with the tion feature disables both program and erase operations
JEDEC single-power-supply Flash standard. Com- in any combination of the sectors of memory, and is im-
mands are written to the command register using plemented using standard EPROM programmers.
standard microprocessor write timings. Register con-
The system can place the device into the standby mode.
tents serve as input to an internal state machine that
Power consumption is greatly reduced in this mode.
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed AMD’s Flash technology combines years of Flash
for the programming and erase operations. Reading memory manufacturing experience to produce the
data out of the device is similar to reading from other h i g h e s t l eve l s o f q u a l i t y, r e l i a b i l i t y, a n d c o s t
Flash or EPROM devices. effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
Device programming occurs by executing the program
tunneling. The bytes are programmed one byte at a
command sequence. This invokes the Embedded Pro-
time using the EPROM programming mechanism of hot
gram algorithm—an inter nal algorithm that
electron injection.

2 Am29F010B
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 DQ5: Exceeded Timing Limits ................................................ 17
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 DQ3: Sector Erase Timer ....................................................... 18
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Table 5. Write Operation Status ..................................................... 18
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 19
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 5. Maximum Negative Overshoot Waveform ...................... 19
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 6. Maximum Positive Overshoot Waveform ........................ 19
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 1. Am29F010B Device Bus Operations .................................9 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 20
Requirements for Reading Array Data ..................................... 9 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Writing Commands/Command Sequences .............................. 9 Figure 7. Test Setup ....................................................................... 22
Program and Erase Operation Status .................................... 10 Table 6. Test Specifications ........................................................... 22
Standby Mode ........................................................................ 10 Key to Switching Waveforms . . . . . . . . . . . . . . . 22
Output Disable Mode .............................................................. 10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 2. Am29F010B Sector Addresses Table ...............................10 Figure 8. Read Operations Timings ............................................... 23
Erase and Program Operations ......................................................... 24
Autoselect Mode ..................................................................... 10
Figure 9. Program Operation Timings ............................................ 25
Table 3. Am29F010B Autoselect Codes (High Voltage Method) ....11
Figure 10. Chip/Sector Erase Operation Timings .......................... 25
Sector Protection/Unprotection ............................................... 11
Figure 11. Data# Polling Timings (During Embedded Algorithms) . 26
Hardware Data Protection ...................................................... 11 Figure 12. Toggle Bit Timings (During Embedded Algorithms) ...... 26
Low VCC Write Inhibit ......................................................................11 Erase and Program Operations ......................................................... 27
Write Pulse “Glitch” Protection ........................................................11 Alternate CE# Controlled Writes .................................................... 27
Logical Inhibit ..................................................................................11 Figure 13. Alternate CE# Controlled Write Operation Timings ...... 28
Power-Up Write Inhibit ....................................................................11
Erase and Programming Performance . . . . . . . 28
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 12
Latchup Characteristic . . . . . . . . . . . . . . . . . . . . 29
Reading Array Data ................................................................ 12
TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . 29
Reset Command ..................................................................... 12
PLCC and PDIP Pin Capacitance . . . . . . . . . . . . 29
Autoselect Command Sequence ............................................ 12
Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Byte Program Command Sequence ....................................... 12
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 30
Figure 1. Program Operation ..........................................................13
PD 032—32-Pin Plastic DIP ................................................... 30
Chip Erase Command Sequence ........................................... 13
PL 032—32-Pin Plastic Leaded Chip Carrier ......................... 31
Sector Erase Command Sequence ........................................ 13
TS 032—32-Pin Standard Thin Small Outline Package ......... 32
Erase Suspend/Erase Resume Commands ........................... 14
TSR 032—32-Pin Standard Thin Small Outline Package ....... 33
Figure 2. Erase Operation ...............................................................14
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 34
Command Definitions ............................................................. 15
Table 4. Am29F010B Command Definitions ...................................15 Revision A (August 12, 1999) ................................................. 34
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 16 Revision A+1 (September 22, 1999) ...................................... 34
DQ7: Data# Polling ................................................................. 16 Revision A+2 (September 27, 1999) ...................................... 34
Figure 3. Data# Polling Algorithm ...................................................16 Revision B (November 12, 1999) ............................................ 34
DQ6: Toggle Bit I .................................................................... 16 Revision C (November 28, 2000) ........................................... 34
Reading Toggle Bit DQ6 ......................................................... 17
Figure 4. Toggle Bit Algorithm .........................................................17

Am29F010B 3
PRODUCT SELECTOR GUIDE
Family Part Number Am29F010B

VCC = 5.0 V ± 5% -45

Speed Option
VCC = 5.0 V ± 10% -55 -70 -90 -120

Max Access Time (ns) 45 55 70 90 120

CE# Access (ns) 45 55 70 90 120

OE# Access (ns) 25 30 30 35 50

Note: See the AC Characteristics section for full specifications.

BLOCK DIAGRAM

DQ0–DQ7

VCC
Erase Voltage Input/Output
VSS Generator Buffers

WE# State
Control

Command
Register
PGM Voltage
Generator
Chip Enable Data
Output Enable STB Latch
CE#
Logic
OE#

Y-Decoder Y-Gating
STB
Address Latch

VCC Detector Timer

X-Decoder Cell Matrix

A0–A16

4 Am29F010B
CONNECTION DIAGRAMS

NC 1 32 VCC

WE#
A16

VCC
A12
A15

NC

NC
A16 2 31 WE#
A15 3 30 NC
4 3 2 1 32 31 30
A12 4 29 A14 A7 5 29 A14
A7 5 28 A13 A6 6 28 A13
A6 6 27 A8 A5 7 A8
27
A5 7 26 A9 A4 8 26 A9
PLCC
A4 8 PDIP 25 A11 A3 9 25 A11
A3 9 24 OE# A2 10 24 OE#
A2 10 23 A10 A1 11 23 A10
A1 11 22 CE# A0 12 22 CE#
DQ0 13 21 DQ7
A0 12 21 DQ7
DQ0 14 15 16 17 18 19 20
13 20 DQ6

VSS
DQ1
DQ2

DQ3
DQ4
DQ5
DQ6
DQ1 14 19 DQ5
DQ2 15 18 DQ4
VSS 16 17 DQ3

Am29F010B 5
CONNECTION DIAGRAMS

A11 1 32 OE#
A9 2 31 A10
A8 3 30 CE#
A13 4 29 DQ7
A14 5 28 DQ6
NC 6 27 DQ5
WE# 7 26 DQ4
VCC 8 Standard TSOP 25 DQ3
NC 9 24 VSS
A16 10 23 DQ2
A15 11 22 DQ1
A12 12 21 DQ0
A7 13 20 A0
A6 14 19 A1
A5 15 18 A2
A4 16 17 A3

OE# 1 32 A11
A10 2 31 A9
CE# 3 30 A8
DQ7 4 29 A13
DQ6 5 28 A14
DQ5 6 27 NC
DQ4 7 26 WE#
DQ3 8 25 VCC
VSS 9 Reverse TSOP 24 NC
DQ2 10 23 A16
DQ1 11 22 A15
DQ0 12 21 A12
A0 13 20 A7
A1 14 19 A6
A2 15 18 A5
A3 16 17 A4

6 Am29F010B
PIN CONFIGURATION LOGIC SYMBOL
A0–A16 = 17 Addresses
DQ0–DQ7 = 8 Data Inputs/Outputs
17
CE# = Chip Enable A0–A16 8
OE# = Output Enable
DQ0–DQ7
WE# = Write Enable CE#
VCC = +5.0 Volt Single Power Supply
OE#
(See Product Selector Guide for speed
options and voltage supply tolerances) WE#

VSS = Device Ground

NC = Pin Not Connected Internally

Am29F010B 7
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed
by a combination of the elements below.

Am29F010B 70 E C

TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)

PACKAGE TYPE
P = 32-Pin Plastic PDIP (PD 032)
J = 32-Pin Rectangular Plastic Leaded Chip Carrier (PL 032)
E = 32-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 032)
F = 32-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR032)

SPEED OPTION
See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION
Am29F010B
1 Megabit (128 K x 8-Bit) CMOS Flash Memory
5.0 Volt-only Read, Program, and Erase

Valid Combinations VCC Voltage Valid Combinations

Valid Combinations list configurations planned to be sup-
Am29F010B-45 5.0 V ± 5% ported in volume for this device. Consult the local AMD sales
Am29F010B-55 PC, PI, PE, office to confirm availability of specific valid combinations and
JC, JI, JE, to check on newly released combinations.
Am29F010B-70 EC, EI, EE, 5.0 V ± 10%
Am29F010B-90 FC, FI, FE
Am29F010B-120

8 Am29F010B
DEVICE BUS OPERATIONS
This section describes the requirements and use of the of the register serve as inputs to the internal state ma-
device bus operations, which are initiated through the chine. The state machine outputs dictate the function of
internal command register. The command register it- the device. The appropriate device bus operations
self does not occupy any addressable memor y table lists the inputs and control levels required, and the
location. The register is composed of latches that store resulting output. The following subsections describe
the commands, along with the address and data infor- each of these operations in further detail.
mation needed to execute the command. The contents

Table 1. Am29F010B Device Bus Operations

Addresses
Operation CE# OE# WE# (Note 1) DQ0–DQ7

Read L L H AIN DOUT

Write L H L AIN DIN

Standby VCC ± 0.5 V X X X High-Z

Output Disable L H H X High-Z

Hardware Reset X X X X High-Z

Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5 V, X = Don’t Care, AIN = Addresses In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A16:A0.
2. The sector protect and sector unprotect functions must be implemented via programming equipment. See the “Sector Pro-
tection/Unprotection” section.

Requirements for Reading Array Data Writing Commands/Command Sequences

To read array data from the outputs, the system must To write a command or command sequence (which in-
drive the CE# and OE# pins to VIL. CE# is the power cludes programming data to the device and erasing
control and selects the device. OE# is the output con- sectors of memory), the system must drive WE# and
trol and gates array data to the output pins. WE# should CE# to VIL, and OE# to VIH.
remain at VIH.
An erase operation can erase one sector, multiple sec-
The internal state machine is set for reading array data tors, or the entire device. The Sector Address Tables
upon device power-up, or after a hardware reset. This indicate the address space that each sector occupies.
ensures that no spurious alteration of the memory con- A “sector address” consists of the address bits required
tent occurs during the power transition. No command is to uniquely select a sector. See the “Command Defini-
necessary in this mode to obtain array data. Standard tions” section for details on erasing a sector or the
microprocessor read cycles that assert valid addresses entire chip.
on the device address inputs produce valid data on the
After the system writes the autoselect command se-
device data outputs. The device remains enabled for
quence, the device enters the autoselect mode. The
read access until the command register contents are
system can then read autoselect codes from the inter-
altered.
nal register (which is separate from the memory array)
See “Reading Array Data” for more information. Refer on DQ7–DQ0. Standard read cycle timings apply in this
to the AC Read Operations table for timing specifica- mode. Refer to the “Autoselect Mode” and “Autoselect
tions and to the Read Operations Timings diagram for Command Sequence” sections for more information.
the timing waveforms. ICC1 in the DC Characteristics
ICC2 in the DC Characteristics table represents the ac-
table represents the active current specification for
tive current specification for the write mode. The “AC
reading array data.
Characteristics” section contains timing specification
tables and timing diagrams for write operations.

Am29F010B 9
Program and Erase Operation Status The device enters the CMOS standby mode when the
CE# pin is held at VCC ± 0.5 V. (Note that this is a more
During an erase or program operation, the system may
restricted voltage range than VIH.) The device enters
check the status of the operation by reading the status
the TTL standby mode when CE# is held at VIH. The
bits on DQ7–DQ0. Standard read cycle timings and ICC
device requires the standard access time (tCE) before it
read specifications apply. Refer to “Write Operation
is ready to read data.
Status” for more information, and to each AC Charac-
teristics section in the appropriate data sheet for timing If the device is deselected during erasure or program-
diagrams. ming, the device draws active current until the
operation is completed.
Standby Mode
ICC3 in the DC Characteristics tables represents the
When the system is not reading or writing to the device, standby current specification.
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the Output Disable Mode
outputs are placed in the high impedance state, inde-
When the OE# input is at VIH, output from the device is
pendent of the OE# input.
disabled. The output pins are placed in the high imped-
ance state.

Table 2. Am29F010B Sector Addresses Table

Sector A16 A15 A14 Address Range

SA0 0 0 0 00000h-03FFFh

SA1 0 0 1 04000h-07FFFh

SA2 0 1 0 08000h-0BFFFh

SA3 0 1 1 0C000h-0FFFFh

SA4 1 0 0 10000h-13FFFh

SA5 1 0 1 14000h-17FFFh

SA6 1 1 0 18000h-1BFFFh

SA7 1 1 1 1C000h-1FFFFh

Note: All sectors are 16 Kbytes in size.

Autoselect Mode
The autoselect mode provides manufacturer and de- the appropriate highest order address bits. Refer to the
vice identification, and sector protection verification, corresponding Sector Address Tables. The Command
through identifier codes output on DQ7–DQ0. This Definitions table shows the remaining address bits that
mode is primarily intended for programming equipment are don’t care. When all necessary bits have been set
to automatically match a device to be programmed with as required, the programming equipment may then
its corresponding programming algorithm. However, read the corresponding identifier code on DQ7–DQ0.
the autoselect codes can also be accessed in-system
To access the autoselect codes in-system, the host
through the command register.
system can issue the autoselect command via the
When using programming equipment, the autoselect command register, as shown in the Command Defini-
mode requires VID on address pin A9. Address pins A6, tions table. This method does not require VID. See
A1, and A0 must be as shown in Autoselect Codes “Command Definitions” for details on using the autose-
(High Voltage Method) table. In addition, when verifying lect mode.
sector protection, the sector address must appear on

10 Am29F010B
 Table 3. Am29F010B Autoselect Codes (High Voltage Method)
A16 A13 A8 A5 DQ7
to to to to to
Description CE# OE# WE# A14 A10 A9 A7 A6 A2 A1 A0 DQ0

Manufacturer ID: AMD L L H X X VID X L X L L 01h

Device ID: Am29F010B L L H X X VID X L X L H 20h

01h
(protected)
Sector Protection Verification L L H SA X VID X L X H L
00h
(unprotected)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection gramming, which might otherwise be caused by

spurious system level signals during VCC power-up and
The hardware sector protection feature disables both
power-down transitions, or from system noise.
program and erase operations in any sector. The hard-
ware sector unprotection feature re-enables both Low VCC Write Inhibit
program and erase operations in previously protected When VCC is less than VLKO, the device does not ac-
sectors. cept any write cycles. This protects data during VCC
Sector protection/unprotection must be implemented power-up and power-down. The command register and
using programming equipment. The procedure re- all internal program/erase circuits are disabled, and the
quires a high voltage (VID) on address pin A9 and the device resets. Subsequent writes are ignored until VCC
control pins. Details on this method are provided in a is greater than VLKO. The system must provide the
supplement, publication number 22337. Contact an proper signals to the control pins to prevent uninten-
AMD representative to obtain a copy of the appropriate tional writes when VCC is greater than VLKO.
document. Write Pulse “Glitch” Protection
The device is shipped with all sectors unprotected. Noise pulses of less than 5 ns (typical) on OE#, CE# or
AMD offers the option of programming and protecting WE# do not initiate a write cycle.
sectors at its factory prior to shipping the device
through AMD’s ExpressFlash™ Service. Contact an Logical Inhibit
AMD representative for details. Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
It is possible to determine whether a sector is protected
CE# and WE# must be a logical zero while OE# is a
or unprotected. See “Autoselect Mode” for details.
logical one.
Hardware Data Protection Power-Up Write Inhibit
The command sequence requirement of unlock cycles If WE# = CE# = VIL and OE# = VIH during power up, the
for programming or erasing provides data protection device does not accept commands on the rising edge
against inadvertent writes (refer to the Command Defi- of WE#. The internal state machine is automatically
nitions table). In addition, the following hardware data reset to reading array data on power-up.
protection measures prevent accidental erasure or pro-

Am29F010B 11
COMMAND DEFINITIONS
Writing specific address and data commands or se- Autoselect Command Sequence
quences into the command register initiates device
The autoselect command sequence allows the host
operations. The Command Definitions table defines the
system to access the manufacturer and devices codes,
valid register command sequences. Writing incorrect
and determine whether or not a sector is protected.
address and data values or writing them in the im-
The Command Definitions table shows the address
proper sequence resets the device to reading array
and data requirements. This method is an alternative to
data.
that shown in the Autoselect Codes (High Voltage
All addresses are latched on the falling edge of WE# or Method) table, which is intended for PROM program-
CE#, whichever happens later. All data is latched on mers and requires VID on address bit A9.
the rising edge of WE# or CE#, whichever happens
The autoselect command sequence is initiated by writ-
first. Refer to the appropriate timing diagrams in the
ing two unlock cycles, followed by the autoselect
“AC Characteristics” section.
command. The device then enters the autoselect
mode, and the system may read at any address any
Reading Array Data
number of times, without initiating another command
The device is automatically set to reading array data sequence.
after device power-up. No commands are required to
retrieve data. The device is also ready to read array A read cycle at address XX00h or retrieves the manu-
data after completing an Embedded Program or Em- facturer code. A read cycle at address XX01h returns
bedded Erase algorithm. the device code. A read cycle containing a sector ad-
dress (SA) and the address 02h in returns 01h if that
The system must issue the reset command to re-en- sector is protected, or 00h if it is unprotected. Refer to
able the device for reading array data if DQ5 goes high, the Sector Address tables for valid sector addresses.
or while in the autoselect mode. See the “Reset Com-
mand” section, next. The system must write the reset command to exit the
autoselect mode and return to reading array data.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information. Byte Program Command Sequence
The Read Operations table provides the read parame-
Programming is a four-bus-cycle operation. The pro-
ters, and Read Operation Timings diagram shows the
gram command sequence is initiated by writing two
timing diagram.
unlock write cycles, followed by the program set-up
command. The program address and data are written
Reset Command
next, which in turn initiate the Embedded Program al-
Writing the reset command to the device resets the de- gorithm. The system is not required to provide further
vice to reading array data. Address bits are don’t care controls or timings. The device automatically provides
for this command. internally generated program pulses and verify the pro-
The reset command may be written between the se- grammed cell margin. The Command Definitions take
quence cycles in an erase command sequence before shows the address and data requirements for the byte
erasing begins. This resets the device to reading array program command sequence.
data. Once erasure begins, however, the device ig- When the Embedded Program algorithm is complete,
nores reset commands until the operation is complete. the device then returns to reading array data and ad-
The reset command may be written between the se- dresses are no longer latched. The system can
quence cycles in a program command sequence determine the status of the program operation by using
before programming begins. This resets the device to DQ7or DQ6. See “Write Operation Status” for informa-
reading array data. Once programming begins, how- tion on these status bits.
ever, the device ignores reset commands until the Any commands written to the device during the Em-
operation is complete. bedded Program Algorithm are ignored.
The reset command may be written between the se- Programming is allowed in any sequence and across
quence cycles in an autoselect command sequence. sector boundaries. A bit cannot be programmed
Once in the autoselect mode, the reset command must from a “0” back to a “1”. Attempting to do so may halt
be written to return to reading array data. the operation and set DQ5 to “1”, or cause the Data#
If DQ5 goes high during a program or erase operation, Polling algorithm to indicate the operation was suc-
writing the reset command returns the device to read- cessful. However, a succeeding read will show that the
ing array data. data is still “0”. Only erase operations can convert a “0”
to a “1”.

12 Am29F010B
 Embedded Erase algorithm is complete, the device re-
turns to reading array data and addresses are no
START longer latched.
Figure 2 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristics” for parameters, and to the Chip/Sector
Write Program
Command Sequence
Erase Operation Timings for timing waveforms.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector
Data Poll
from System erase command sequence is initiated by writing two un-
Embedded lock cycles, followed by a set-up command. Two
Program additional unlock write cycles are then followed by the
algorithm
address of the sector to be erased, and the sector
in progress
erase command. The Command Definitions table
Verify Data? shows the address and data requirements for the sec-
No
tor erase command sequence.

Yes The device does not require the system to preprogram

the memory prior to erase. The Embedded Erase algo-
rithm automatically programs and verifies the sector for
No an all zero data pattern prior to electrical erase. The
Increment Address Last Address?
system is not required to provide any controls or tim-
ings during these operations.
Yes
After the command sequence is written, a sector erase
Programming time-out of 50 µs begins. During the time-out period,
Completed additional sector addresses and sector erase com-
mands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of sec-
Note: See the appropriate Command Definitions table for tors may be from one sector to all sectors. The time
program command sequence. between these additional cycles must be less than 50
µs, otherwise the last address and command might not
Figure 1. Program Operation be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The in-
terrupts can be re-enabled after the last Sector Erase
Chip Erase Command Sequence command is written. If the time between additional sec-
Chip erase is a six-bus-cycle operation. The chip erase tor erase commands can be assumed to be less than
command sequence is initiated by writing two unlock 50 µs, the system need not monitor DQ3. Any com-
cycles, followed by a set-up command. Two additional mand during the time-out period resets the device
unlock write cycles are then followed by the chip erase to reading array data. The system must rewrite the
command, which in turn invokes the Embedded Erase command sequence and any additional sector ad-
algorithm. The device does not require the system to dresses and commands.
preprogram prior to erase. The Embedded Erase algo- The system can monitor DQ3 to determine if the sector
rithm automatically preprograms and verifies the entire erase timer has timed out. (See the “DQ3: Sector Erase
memory for an all zero data pattern prior to electrical Timer” section.) The time-out begins from the rising
erase. The system is not required to provide any con- edge of the final WE# pulse in the command sequence.
trols or timings during these operations. The Command
Definitions table shows the address and data require- Once the sector erase operation has begun, all other
ments for the chip erase command sequence. commands are ignored.

Any commands written to the chip during the Embed- When the Embedded Erase algorithm is complete, the
ded Erase algorithm are ignored. device returns to reading array data and addresses are
no longer latched. The system can determine the sta-
The system can determine the status of the erase op- tus of the erase operation by using DQ7 or DQ6. Refer
eration by using DQ7 or DQ6. See “Write Operation to “Write Operation Status” for information on these
Status” for information on these status bits. When the status bits.

Am29F010B 13
Figure 2 illustrates the algorithm for the erase opera- mode. The device allows reading autoselect codes
tion. Refer to the Erase/Program Operations tables in even at addresses within erasing sectors, since the
the “AC Characteristics” section for parameters, and to codes are not stored in the memory array. When the
the Sector Erase Operations Timing diagram for timing device exits the autoselect mode, the device reverts to
waveforms. the Erase Suspend mode, and is ready for another
valid operation. See “Autoselect Command Sequence”
Erase Suspend/Erase Resume Commands for more information.
The Erase Suspend command allows the system to in- The system must write the Erase Resume command
terrupt a sector erase operation and then read data (address bits are “don’t care”) to exit the erase suspend
from, or program data to, any sector not selected for mode and continue the sector erase operation. Further
erasure. This command is valid only during the sector writes of the Resume command are ignored. Another
erase operation, including the 50 µs time-out period Erase Suspend command can be written after the de-
during the sector erase command sequence. The vice has resumed erasing.
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
dresses are “don’t-cares” when writing the Erase START
Suspend command.
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
Write Erase
of 20 µs to suspend the erase operation. However,
Command Sequence
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation. Data Poll
from System
After the erase operation has been suspended, the Embedded
system can read array data from any sector not se- Erase
lected for erasure. (The device “erase suspends” all algorithm
sectors selected for erasure.) Normal read and write in progress
timings and command definitions apply. Reading at any No
Data = FFh?
address within erase-suspended sectors produces sta-
tus data on DQ7–DQ0. The system can use DQ7 to
determine if a sector is actively erasing or is erase-sus- Yes
pended. See “Write Operation Status” for information
on these status bits.
Erasure Completed
After an erase-suspended program operation is com-
plete, the system can once again read array data within
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or Notes:
DQ6 status bits, just as in the standard program oper- 1. See the appropriate Command Definitions table for erase
ation . See “Wr i te Operati on Status ” for m ore command sequence.
information. 2. See “DQ3: Sector Erase Timer” for more information.

The system may also write the autoselect command Figure 2. Erase Operation
sequence when the device is in the Erase Suspend

14 Am29F010B
Command Definitions
Table 4. Am29F010B Command Definitions
Bus Cycles (Notes 2-3)
Command

Cycles
First Second Third Fourth Fifth Sixth
Sequence
(Note 1) Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 4) 1 RA RD

Reset (Note 5) 1 XXXX F0

Reset (Note 6) 3 555 AA 2AA 55 555 F0

Manufacturer ID 4 555 AA 2AA 55 555 90 X00 01

Autoselect Device ID 4 555 AA 2AA 55 555 90 X01 20

(Note 7) 00
Sector Protect Verify (SA)
4 555 AA 2AA 55 555 90
(Note 8) X02 01

Program 4 555 AA 2AA 55 555 A0 PA PD

Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Erase Suspend (Note 9) 1 XXX B0

Erase Resume (Note 10) 1 XXX 30

Legend:
X = Don’t care PD = Data to be programmed at location PA. Data latches on the
RA = Address of the memory location to be read. rising edge of WE# or CE# pulse, whichever happens first.

RD = Data read from location RA during read operation. SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A16–A14 uniquely select any sector.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.

Notes:
1. See Table 1 for description of bus operations. 7. The fourth cycle of the autoselect command sequence is a
2. All values are in hexadecimal. read operation.

3. Except when reading array or autoselect data, all command 8. The data is 00h for an unprotected sector and 01h for a
bus cycles are write operations. protected sector. See “Autoselect Command Sequence” for
more information.
4. No unlock or command cycles required when reading array
data. 9. The system may read in non-erasing sectors, or enter the
autoselect mode, when in the Erase Suspend mode. The
5. The Reset command is required to return to reading array Erase Suspend command is valid only during a sector erase
data when device is in the autoselect mode, or if DQ5 goes operation.
high (while the device is providing status data).
10. The Erase Resume command is valid only during the Erase
6. The device accepts the three-cycle reset command Suspend mode.
sequence for backward compatibility.

Am29F010B 15
WRITE OPERATION STATUS
The device provides several bits to determine the sta- Table 5 shows the outputs for Data# Polling on DQ7.
tus of a write operation: DQ3, DQ5, DQ6, and DQ7. Figure 3 shows the Data# Polling algorithm.
Table 5 and the following subsections describe the
functions of these bits. DQ7 and DQ6 each offer a
method for determining whether a program or erase
operation is complete or in progress. These three bits START
are discussed first.

DQ7: Data# Polling

Read DQ7–DQ0
The Data# Polling bit, DQ7, indicates to the host sys- Addr = VA
tem whether an Embedded Algorithm is in progress or
completed. Data# Polling is valid after the rising edge
of the final WE# pulse in the program or erase com-
mand sequence.
DQ7 = Data? Yes
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. When the Embedded Program
algorithm is complete, the device outputs the datum No
programmed to DQ7. The system must provide the pro-
gram address to read valid status information on DQ7. No
If a program address falls within a protected sector, DQ5 = 1?
Data# Polling on DQ7 is active for approximately 2 µs,
then the device returns to reading array data.
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase al-
gorithm is complete, Data# Polling produces a “1” on Read DQ7–DQ0
DQ7. This is analogous to the complement/true datum Addr = VA
output described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of Yes
the sectors selected for erasure to read valid status in- DQ7 = Data?
formation on DQ7.
After an erase command sequence is written, if all sec- No
tors selected for erasing are protected, Data# Polling
on DQ7 is active for approximately 100 µs, then the de- PASS
FAIL
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se- Notes:
lected sectors that are protected. 1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
When the system detects DQ7 has changed from the sector selected for erasure. During chip erase, a valid
complement to true data, it can read valid data at DQ7– address is any non-protected sector address.
DQ0 on the following read cycles. This is because DQ7
2. DQ7 should be rechecked even if DQ5 = “1” because
may change asynchronously with DQ0–DQ6 while
DQ7 may change simultaneously with DQ5.
Output Enable (OE#) is asserted low. The Data# Poll-
ing Timings (During Embedded Algorithms) figure in
Figure 3. Data# Polling Algorithm
the “AC Characteristics” section illustrates this.

16 Am29F010B
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete. START
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final WE# pulse in the com-
mand sequence (prior to the program or erase
operation), and during the sector erase time-out. Read DQ7–DQ0
During an Embedded Program or Erase algorithm op-
eration, successive read cycles to any address cause
DQ6 to toggle. (The system may use either OE# or Read DQ7–DQ0 (Note 1)
CE# to control the read cycles.) When the operation is
complete, DQ6 stops toggling.
After an erase command sequence is written, if all sec-
tors selected for erasing are protected, DQ6 toggles for Toggle Bit No
approximately 100 µs, then returns to reading array = Toggle?
data. If not all selected sectors are protected, the Em-
bedded Erase algorithm erases the unprotected Yes
sectors, and ignores the selected sectors that are
protected.
If a program address falls within a protected sector, No
DQ5 = 1?
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data. Yes

The Write Operation Status table shows the outputs for

Toggle Bit I on DQ6. Refer to Figure 4 for the toggle bit Read DQ7–DQ0 (Notes
algorithm, and to the Toggle Bit Timings figure in the Twice 1, 2)
“AC Characteristics” section for the timing diagram.

Reading Toggle Bit DQ6

Toggle Bit No
Refer to Figure 4 for the following discussion. When- = Toggle?
ever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, a Yes
system would note and store the value of the toggle bit Program/Erase
after the first read. After the second read, the system Operation Not Program/Erase
would compare the new value of the toggle bit with the Complete, Write Operation Complete
first. If the toggle bit is not toggling, the device has com- Reset Command
pleted the program or erase operation. The system can
Notes:
read array data on DQ7–DQ0 on the following read
1. Read toggle bit twice to determine whether or not it is
cycle. toggling. See text.
However, if after the initial two read cycles, the system 2. Recheck toggle bit because it may stop toggling as DQ5
determines that the toggle bit is still toggling, the sys- changes to “1”. See text.
tem also should note whether the value of DQ5 is high Figure 4. Toggle Bit Algorithm
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling,
since the toggle bit may have stopped toggling just as The remaining scenario is that the system initially de-
DQ5 went high. If the toggle bit is no longer toggling, termines that the toggle bit is toggling and DQ5 has not
the device has successfully completed the program or gone high. The system may continue to monitor the
erase operation. If it is still toggling, the device did not toggle bit and DQ5 through successive read cycles, de-
complete the operation successfully, and the system termining the status as described in the previous
must write the reset command to return to reading paragraph. Alternatively, it may choose to perform
array data. other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 4).

Am29F010B 17
DQ5: Exceeded Timing Limits tional sectors are selected for erasure, the entire time-
out also applies after each additional sector erase com-
DQ5 indicates whether the program or erase time has
mand. When the time-out is complete, DQ3 switches
exceeded a specified internal pulse count limit. Under
from “0” to “1.” The system may ignore DQ3 if the sys-
these conditions DQ5 produces a “1.” This is a failure
tem can guarantee that the time between additional
condition that indicates the program or erase cycle was
sector erase commands will always be less than 50 µs.
not successfully completed.
See also the “Sector Erase Command Sequence”
The DQ5 failure condition may appear if the system section.
tries to program a “1” to a location that is previously pro-
After the sector erase command sequence is written,
grammed to “0.” Only an erase operation can change
the system should read the status on DQ7 (Data# Poll-
a “0” back to a “1.” Under this condition, the device
ing) or DQ6 (Toggle Bit I) to ensure the device has
halts the operation, and when the operation has ex-
accepted the command sequence, and then read DQ3.
ceeded the timing limits, DQ5 produces a “1.”
If DQ3 is “1”, the internally controlled erase cycle has
Under both these conditions, the system must issue the begun; all further commands are ignored until the
reset command to return the device to reading array erase operation is complete. If DQ3 is “0”, the device
data. will accept additional sector erase commands. To en-
sure the command has been accepted, the system
DQ3: Sector Erase Timer software should check the status of DQ3 prior to and
After writing a sector erase command sequence, the following each subsequent sector erase command. If
system may read DQ3 to determine whether or not an DQ3 is high on the second status check, the last com-
erase operation has begun. (The sector erase timer mand might not have been accepted. Table 5 shows
does not apply to the chip erase command.) If addi- the outputs for DQ3.

Table 5. Write Operation Status

DQ7 DQ5
Operation (Note 1) DQ6 (Note 2) DQ3

Standard Embedded Program Algorithm DQ7# Toggle 0 N/A

Mode
Embedded Erase Algorithm 0 Toggle 0 1

Erase Reading within Erase Suspended Sector 1 No toggle 0 N/A

Suspend
Mode Reading within Non-Erase Suspended Sector Data Data Data Data

Notes:
1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.
2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See “DQ5: Exceeded Timing Limits” for more information.

18 Am29F010B
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +125°C
20 ns 20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C +0.8 V
Voltage with Respect to Ground
–0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . .–2.0 V to +7.0 V
A9 (Note 2). . . . . . . . . . . . . . . . . . . .–2.0 V to +13.0 V –2.0 V
All other pins (Note 1) . . . . . . . . . . . .–2.0 V to +7.0 V
20 ns
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes: Figure 5. Maximum Negative
1. Minimum DC voltage on input or I/O pin is –0.5 V. During Overshoot Waveform
voltage transitions, inputs may overshoot VSS to –2.0 V
for periods of up to 20 ns. See Figure 5. Maximum DC
voltage on input and I/O pins is VCC + 0.5 V. During volt-
age transitions, input and I/O pins may overshoot to V CC
+ 2.0 V for periods up to 20 ns. See Figure 6. 20 ns
2. Minimum DC input voltage on A9 pin is –0.5V. During VCC
voltage transitions, A9 pins may overshoot VSS to –2.0 V +2.0 V
for periods of up to 20 ns. See Figure 5. Maximum DC in- VCC
put voltage on A9 is +12.5 V which may overshoot to 14.0 +0.5 V
V for periods up to 20 ns.
2.0 V
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second. 20 ns 20 ns
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is Figure 6. Maximum Positive
a stress rating only; functional operation of the device at Overshoot Waveform
these or any other conditions above those indicated in the op-
erational sections of this specification is not implied. Expo-
sure of the device to absolute maximum rating conditions for
extended periods may affect device reliability.

OPERATING RANGES
Commercial (C) Devices
Case Temperature (TA) . . . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Case Temperature (TA) . . . . . . . . . . . –40°C to +85°C
Extended (E) Devices
Case Temperature (TA) . . . . . . . . . . –55°C to +125°C
VCC Supply Voltages
VCC for ±5% devices . . . . . . . . . . .+4.75 V to +5.25 V
VCC for ±10% devices . . . . . . . . . .+4.50 V to +5.50 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.

Am29F010B 19
DC CHARACTERISTICS
TTL/NMOS Compatible
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

VCC Active Read Current

ICC1 CE# = VIL, OE# = VIH 12 30 mA
(Notes 1, 2)

VCC Active Write Current

ICC2 CE# = VIL, OE# = VIH 30 40 mA
(Notes 2, 3, 4)

ICC3 VCC Standby Current CE# and OE# = VIH 0.4 1.0 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.0 VCC + 0.5 V

Voltage for Autoselect and Sector

VID VCC = 5.0 V 10.5 12.5 V
Protect

VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V

VOH Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V

VLKO Low VCC Lock-out Voltage 3.2 4.2 V

Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC=VCCmax.
3. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
4. Not 100% tested.

20 Am29F010B
DC CHARACTERISTICS (Continued)
CMOS Compatible
Parameter
Symbol Parameter Description Test Description Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9 Input Load Current VCC = VCC Max, A9 = 12.5 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Active Current (Notes 1, 2) CE# = VIL, OE# = VIH 12 30 mA

VCC Active Current

ICC2 CE# = VIL, OE# = VIH 30 40 mA
(Notes 2, 3, 4)

ICC3 VCC Standby Current (Note 5) CE# = VCC ± 0.5 V, OE# = VIH 1 5 µA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 x VCC VCC + 0.3 V

Voltage for Autoselect and

VID VCC = 5.25 V 10.5 12.5 V
Sector Protect

VOL Output Low Voltage IOL = 12 mA, VCC = VCC Min 0.45 V

VOH1 IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V

Output High Voltage
VOH2 IOH = –100 µA, VCC = VCC Min VCC – 0.4 V

VLKO Low VCC Lock-out Voltage 3.2 4.2 V

Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC=VCCmax.
3. ICC active while Embedded Program or Embedded Erase Algorithm is in progress.
4. Not 100% tested.
5. ICC3 = 20 µA max at extended temperatures (> +85°C).

Am29F010B 21
TEST CONDITIONS
Table 6. Test Specifications
5.0 V
Test Condition -45 All others Unit

2.7 kΩ Output Load 1 TTL gate

Device
Under Output Load Capacitance, CL
30 100 pF
Test (including jig capacitance)
CL 6.2 kΩ Input Rise and Fall Times 5 20 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

1.5 0.8 V
reference levels

Note: Diodes are IN3064 or equivalent Output timing measurement

1.5 2.0 V
reference levels
Figure 7. Test Setup

KEY TO SWITCHING WAVEFORMS

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

22 Am29F010B
AC CHARACTERISTICS
Read-only Operations Characteristics
Parameter
Symbol Speed Options

JEDEC Std Parameter Description Test Setup -45 -55 -70 -90 -120 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 45 55 70 90 120 ns

CE# = VIL
tAVQV tACC Address to Output Delay Max 45 55 70 90 120 ns
OE# = VIL

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 45 55 70 90 120 ns

tGLQV tOE Output Enable to Output Delay Max 25 30 30 35 50 ns

Chip Enable to Output High Z

tEHQZ tDF Max 10 15 20 20 30 ns
(Note 1)

Output Enable to Output High Z

tGHQZ tDF Max 10 15 20 20 30 ns
(Note 1)

Read Min 0 ns
Output Enable Hold Time
tOEH Toggle and Data
(Note 1) Min 10 ns
Polling

Output Hold Time From

tAXQX tOH Addresses CE# or OE#, Min 0 ns
Whichever Occurs First

Notes:
1. Not 100% tested.
2. See Figure 7 and Table 6 for test specifications.

tRC

Addresses Addresses Stable

tACC
CE#

tDF
tOE
OE#
tOEH

WE# tCE
tOH
HIGH Z HIGH Z
Outputs Output Valid

Figure 8. Read Operations Timings

Am29F010B 23
AC CHARACTERISTICS
Erase and Program Operations
Parameter Symbol Speed Options

JEDEC Std Parameter Description -45 -55 -70 -90 -120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 45 55 70 90 120 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 35 45 45 45 50 ns

tDVWH tDS Data Setup Time Min 20 20 30 45 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

Read Recover Time Before Write

tGHWL tGHWL Min 0 ns
(OE# High to WE# Low)

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 25 30 35 45 50 ns

tWHWL tWPH Write Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs

tWHWH2 tWHWH2 Chip/Sector Erase Operation (Note 2) Typ 1.0 sec

tVCS VCC Set Up Time (Note 1) Min 50 µs

Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more informaiton.

24 Am29F010B
AC CHARACTERISTICS
Program Command Sequence (last two cycles) Read Status Data (last two cycles)
tWC tAS

Addresses 555h PA PA PA
tAH

CE#
tCH

OE#

tWP tWHWH1

WE#
tWPH
tCS
tDS
tDH

Data A0h PD Status DOUT

tVCS

VCC

Note: PA = program address, PD = program data, DOUT is the true data at the program address.
Figure 9. Program Operation Timings

Erase Command Sequence (last two cycles) Read Status Data

tWC tAS
Addresses 2AAh SA VA VA
555h for chip erase
tAH
CE#

OE# tCH

tWP
WE#
tWPH tWHWH2
tCS
tDS
tDH
In
Data 55h 30h Progress Complete

10 for Chip Erase

tVCS
VCC

Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
Figure 10. Chip/Sector Erase Operation Timings

Am29F010B 25
AC CHARACTERISTICS
tRC
Addresses VA VA VA
tACC
tCE
CE#

tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ7 Complement Complement True Valid Data

High Z
DQ0–DQ6 Status Data Status Data True Valid Data

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 11. Data# Polling Timings (During Embedded Algorithms)

tRC
Addresses VA VA VA VA
tACC
tCE
CE#

tCH
tOE
OE#
tOEH tDF
WE#
tOH
High Z
DQ6 Valid Status Valid Status Valid Status Valid Data
(first read) (second read) (stops toggling)

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle.
Figure 12. Toggle Bit Timings (During Embedded Algorithms)

26 Am29F010B
AC CHARACTERISTICS
Erase and Program Operations
Alternate CE# Controlled Writes

Parameter Symbol Speed Options

JEDEC Standard Parameter Description -45 -55 -70 -90 -120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 45 55 70 90 120 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 35 45 45 45 50 ns

tDVEH tDS Data Setup Time Min 20 20 30 45 50 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time (Note 1) Min 0 ns

tGHEL tGHEL Read Recover Time Before Write Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 25 30 35 45 50 ns

tEHEL tCPH CE# Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 7 µs

tWHWH2 tWHWH2 Chip/Sector Erase Operation (Note 2) Typ 1.0 sec

Notes:
1. Not 100% tested.
2. See the “Erase and Programming Performance” section for more information.

Am29F010B 27
AC CHARACTERISTICS
555 for program PA for program
2AA for erase SA for sector erase
555 for chip erase
Data# Polling

Addresses PA
tWC tAS
tAH
tWH

WE#
tGHEL
OE#
tCP tWHWH1 or 2

CE#
tWS tCPH
tDS
tDH
DQ7# DOUT
Data
A0 for program PD for program
55 for erase 30 for sector erase
10 for chip erase

Notes:
1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.
2. Figure indicates the last two bus cycles of the command sequence.
Figure 13. Alternate CE# Controlled Write Operation Timings

ERASE AND PROGRAMMING PERFORMANCE

Limits

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Excludes 00h programming prior to

Chip/Sector Erase Time 1.0 15 sec
erasure (Note 4)

Byte Programming Time 7 300 µs Excludes system-level overhead

Chip Programming Time (Note 3) 0.9 6.25 sec (Note 5)

Notes:
1. Typical program and erase times assume the following conditions: 25°C, 5.0 V VCC, 1 million cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 4.5 V (4.75 V for -45), 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then
does the device set DQ5 = 1. See the section on DQ5 for further information.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle command sequence for programming. See Table 4
for further information on command definitions.
6. The device has a minimum guaranteed erase cycle endurance of 1 million cycles.

28 Am29F010B
LATCHUP CHARACTERISTIC
Parameter Description Min Max

Input Voltage with respect to VSS on I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Note: Includes all pins except VCC. Test conditions: VCC = 5.0 Volt, one pin at a time.

TSOP PIN CAPACITANCE

Parameter
Symbol Parameter Description Test Conditions Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.

PLCC AND PDIP PIN CAPACITANCE

Parameter
Symbol Parameter Description Test Conditions Typ Max Unit

CIN Input Capacitance VIN = 0 4 6 pF

COUT Output Capacitance VOUT = 0 8 12 pF

CIN2 Control Pin Capacitance VPP = 0 8 12 pF

Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION
Parameter Description Test Conditions Min Unit

150°C 10 Years
Minimum Pattern Data Retention Time
125°C 20 Years

Am29F010B 29
PHYSICAL DIMENSIONS
PD 032—32-Pin Plastic DIP

Dwg rev AD; 10/99

30 Am29F010B
PHYSICAL DIMENSIONS* (continued)
PL 032—32-Pin Plastic Leaded Chip Carrier

Dwg rev AH; 10/99

Am29F010B 31
PHYSICAL DIMENSIONS* (continued)
TS 032—32-Pin Standard Thin Small Outline Package

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic Space Centering.

32 Am29F010B
PHYSICAL DIMENSIONS* (continued)
TSR 032—32-Pin Standard Thin Small Outline Package

Dwg rev AA; 10/99

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Am29F010B 33
REVISION SUMMARY
Revision A (August 12, 1999) Revision B (November 12, 1999)
In iti al r el ea se. Th e Am 2 9F 0 10 B re pl aces th e AC Characteristics—Figure 9. Program Operations
Am29F010A data sheet (22181B+1). Timing and Figure 10. Chip/Sector Erase
Operations
Revision A+1 (September 22, 1999)
Deleted tGHWL and changed OE# waveform to start at
Device Bus Operations high.
Sector Protection/Unprotection: Corrected the publica-
Physical Dimensions
tion number for the programming supplement.
Replaced figures with more detailed illustrations.
Revision A+2 (September 27, 1999)
Revision C (November 28, 2000)
Erase and Programming Performance table
Global
In Notes 1 and 6, corrected the erase cycle endurance
to 1 million cycles. Added table of contents. Removed Preliminary status
from document.
Ordering Information
Deleted burn-in option.

Trademarks

Copyright © 2000 Advanced Micro Devices, Inc. All rights reserved.

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

34 Am29F010B