Analog Circuits LAB Manual

Experiment No. 6

Op-Amp as Comparator & Schmitt Trigger

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 1

 Analog Circuits LAB Manual

Expt.No.6 Op – Amp as comparator and Schmitt trigger.

Aim: Test a comparator circuit and design a Schmitt trigger for the given UTP and LTP
values and obtain the hysteresis.

Apparatus required:
SI. No. Particulars Specification Quantity
1 Op-Amp IC - 741 1
2 Resistor 100KΩ, 10 KΩ 2
22 KΩ,18 KΩ,3.9 KΩ 1
1.5 KΩ ,1KΩ , 220 KΩ 1

3 Dual Regulated Power supply 0-30V, 2A 1

4 Function Generator 1– 3M Hz, 20 Vp-p 1
,1
5 Cathode Ray Oscilloscope 0– 30M Hz 1

Theory:
A comparator as its name implies, compares a signal voltage on one input of an op-amp with
a known voltage called a reference voltage on the other input. Comparators are used in
circuits such as, digital Interfacing, Schmitt Trigger, discriminator, voltage level detector and
oscillators.

Non-inverting Comparator:
A fixed reference voltage Vref of 1 V is applied to the negative terminal and time varying
signal voltage Vin is applied to the positive terminal. When Vin is less than Vref the output
becomes V0 at –Vsat [Vin < Vref => V0 (-Vsat)]. When Vin is greater than Vref, the (+)
input becomes positive, the V0 goes to +Vsat. [Vin > Vref => V0 (+Vsat)]. Thus the V0
changes from one saturation level to another. The diodes D1 and D2 protect the op-amp from
damage due to the excessive input voltage Vin. Because of these diodes, the difference input
voltage Vid of the op-amp diodes are called clamp diodes. The resistance R in series with Vin
is used to limit the current . One of the applications of comparator is the zero crossing
detectors or sine wave to square wave Converter. The basic comparator can be used as a zero
crossing detector by setting Vref is set to Zero. (Vref =0V).

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 2

 Analog Circuits LAB Manual

Drawbacks of Zero- crossing detector:

In some applications, the input Vin may be a slowly changing waveform, (i.e) a low
frequency signal. Vin will take more time to cross 0V, therefore V0 may not switch quickly
from one saturation voltage to the other. Because of the noise at the op-amp‘s input terminals
the output V0 may fluctuate between 2 saturations voltages +Vsat and –Vsat. Both of these
problems can be solved with the use of regenerative or positive feedback that causes the
output V0 to change faster and eliminate any false output transitions due to noise signals at
the input. Inverting comparator with positive feedback . This is known as ―Schmitt Trigger.

Schmitt Trigger:
This circuit converts an irregular shaped waveform to a square wave or pulse. The circuit is
known as Schmitt Trigger or squaring circuit. The input voltage Vin triggers (changes the
state of) the o/p V0 every time it exceeds certain voltage levels called the upper threshold Vut
and lower threshold voltage. These threshold voltages are obtained by using the voltage
divider circuit R1 – R2, where the voltage across R1 is feedback to the (+) input. The voltage
across R1 is variable reference threshold voltage that depends on the value of the output
voltage. When V0 = +Vsat, the voltage across R1 is called ―upper threshold voltage Vut.
The input voltage Vin must be more positive than Vut in order to cause the output V0 to
switch from +Vsat to –Vsat. As long as Vin < Vut , V0 is at +Vsat, using voltage divider rule,

Vut = +Vsat

Similarly, when V0 = -Vsat, the voltage across R1 is called lower threshold voltage Vlt . the
vin must be more negative than Vlt in order to cause V0 to switch from –Vsat to +Vsat. In
other words, for Vin > Vlt , V0 is at –Vsat. Vlt is given by the following eqn Vlt =-Vsat

. Thus, if the threshold voltages Vut and Vlt are made larger than the input noise

voltages, the positive feedback will eliminate the false o/p transitions. Also the positive
feedback, because of its regenerative action, will make V0 switch faster between +Vsat and –
Vsat. The comparator with positive feedback is said to exhibit hysteresis, a dead band
condition. (i.e) when the input of the comparator exceeds Vut its output switches from +Vsat
to –Vsat and reverts to its original state, +Vsat when the input goes below Vlt. The hysteresis
voltage is equal to the difference between Vut and Vlt. Therefore Vref = Vut – Vlt

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 3

 Analog Circuits LAB Manual

Design:
Schmitt Trigger
a) Inverting Schmitt trigger with same UTP and LTP: To design inverting Schmitt
trigger circuit for UTP = LTP = 1V.

Let I2 = 100 IB (Max)

IB (Max) = 500nA.
I2 = 50µA

R2 = = 20KΩ (Two 10 KΩ resistors in series)

( )
R1 = 200 KΩ (Two 100 KΩ resistors in series)

b) Inverting Schmitt trigger with different UTP and LTP: To design inverting
Schmitt trigger circuit for UTP =4V and LTP= 2V.

( )
UTP=

(( ) )
4 =

4R1+4R2 = 10.3R2

Let R2 = 1 KΩ

R1= =1.5 KΩ (Std)

( )
LTP =

(( ) )
2=

R3 = 4.15 KΩ = 3.9 KΩ (Std)

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 4

 Analog Circuits LAB Manual

c) Non-Inverting Schmitt trigger with same UTP and LTP: To design non-inverting
Schmitt trigger circuit for UTP=LTP=2V.

R1= = = 40 KΩ (22 KΩ + 18 KΩ in series)

R2 = = = 220 KΩ

d) Non-Inverting Schmitt trigger with different UTP and LTP: To design non-
inverting Schmitt trigger circuit for UTP= 3V, LTP=1V.

Let I2 = 500µA

UT
R1 = = = 6 KΩ = 5.6 KΩ (Std)
2

( )
R2 = = = 20 KΩ (Two 10 KΩ resistors in series)

LTP = 1 V

I3 = = = 178 µA

( )
R3 = = = 57KΩ = 56 KΩ (Std)

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 5

 Analog Circuits LAB Manual

Circuit diagram:
a) Inverting Zero crossing detector
+VCC = 12V

3
+ 7
6
Vo
IC741
_
R1= 1 KΩ
4
2

R2 =1 KΩ -VEE = -12V CRO

Vref = 0

Vin = 10 V(P-P)

Fig. 1 Circuit of Inverting Zero Crossing Detector

Nature of graph

Fig. 2 Waveform of Inverting Zero Crossing Detector

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 6

 Analog Circuits LAB Manual

b) Non inverting Voltage level detector

+12
2
_
7
6

IC741 Vo

R1=1KΩ + 4
3
CRO
R2 = 1KΩ -12
Vref = 2V

Vin = 10V(P-P)

Fig. 3 Circuit of Non - Inverting Voltage Level Detector

Nature of graph

Fig. 4 Waveform of Non - Inverting Voltage Level Detector

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 7

 Analog Circuits LAB Manual

c) Inverting Schmitt trigger with same UTP and LTP

+VCC = +12V

- 7
6
IC741 Vo
3
Vi= 10V(P-P) +
4

-VEE = -12V R1

CRO

R2

Fig. 5 Inverting Schmitt Trigger with same UTP & LTP

d) Inverting Schmitt trigger with different UTP and LTP

VCC

2
7
-
6
IC741
3
Vi + D1 D2
4
10V(p-p)
-VEE
R1 R3 CRO
Vo

R2

Fig. 6 Inverting Schmitt Trigger with different UTP & LTP

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 8

 Analog Circuits LAB Manual

Nature of graph

Fig. 6 Waveform for Inverting Schmitt Trigger

Hysteresis Characteristics /Transfer Characteristics

Fig. 7 Hysteresis characteristics Inverting Schmitt Trigger

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 9

 Analog Circuits LAB Manual

e) Non-Inverting Schmitt trigger with same UTP and LTP

R2

VCC
R1
+ 7
3
Ic741
- 6
Vi
2 4
10V(p-p) CRO
-VEE Vo

Fig. 8 Non Inverting Schmitt Trigger with same UTP & LTP

f) Non-Inverting Schmitt trigger with different UTP and LTP

D1 R2

D2 R3

VCC

R1 7
3
+
6
IC741
2
_
Vi 4
CRO
-VEE Vo

Fig. 9 Non Inverting Schmitt Trigger with different UTP & LTP

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 10

 Analog Circuits LAB Manual

Nature of graph

UTP

LTP

Fig. 10 Waveform for Non-Inverting Schmitt Trigger

Hysteresis Characteristics /Transfer Characteristics

Fig. 11 Hysteresis characteristics for Non-Inverting Schmitt Trigger

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 11

 Analog Circuits LAB Manual

Procedure:
a) Zero crossing detector
1. Connect the circuit as shown in Fig 1.
2. Apply ac input (sine wave) of arbitrary amplitude with Vref = 0.
3. Apply the biasing voltages of +12V to pin7 and pin4 of IC741 respectively.
4. Note down the output waveform and plot the graph.

b) Voltage level detector

1. Connect the circuit as shown in Fig 3.
2. Apply ac input (sine wave) of arbitrary amplitude with Vref = 1 V.
3. Apply the biasing voltages of +12V to pin7 and pin4 of IC741 respectively.
4. Note down the output waveform and plot the graph.

c) Schmitt Trigger
1. Connect the circuit as shown in Fig 5 and Fig 6, Fig 8 and Fig 9.
2. Apply ac input (sine wave) of arbitrary amplitude with peak voltage greater than UTP
and LTP to the input of a Schmitt trigger.
3. Observe the output at pin6 of the IC 741.
4. Note down the readings from CRO.
5. Find the upper and lower threshold voltages from the output waveform or from
Output/input characteristics (Hysteresis curve).
6. Adjust the frequency till proper hysteresis curve is obtained.
7. Plot the graph for output voltage and output/input characteristics.

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 12

 Analog Circuits LAB Manual

Tabular Column

a) Inverting Zero Crossing detector

SI. No. Vin Vref Vo

(in V) (in V) (in V)

b) Non Inverting Voltage level detector

SI. No. Vin Vref Vo

(in V) (in V) (in V)

c) Inverting Schmitt trigger with same UTP & LTP

SI. No. Vi Vo Vo UTP UTP LTP LTP

(p-p) (p-p) (p-p) (Theo) (Practical) (Theo) (Practical)
(Theo) (Practical)
(in V) (in V) (in V) (in V) (in V) (in V) (in V)
1

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 13

 Analog Circuits LAB Manual

d) Inverting Schmitt trigger with different UTP & LTP

SI. No. Vi Vo Vo UTP UTP LTP LTP

(p-p) (p-p) (p-p) (Theo) (Practical) (Theo) (Practical)
(Theo) (Practical)
(in V) (in V) (in V) (in V) (in V) (in V) (in V)
1

e) Non Inverting Schmitt trigger with same UTP & LTP

SI. No. Vi Vo Vo UTP UTP LTP LTP

(p-p) (p-p) (p-p) (Theo) (Practical) (Theo) (Practical)
(Theo) (Practical)
(in V) (in V) (in V) (in V) (in V) (in V) (in V)
1

f) Non Inverting Schmitt trigger with different UTP & LTP

SI. No. Vi Vo Vo UTP UTP LTP LTP

(p-p) (p-p) (p-p) (Theo) (Practical) (Theo) (Practical)
(Theo) (Practical)
(in V) (in V) (in V) (in V) (in V) (in V) (in V)
1

Result:

The Op-Amp as comparator (Zero crossing detector, Voltage level detector) and Schmitt
trigger with same and different UTP & LTP is designed and verified.

Prof. Chaitanya K J, Dept. of ECE, JCER, Belagavi. Page 14