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System On Chip - FPGA Architecture

The document provides an introduction to FPGA architecture. It discusses the core components of FPGAs including programmable logic blocks, routing resources, and I/O. It then focuses on the logic blocks, describing lookup tables (LUTs) and how they can implement different functions. The document discusses important design decisions for FPGA architecture including LUT size, cluster size, and the use of hard blocks.

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Amoghavarsha BM
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94 views28 pages

System On Chip - FPGA Architecture

The document provides an introduction to FPGA architecture. It discusses the core components of FPGAs including programmable logic blocks, routing resources, and I/O. It then focuses on the logic blocks, describing lookup tables (LUTs) and how they can implement different functions. The document discusses important design decisions for FPGA architecture including LUT size, cluster size, and the use of hard blocks.

Uploaded by

Amoghavarsha BM
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Introduction to FPGAs

Outline
• Architecture
– Logic
– Routing
– I/O

• State-of-the-art: Xilinx Virtex 7


FPGA Architecture

Programmable Logic

Programmable Routing

3
Logic: Lookup Tables

LUT FF

2K 2 K :1
LUT FF

SRAM MUX

LUT FF

LUT FF

Slice/Cluster

4
Look-up Table
• 2K SRAM Cells

• 22K different functions

2K 2 K :1

SRAM MUX • 2K:1 MUX


– K-levels of 2:1 muxes

5
Look-up Table: 2-inputs
• 22 SRAM Cells

• 222 different functions

22 2 2 :1

SRAM MUX • 22:1 MUX


– 2-levels of 2:1 muxes

6
Look-up Table: 2-input NAND
• 4 SRAM Cells
– 6 transistors each

1 • 4:1 MUX
1 4:1
– ~12 transistors
1 MUX

0 • ~40 Transistors
2

7
Look-up Table: 2-input NAND

HUGE!

1
1 4:1

1 MUX

0
2

40 Transistors 4 Transistors
8
Design Flow: FPGA

Benchmark Circuits HDL

Logic Synthesis

FPGA Architecture Technology Mapping

Pack, Place & Route

FPGA Area, Power, Speed

9
Architecture-level studies
• Depth of the CAD flow
• Quality of the CAD tools
• Benchmark circuits
• Quality of tools used to measure performance
LOGIC BLOCK ARCHITECTURE
Logic: Soft

Programmable
Logic Blocks

12
Logic: Hard Blocks

Memory
Blocks

13
Logic: Hard Blocks

DSP
Blocks

14
Logic: Lookup Tables

LUT FF

2K 2 K :1
LUT FF

SRAM MUX

LUT FF

LUT FF

Slice/ Cluster

15
Design decisions
• LUT size
• Number of LUTs per cluster
• Inputs/Outputs to/from each cluster
• Area and Speed
No. of Logic Blocks vs.
Logic Block Functionality

• LUT size increases exponentially with K


• Routing tracks surrounding logic increases
with the number of input pins
Total FPGA area vs. LUT size
Terminology
• Basic logic element (BLE) LUT FF

• Cluster
– Size grows quadratically LUT FF

– Local interconnect
– Fewer inputs (shared) LUT FF

LUT FF
LUTs on critical path & LUT delay
vs LUT size

Functionality increases=> fewer logic blocks on critical path


=> internal delay increases
CLUSTER SIZE
• Rose et al
– 2N +2
– not 4N

• Ahmed et al
– I = K (N+1)/2
– not KN
Critical path: Function of LUT and Cluster size

Diminishing returns beyond


LUT6 and cluster size 3,4
Cluster multiplexer area and LUT size.
HETEROGENEOUS BLOCKS
Choice of functions
• Which function?
• Ratio of special function
to generic logic?
• What to do with special
function blocks when
they are not used?
Hard blocks
• FFs (set, reset, enable, load,…)
• Add, sub, carry logic, …
• Use LUTs as memories
• Block RAMs/ ROMs, FIFOs
• Multipliers (fracturable)
• Processors
Challenge
• Performance, power, area
– As compared to ASICs
• Introduce other hard blocks
– Floating point units, etc.
• Shadow logic

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