International Conference on Communication and Signal Processing, April 4-6, 2019, India

Performance Analysis of Wallace Tree

Multiplier with Kogge Stone Adder using 15-4
Compressor
A.Sundhar, S.Deva tharshini, G.Priyanka, S.Ragul and C.Saranya

Abstract—The major role of electronics device is to provide low propagation. Either there are not any carry signals or they do
power dissipation and compact area with high speed arrive at the same time of the internal values[5-7].
performance. Among the major modules in digital building blocks For the purpose of reducing the delay in the second stage,
system, multiplier is the most complex one and main source of
power dissipation. Approximate Computing to multiplier design
several compressors are needed. Small sizes of compressors
plays major role in electronic applications, like multimedia by are useful for designing the small size multiplier. In multiplier
providing fastest result even though it possesses low reliability. In design, the different sizes of compressors are required
this paper, a design approach of 16bit Wallace Tree approximate depending upon the bit size. In this paper, a scheme for delay
multiplier with 15-4 compressor is considered to provide more reduction in 16bit Wallace tree multiplier with 15:4
reliability. The 16×16 Wallace tree multiplier is synthesized and compressor is considered. To build 15:4 compressor, a 5:3
simulated using Xilinx ISE 14.5 software. The multiplier occupies
about 15% of total coverage area. The dissipated power and delay compressor is considered as a basic module. AND gate is used
of the multiplier are 0.042μw, 3.125ns respectively. for the generation of partial products. For ‘N’ bit multiplier
‘N2’ AND gates are needed. In the partial product reduction
Index Terms—Kogge stone adder, 15-4 compressor, Wallace phase, there are three major components namely half adder,
tree multiplier, area, power delay and Xilinx ISE 14.5. full adder and 5-3 compressor[8-11]. The final stage of
addition is done by using Kogge-Stone adder. Fig. 1 shows the
I. INTRODUCTION
structure of 16X16 multiplier. Simulation results show that the

M ULTIPLIERS are the essential part of the digital system

like Arithmetic and Logic Units, Digital Signal
approximate multiplier with compressor using Kogge stone
adder achieves high performance while comparing to the
Processors, etc. Usually, they prompt the performance like multipliers with compressor using other adder like parallel
power, delay and area utilization of the system. Hence there is adder. This paper is elaborated in following sections. Designs
an increasing demand for the improvement of performance of of approximate 16×16 Wallace tree multiplier are detailed in
the multiplier[1-4]. The multiplier consists of 3 stages - partial section II. Brief notes and design of 15-4 compressor, 5-3
products generation, partial products reduction and addition at compressor and Kogge stone adder is described in section III.
the last stage. The second stage ( partial product) in multiplier The section IV depicts the Result analysis. Section V
utilize more time and power. Various techniques were concluded the overall paper.
suggested to diminish multipliers critical stages. The most
popular technique is using the compressor in the reduction II. WALLACE TREE MULTIPLIER
stage of partial product. The compressor is simply an adder
Multiplier is the substantive part of the electronic device
circuit. It takes a number of equally-weighted bits, adds them,
and decides the overall performance of the system [1]. When
and produces some sum signals. Compressors are commonly
designing a multiplier, huge amount of power and delay are
used with the aim of reducing and accumulating a large
generated. To minimize these disadvantages, adders and
number of inputs to a smaller number in a parallel manner.
compressor are used. Hence reducing delay in multiplier has
Their main application is within a multiplier, where partial
been a main aim to enhance the performance of the digital
products have to be summed up in a large amount
systems like DSP processors [8]. Hence many attempts are
concurrently. The inner structure of compressors avoids carry
done on multipliers to make it faster. It is an effective
hardware realization of digital system that is nothing but a
Dr.A. Sundhar is working as Assistant Professor, Department of Wallace tree which multiplies two numbers and minimizes the
Electronics and Communication Engineering, Perunthalaivar Kamarajar number of partial products [4]. In vector processors, several
Institute of Engineering and Technology, Karaikal, India, email: multiplications are performed to obtain data or loop level
[email protected].
S. Deva Tharshini, G. Priyanka, S. Ragul and C. Saranya are studying parallelism. High processing speed and low power
Final year B.Tech degree in the department of Electronics and consumption are the major advantages of this multiplier [2].
Communication Engineering, Perunthalaivar Kamarajar Institute of
Engineering and Technology, Karaikal, India,
([email protected],[email protected],ragulprince2510@gmail
.com, [email protected])

978-1-5386-7595-3/19/$31.00 ©2019 IEEE

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 column. In case of a single bit, it is moved further to the
subsequent level of that particular column without any need for
further processing. Until only two rows will remain, this
reduction process is repeated. Finally, summation of the last
two rows is achieved using 4-bit Kogge-Stone adder.

III. 15-4 COMPRESSOR

A compressor is simply an adder circuit. It takes a number
of equally-weighted bits, adds them, and produces some sum
signals. Compressors are commonly used with the aim of
reducing and accumulating a large number of inputs to a
smaller number in a parallel manner. They are the important
parts of the multiplier design as they highly influence the
speed of the multiplier. Their main application is within a
multiplier, where a huge number of partial products have to be
summed up concurrently. For high speed applications like
DSP, image processing needs several compressors to perform
arithmetic operation. A compressor adder provides reduced
delay over conventional adders using both half adders and full
Fig. 1. Structure of 16×16 Multiplier using 15-4 compressor
adders. Here the representation as ‘N-r’, in which ’N’ denotes
The three stages of Wallace tree multiplier are mentioned as the number of bits and ‘r’ denotes as the total number of 1’s
below: present in ‘N’ inputs. The compressor reduces the number of
1) Partial products generation gates and the delay with reference to other adder circuits. The
2) Partial products reduction inner structure of compressors avoids carry propagation. Either
3) Addition at the final stage there are not any carry signals or they do arrive at the same
time of the internal values. Compressors are widely used in the
reduction stage of a multiplier to accumulate partial products
in a concurrent manner. In this part it is considered the design
of 15-4 compressor by using with approximate 5-3
compressors [5]. This compressor compresses 15 inputs (C0-
C14) into 4 outputs (B0-B3). The 15-4 compressor consists of
three phases. The first phase has five full adders, the second
phase uses two 5-3 compressors and finally the 4-bit kogge
stone adder. In this compressor design, approximate 5-3
compressor are preferred over accurate 5-3 compressors as
shown in the Fig. 3

Fig. 2. Schematic View of 16×16 Bit Wallace Tree Multiplier

Fig. 1 and Fig. 2 describes the structure and schematic view

of 16bit multiplier using with the help of 15-4 compressor.
Here in this design each dot denotes partial product. From 13th
column onwards, 15-4 compressors are used in this multiplier
architecture. Column number 13 consist of 13 partial products,
in order to get 15 partial products 2 zeros are added. Similarly,
in 14th column, one zero is added. Approximate compressors
are used in 13th, 14th and15th column of multipliers. The
partial product reduction phase consists of half adder, full
adder and 5:3 compressors. When the numbers of bits in the
column are 2 and 3 half adders and full adders are used in each Fig. 3. Logic Diagram of Approximate 15-4 Compressor [6]

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 A. 5-3 Compressor C. Final processing.

The 15-4 compressor consists of 5-3 compressor as a basic A. Pre-Processing

design. The 5-3 compressor utilizes five primary inputs In this stage, the generate and propagate signals are given by
namely A0, A1, A2, A3, A4 and produces three outputs the equations 5&6.
namely B0, B1, B2. In this compressor, the presence of Pi=Ai ⊕ Bi (5)
number of 1’s at the input decides the output of compressor Gi=Ai . Bi (6)
and also uses counter property. B. Generation of carry
In this stage, carries are calculated with their corresponding
bits and this operation is executed in parallel manner. Carry
propagation and generation are used as intermediate signals.
The logic equations for carry propagate and generate are
shown below.
Gi= (Pi . Giprev) +Gi (7)
Pi= ( Pi . Piprev) (8)
C. Final Processing
In final processing, the sum and carry outputs bits are
computed for the given input bits and the logic equation for the
final processing stage is given by
Ci=Gi (9)
Si=Pi ⊕ Ci-1 (10)

Fig. 4. Logic diagram of 5-3 compressor

B2 ʹ = [A3.A2] (1)
B2=A0.[~(A0⊕A1)]+A2.(A0⊕A1)[A3.
(~(A0⊕A1⊕A2⊕A3))] + A4. [ A0⊕A1⊕A2⊕A3] (2)
B1=A0.[~(A0⊕A1)]+A2.(A0⊕A1)⊕[A3.
(~(A0⊕A1⊕A2⊕A3))] + A4. [ A0⊕A1⊕A2⊕A3] (3)
B0=[A0⊕A1⊕A2⊕A3⊕A4] (4)

The design of compression of given 5 inputs into 3 output

is called the design of 5-3 compressor. Error rate of 5-3
compressor is considered. The design equations of 5-3
approximate compressor are shown in following equations Fig. 5. Block diagram of kogge stone adder
respectively. The logic diagram of approximate 5-3
compressor is as shown in Fig. 4.
B. Kogge Stone Adder
In 1973, Peter M. Kogge and Harold S. Stone introduced
the concept of efficient and high-performance adder called
kogge-stone adder. It is basically a parallel prefix adder. This
type of adder has the specialty of fastest addition based on
design time. It is known for its special and fastest addition
based on design time [9], [10]. In Fig. 5 and Fig. 6, the
functional block diagram and RTL view of a 4-bit Kogge-
Stone Adder is shown. By using the ith bit of given input, the
propagate signals ‘Pi’ and generate signals ‘Gi’ are calculated.
Similarly, these generated signals produce output carry signals.
Therefore by minimizing the computation delay, Prefix Adders
are mainly classified into 3 categories.
A. Pre- processing
B. Generation of Carry Fig. 6. RTL view of kogge-stone adder

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 IV. SIMULATION RESULT
The design of approximate16 bit Wallace multiplier using
15-4 compressor has been done in HDL, using Xilinx ISE
14.5. Simulation results show the design of overall architecture
of Wallace tree multiplier as shown in Fig. 7. The parameters
of area are utilized by the multiplier design and power
consumption are obtained through simulation and tabulated in
Table I and Table II. The snapshot of delay obtained through Fig. 8. Delay analysis of 16×16bit Wallace tree multiplier
simulation is shown in Fig. 8. The processing delay at the end TABLE III
of addition level can be reduced by using kogge stone adder. DESIGN ANALYSIS OF MULTIPLIER
SI.NO Types of Area Power Delay
Multiplier (μm2) (μw) (ns)
1 16×16bit 5066.2 563.2 4.24
multiplier 0
using Accurate
15-4
compressor
2 16×16bit 5159.3 557.2 4.24
multiplier
using 15-4
compressor
with 4-bit
parallel adder
3 16×16bit 1570 420 3.125
multiplier
using 15-4
compressor
with kogge
stone adder
Fig. 7. Overall Architecture Of 16×16 Bit Wallace Tree Multiplier
The performance of 15-4 compressor based approximate
Table I and II describes the area utilization and power 16×16 multiplier is also compared with various adders at the
parameters of a 16-bit Wallace multiplier. It shows better final stage instead of Kogge stone adder. The comparative
result than other adder apart from that it gives less area and results in terms of reduced delay, area and power dissipation
low propagation delay. are tabulated in Table III.
TABLE I
DEVICE UTILIZATION OF 16×16 WALLACE TREE MULTIPLIER
V. CONCLUSION
The approximate 16×16bit Wallace tree multiplier using 15-
4 compressor architecture has been designed and synthesized
using on Spartan 3 XC3S100E board and simulated in Xilinx
ISE 14.5. The performance of proposed Multiplier with kogge
stone adder is compared with the same architecture of
multiplier using parallel adder. It can be inferred that 16×16
multiplier architecture using 15-4 compressor with kogge
stone adder is faster compared to multiplier with parallel
TABLE II adder. In future the performance of the proposed multiplier can
POWER ANALYSIS OF 16×16 WALLACE TREE MULTIPLIER be improved and applied in applications like video and image
processing.

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