20/07/2018 Vlsi Physical Design - - Unit 3 - Week 2

[email protected] ▼

Courses » Vlsi Physical Design Announcements Course Ask a Question Progress Mentor

Unit 3 - Week 2

Course
outline Week 2 Assignment
The due date for submitting this assignment has passed. Due on 2018-02-07, 23:59 IST.
How to access
the portal Submitted assignment

Week 1 1) If N denotes the number of circuit nodes, the worst-case time complexity of the Kernighan- 1 point
Lin algorithm is given by:
Week 2
O(N)
Lecture 7: O(N log2N)
Partitioning
O(N2)
Lecture 8:
O(N3)
Floorplanning

Lecture 9: No, the answer is incorrect.

Floorplanning Score: 0
Algorithms
Accepted Answers:
Lecture 10: Pin O(N3)
Assignment
2) Which of the following are true about the Kernighan-Lin algorithm? 1 point
Lecture 11:
Placement (Part
In every iteration, the pair of nodes that are swapped are locked so that they do not get
1)
swapped again in the same iteration.
Lecture 12: In every iteration, the nodes that are swapped can be swapped again in the same iteration if it
Placement (Part
leads to a reduction in cost.
2)
The algorithm can be extended to the case when the number of nodes in the partitions are
Lecture 13: unequal.
Placement (Part
3) The algorithm can be extended to the case when the nodes are of unequal sizes.

Lecture 14: No, the answer is incorrect.

Placement (Part Score: 0
4)
Accepted Answers:
Week 2 Lecture In every iteration, the pair of nodes that are swapped are locked so that they do not get swapped again in
Material the same iteration.
Quiz : Week 2 The algorithm can be extended to the case when the number of nodes in the partitions are unequal.
Assignment The algorithm can be extended to the case when the nodes are of unequal sizes.

Feedback for 3) While estimating the wire length during placement, which of the following statements are 1 point
week 2 false?
Lecture 7: Note
All the pins of a block are assumed to reside at the center, and the Manhattan distance between
Lecture 8: Note the centers of block pairs is used
to estimate the distance to increase the accuracy.
Lecture 9: Note
The exact locations of the pins are considered, and each net is modeled using some topology
Lecture 10:
and the cost calculated.
Note
For calculating the wire length between two pins, Euclidean distance is preferred to Manhattan
Lecture 11: distance.
Note
All of the above statements are false.

https://onlinecourses.nptel.ac.in/noc18_cs06/unit?unit=17&assessment=125 1/4
20/07/2018 Vlsi Physical Design - - Unit 3 - Week 2

Lecture 12: No, the answer is incorrect.

Note Score: 0

Lecture 13: Accepted Answers:

Note All the pins of a block are assumed to reside at the center, and the Manhattan distance between the cente
of block pairs is used
Lecture 14:
Note to estimate the distance to increase the accuracy.
For calculating the wire length between two pins, Euclidean distance is preferred to Manhattan distance.
Week 2 All of the above statements are false.
Assignment
Solution 4) Which of the following statements are true? 1 point

Week 3 There exists rectangular floorplans for which the dual graph may not be planar triangulated.
In the absence of cross junctions, the dual graph of a rectangular floorplan is always planar
Week 4
triangulated.
For a planar triangulated dual graph, it is always possible to find a rectangular floorplan.
Week 5
All of the above.
Week 6
No, the answer is incorrect.
Score: 0
Week 7
Accepted Answers:
Week 8 There exists rectangular floorplans for which the dual graph may not be planar triangulated.
In the absence of cross junctions, the dual graph of a rectangular floorplan is always planar triangulated.
Week 9
5) Three blocks B1, B2 and B3 are placed in a floorplan with center co-ordinates as (10,10), (20,20)
and (30,30) respectively. The numbers of
Week 10
wires connecting B1 and B2 is 5, B2 and B3 is 7, and B1 and B3 is 3. The estimated wire length
will be __________ units
Week 11

Week 12:
Hint
DOWNLOAD
VIDEOS
No, the answer is incorrect.
Supplementary Score: 0
Demo Tutorials Accepted Answers:
(Type: Numeric) 360

1 point

6) For which of the following functional blocks, the set of input lines form a set of functionally 1 point
equivalent pins?

3-input OR gate
A full adder with three inputs
3-input exclusive-OR gate
A 2-to-4 decoder

No, the answer is incorrect.

Score: 0
Accepted Answers:
3-input OR gate
A full adder with three inputs
3-input exclusive-OR gate

7) Consider a 5-terminal net with terminal co-ordinates (5,5), (7,8), (10,12), (15,3) and (12,15) 1 point
respectively. The estimated length of the net
using the complete graph topology will be:

44.8
36.2
112.0
56.0

No, the answer is incorrect.

Score: 0

https://onlinecourses.nptel.ac.in/noc18_cs06/unit?unit=17&assessment=125 2/4
20/07/2018 Vlsi Physical Design - - Unit 3 - Week 2
Accepted Answers:
44.8

8) Consider a 5-terminal net with terminal co-ordinates (5,5), (7,8), (10,12), (15,3) and (12,15) 1 point
respectively. The estimated length of the net
using the semiperimeter topology will be:

44.0
22.0
36.0
30.0

No, the answer is incorrect.

Score: 0
Accepted Answers:
22.0

9) Which of the following is true for the Timberwolf placement algorithm? 1 point

We start with an initial partition of the blocks and improve it so that the cost reduces in every
iteration.
The cost can sometimes increase across iterations.
The probability of accepting worse moves decreases as the number of iterations increases.
It generates optimal placement solutions for rectangular blocks.

No, the answer is incorrect.

Score: 0
Accepted Answers:
The cost can sometimes increase across iterations.
The probability of accepting worse moves decreases as the number of iterations increases.

10)Consider the force directed placement problem applied to a 4x4 grid. Assume that four 1 point
blocks A, B, C and D are already pre-placed on the
grid locations (0,3), (3,3), (0,0) and (3,1) respectively. A new block S is required to be placed,
where the weights with respect to the already
placed blocks are: wSA=10, wSB=4, wSC=8, and wSD=3. The zero-force target location of S
(using rounding off when required) will be:

(0,2)
(0,1)
(1,2)
(1,1)

No, the answer is incorrect.

Score: 0
Accepted Answers:
(1,2)

Previous Page End

https://onlinecourses.nptel.ac.in/noc18_cs06/unit?unit=17&assessment=125 3/4
20/07/2018 Vlsi Physical Design - - Unit 3 - Week 2

© 2014 NPTEL - Privacy & Terms - Honor Code - FAQs -

A project of In association with

Funded by

Powered by

https://onlinecourses.nptel.ac.in/noc18_cs06/unit?unit=17&assessment=125 4/4