Scribd
Upload
98 views4 pages

DLC

The document contains exam questions from past years for the course EE6301 - Digital Logic Circuits covering topics such as Boolean algebra, logic gates, flip-flops, counters, memory and VHDL. Questions test knowledge of concepts like Karnaugh maps, synchronous/asynchronous counters, cache memory, and switch-level modeling. Problems involve reducing logic expressions, designing circuits like adders and decoders, and writing VHDL code.

Uploaded by

ram
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
98 views4 pages

DLC

The document contains exam questions from past years for the course EE6301 - Digital Logic Circuits covering topics such as Boolean algebra, logic gates, flip-flops, counters, memory and VHDL. Questions test knowledge of concepts like Karnaugh maps, synchronous/asynchronous counters, cache memory, and switch-level modeling. Problems involve reducing logic expressions, designing circuits like adders and decoders, and writing VHDL code.

Uploaded by

ram
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 4

APRIL / MAY - 2018

EE6301- DIGITAL LOGIC CIRCUITS

1. State the associative property of Boolean algebra. A/M 18


2. Reduce A(A + B). A/M 18
3. Define duality property. A/M 18
4. What is a karnaugh map? A/M 18
5. What is a master-slave flip-flop? A/M 18
6. Give the comparison between synchronous and asynchronous counters. A/M 18
7. Define address and word. A/M 18
8. Why was PAL developed? A/M 18
9. Define Cache memory. A/M 18
10. Infer the concept of switch-level modeling. A/M 18

11. (a) (i) Prove that ABC+ABC’+AB’C+A’BC=AB+AC+BC. A/M 18


(ii) Convert the given expression in canonical SOP form Y=AC+AB+BC. A/M 18

(b) Designing a 4-bit Adder-Subtractor circuit. A/M 18

12. (a) Write down the steps in implementing a Boolean function with levels of AND gates. A/M 18

(b) Give the general procedure for converting a Boolean expression in to multilevel NAND diagram.
A/M 18

13. (a) Explain the operation of SR flip-flop, T flip-flop and JK flip-flop. A/M 18

(b) Explain the flip-flop excitation tables for JK flip-flop and RS flip-flop. A/M 18

14. (a) Elaborate the concept of PROM, EPROM, EEPROM in detail. A/M 18

(b) Explain the operation of bipolar RAM cell with suitable diagram. A/M 18

15. (a) Give the different arithmetic operators and bitwise operators. A/M 18

(b) Explain in detail about the principal of operation of RTL design. A/M 18

16. (a) Draw the circuit of CMOS AND gate and explain its operation. Also implement using PHDL. A/M
18

(b) Design and explain and bit shift register. Also give its truth table with its input and output waveform.
A/M 18
APRIL / MAY - 2017

EE6301- DIGITAL LOGIC CIRCUITS

1. Reduce a ( b +b c ' )+ ab '


2. Convert 14310 into its binary and binary coded decimal equivalent.
3. Write POS form of the SOP expression f ( x , y , z )=x ' yz + xy z' + xy ' z.
4. Design a Half Subtractor.
5. Give the characteristic equation and characteristic table of a T Flip Flop.
6. State the differences between Moore and Melay state machines.
7. What is a flow table? Give example.
8. State the difference between PROM, PAL and PLA.
9. Give the syntax for package declaration and package body in VHDL.
10. Write the VHDL code for a 2 X 1 multiplexer using behavioral modeling.

11. (a) (i) Design a odd-parity hamming code generator and detector for 4-bit data and explain their logic.
(ii) Convert FACE16 into binary, octal and decimal equivalent.

(b) (i) With circuit schematic explain the working of a two-input TTL NAND gate.
(ii) Compare Totem Pole and open collector outputs.

12. (a) (i) Reduce the following minterms using Karnaugh-Map


f ( w , x , y , z )=∑ m ( 0,1,2,5,6,7,8,12,14 ) + ∑ d (9,15).
(ii) Implement the following function using a suitable multiplexer f ( a ,b ,c ) =∑ m(3,7,4,5).

(b) (i) Design a 3 x8 decoder and explain its operation as minterm generator.
(ii) Design a full adder using only NOR gates.
13. (a) (i) Draw and explain the operation of a Master – Slave JK Flip Flop.
(ii) Design a 5-bit ring counter and mention its applications.
(b) (i) Design 4-bit parallel in serial out shift register using D Flip Flops.
(ii) Using partitioning minimization procedure reduce the following state table:
Present State Next state Output
W=0 w=1 Z
A B C 1
B D F 1
C F E 0
D B G 1
E F C 0
F E D 0
G F G 0
14. (a) A control mechanism for a vending machine accepts nickels and dimes. It dispense merchandise
when 20 cents is deposited ; it does not give change if 25 cents is deposited. Design the FSM that
implements the required control, using as few states as possible. Find a suitable assignment and derive
next-state and output expressions.
(b) (i) Implement the following logic and analyse for the pressure of any hazard f =x 1 x 2 + x́ 1 x 3. If
hazard is present briefly explain the type of hazard and design a hazard-free circuit.
(ii) Implement the following function using programmable logic array:
f 1 ( x , y , z )=∑m(0 , 1 ,3 , 5 , 7)
f 2 ( x , y , z )=∑m(2 , 4 , 6).
15. (a) Design a 3 bit magnitude comparator and write the VHDL code to realize it using structural
modeling.
(b) Design a 4 X 4 array multiplier and write the VHDL code to realize it using structural modeling.

16. (a) Design a CMOS inverter and explain its operation. Comment on its characteristics such as Fan-in,
Fan-out power dissipation, propagation delay and noise margin. Compare its advantages over other logic
families.
17. (b) Write the VHDL code for the given state diagram, using behavioral modeling. Design it using one-
hot state assignment and implement it using Programmable Array Logic (PAL)
NOV / DEC - 2017

EE6301- DIGITAL LOGIC CIRCUITS

1. Convert (115)10 and (235)10 to hexadecimal numbers.


2. What is a gray code and mention its advantages.
3. What is a K-map?
4. Compare decoder and demultiplexer.
5. What do you mean by race around condition in a flip-flop?
6. What is a preset table counter and ripple counter?
7. What happens to the information stored in a memory location after it has been read and write operation?
8. What is Programmable Logic Array?
9. Define modularity.
10. What are the languages that are combined together to get VHDL language?

11. (a) Explain in detail about error detecting and error correcting code.
12. (b) Write short notes on following:
(i) RTL (ii) DTL (iii) TTL and (iv) ECL

13. (a) (i) Plot the logical expression ABCD+ A

You might also like