f 'llapter 10

Stability and Frequency

Compensation

Negative feedback finds wide application in the processing of analog signals. The properties
of feedback described in Chapter 8 allow precise operations by suppressing variations of
the open-loop characteristics. Feedback systems, however, suffer from potential instability,
that is, they may oscillate.
In this chapter, we deal with the stability and frequency compensation of linear feedback
systems to the extent necessary to understand design issues of analog feedback circuits.
Beginning with a review of stability criteria and the concept of phase margin, we study
frequency compensation, introducing various techniques suited to different op amp topolo-
gies. We also analyze the impact of frequency compensation on the slew rate of two-stage
op amps.

10.1 General Considerations

Let us consider the negative feedback system shown in Fig. 10.1, where f3 is assumed
constant. Writing the closed-loop transfer function as

Y H(s)
(10.1)
X(s) = 1 + {3H(s)'

we note that if f3 H (s = jw 1) = -1, the "gain" goes to infinity, and the circuit can amplify
its own noise until it eventually begins to oscillate. In other words, if f3 H (j w1) = -1, then

X(s) H(s) t--,_...Y(s)

Figure 10.1 Basic negative-feedback

system.

345
 346 Chap. 10 Stability and Frequency Compens.11

the circuit may oscillate at frequency cv 1. This condition can be expressed as

lf3H(jcvJ)I = 1 (I 0

Lf3 H(jcvt) = -180°, (HI '

which are called "Barkhausen's Criteria." Note that the total phase shift around the loop •
cv1 is 360° because negative feedback itself introduces 180° of phase shift. The 360° phu
shift is necessary for oscillation since the feedback signal must add in phase to the origlnnl
noise to allow oscillation buildup. By the same token, a loop gain of unity (or greater) I
also required to enable growth of the oscillation amplitude.
In summary, a negative feedback system may oscillate at cv1 if (1) the phase shift around
the loop at this frequency is so much that the feedback becomes positive and (2) the lour
gain is still enough to allow signal buildup. lllustrated in Fig. 10.2, the situation can h
viewed as excessive loop gain at the frequency for which the phase shift reaches -180° 01 ,
equivalently, excessive phase at the frequency for which the loop gain drops to unity. Thu•,
to avoid instability, we must minimize the total phase shift so that for lf3 H I = 1, Lf3H Ia
still more positive than -180°. In this chapter, we assume f3 is less than or equal to unity
and does not depend on the frequency.

I Unstable Stable

'
i
20iogi~H(co>l 201og I~ H (co) I

' co (log scale) co (log scalo)

co (log scale) co (log scalo)

~(co)

(a) (b)

Figure 10.2 Bode plots of loop gain for unstable and stable systems.

The frequencies at which the magnitude and phase of the loop gain are equal to unity and
-180°, respectively, play a critical role in the stability and are called the "gain crossow1
point" and the "phase crossover point," respectively. In a stable system, the gain crossovc r ...,
must occur well before the phase crossover. For the sake of brevity, we denote the gair1
crossover by GX and the phase crossover by PX. Note that if f3 is reduced (i.e., less feedbac I
is applied), then the magnitude plots of Fig. 10.2 are shifted down, thereby moving the gau1
crossover closer to the origin and making the feedback system more stable. Thus, th(
 I!I 1 General Considerations 347

worst-case stability corresponds to f3 = 1, i.e, unity-gain feedback. For this reason, we

often analyze the magnitude and phase plots for f3 H = H.
Before studying more specific cases, let us review a few basic rules of constructing Bode
plots. A Bode plot illustrates the asymptotic behavior of the magnitude and phase of a
complex function according to the magnitude of the poles and zeros. The following two
rules are u~ed. (1) The slope of the magnitude plot changes by +20 dB/dec at every zero
frequency and by -20 dB/dec at every pole frequency. (2) For a pole (zero) frequency of
Wm, the phase begins to fall (rise) at approximately O.lwm, experiences a change of -45°
(+45°) at Wm, and approaches a change of -90° (+90°) at approximately lOwm. The key
point here is that the phase may be much more significantly affected by high-frequency
poles and zeros than the magnitude is.
It is also instructive to plot the location of the poles of a closed-loop system on a
complex plane. Expressing each pole frequency as Sp = jwp +up and noting that the
impulse response of the system includes a term exp(jwp + up)t, we observe that if sp falls
in the right half plane, i.e., if uP > 0, then the system is likely to oscillate because its
time-domain response exhibits a growing exponential [Fig. 10.3(a)]. Even if Up = 0, the
system may sustain oscillations [Fig. 10.3(b)]. Conversely, if the poles lie in the left half
plane, all time-domain exponential terms-decay to zero [Fig. 10.3(c)]. 1 In practice, we plot

}ro O'pt /
'' fro
HOp ·····)!C e~/ +O)p
II
''
''
'
... ¢> ...L3i~r-H-++++-r-~t...
---+-cr-p+i--tcr ... ¢> ---"-H-H++-H-+r~:...-t
---+----t(j
.'' ... u
-rop ·····X -rop v v

(a) (b)

jro ..
~- -· ···· +ffip
.
~l~cr-p- + - -....
cr ¢> ....-f-+++H~~_.,..t
''
'
)( ........ -ffip '
''

(c)
t.d..
~I

Figure 10.3 Time-domain response of a system versus the position of poles, (a) unstable with growing amplitude,
Ill
(b) unstable with constant-amplitude oscillation, (c) stable.
'I\

1
1<.' We ignore the effect of zeros for now.
348 Chap 10 Stability and Frequency Campen ..

the location of the poles as the loop gain varies, thereby revealing how close to oscill.,r
the system may come. Such a plot is called a "root locus."
We now study a feedback system incorporating a one-pole feedforward amplifier
suming H(s) = Ao/(1 + s/wo ), we have from (10.1),

Ao
Y (s) = 1 + .BAo (IIH
X 1+ s
wo(l + .B Ao)
In order to analyze the stability behavior, we plot I,BH(s = jw)l and L,BH(s = jt,
(Fig. 10.4), observing that a single pole cannot contribute a phase shift greater than 1)(1
and the system is unconditionally stable for all non-negative values of .B. Note that LPIl l
independent of .B.
201og lp H(ro)l

201og PA 0 t----,...

ro (log scale)

0 ro (log scale)
-45 .........
0
-90
~(ro)
Figure 10.4 Bode plots of loop gain for a one-pole
system.

Example 10.1 - - - - - - - - - - - - - - - - - - - - -.....

Construct the root locus for a one-pole system.
Solution
Equation (10.4) implies that the closed-loop system has a pole sp = -cvo(l +~Ao), i.e., a real-valnr
pole in the left ~alf plane that moves away from the origin as the loop gain increases (Fig. 10.5).
jro

Figure10.5
 I 10.2 Multipole Systems 349

10.2 Multipole Systems

Our study of op amps in Chapter 9 indicates that such circuits generally contain multiple
poles. In two-stage op amps, for example, each gain stage introduces a "dominant" pole. It
is therefore important to study a feedback system whose core amplifier exhibits more than
one pole. ,
Let us consider a two-pole system first. For stability considerations, we plot I.BHI and
L,BH as a function of the frequency. Shown in Fig. 10.6, the magnitude begins to drop at
20 dB/dec at cv = cvp 1 and at 40 dB/dec at cv = cvp 2• Also, the phase begins to change
at cv = O.lcvp 1, reaches -45° at cv = cvp 1 and -90° at cv = 10cvp1, begins to change
again at cv = 0.1cvp 2 (if O.lcvp 2 > 10cvp1), reaches -135° at cv = cvp2 , and asymptotically
approaches -180°. The system is therefore stable because I.BHI drops to below unity at a
frequency for which L.B H < -180°.

201ogi~H(co)l

ro (tog scale)

0
ro (log scale)
-90 •........
0
-180
il_tt(co)

Figure 10.6 Bode plots of loop gain for a two-pole system.

What happens if the feedback is made "weaker?" To reduce the amount of feedback,
we decrease ,8, obtaining the gray magnitude plot in Fig. 10.6. For a logarithmic vertical
axis, a change in .B translates the magnitude plot vertically. Note that the phase plot does
not change. The key point is that as the feedback becomes weaker, the gain crossover point
moves toward the origin while the phase crossover point remains constant, resulting in a
more stable system. The stability is obtained at the cost of weaker feedback.

Example 10.2 - - - - - - - - -- - - - - - - -- - - - -
Construct the root locus for a two-pole system.
Solution
Writing the open-loop transfer function as:

Ao (10.5)
H(s ) = ,
(1+ _s ) (1 + _s )
Wp! Wp 2
350 Chap. 10 Stability and Frequency Compens 11

we have

Y
- (s)
Ao
= --,--- -:---:-----:--- ( Ill J
X (1 + _s_)(1 + _s_) + .BAo
Wpl Wp2

_ AowpJWp2
( 10 ~)
- s2 + (Wpi + Wp2)S + (1 + f3Ao)WpiWp2.
Thus, the closed-loop poles are given by

-(Wpi + Wp2) ± J(Wp! + Wp2) 2 - 4(1 + f3Ao)Wp!Wp2

S! 2
. = 2 (lQ,ft\t

As expected, for .B = 0, s!, 2 = -wPr. -w p2. As f3 increases, the term under the square root dropt,
taking on a value of zero for

As shown in Fig. 10.7, the poles begin at -Wp! and -Wp2• move toward each other, coincide fnt
.B = .81. and become complex for f3 > f3t·

jro

~= 0

Figure 10.7

The foregoing calculations point to the complexity of the algebra required to construct .1
root locus for higher-order systems. For this reason, many root locus techniques have bee11
devised so as to minimize such computations (1].
We now study a three-pole system. Shown in Fig. 10.8 are the Bode plots ofthemagnitudt
and phase of the loop gain. The third pole gives rise to additional phase shift, possibly movi n~·
the phase crossover to frequencies lower than the gain crossover and leading to oscillation
Since the third pole also decreases the magnitude of the loop gain at a greater rate, !ht·
reader may wonder why the gain crossover does not move as much as the phase crossover
does. As mentioned before, the phase begins to change at approximately one-tenth of tht
pole frequency whereas the magnitude begins to drop only near the pole frequency. For tim
reason, additional poles (and zeros) impact the phase to a much greater extent than they dt 1
the magnitude.
I 0.3 Phase Margin 351

201og I~ H (ro) I

I'

ffip1 C0p2 ro (log scale)

0
-90 ...... . co (log scale)
0
-180 ···············
0
-270 ........................
~(co)

Figure 10.8 Bode plots of loop gain for a three-pole

system.

As with a two-pole system, if the feedback factor in Fig. 10.8 decreases, the circuit
becomes more stable because the gain crossover moves toward the origin while the phase
crossover remains constant.

Our foregoing study indicates that to ensure stability, I.BHI must drop to unity before Lf3H
crosses -180°. We may naturally ask: how far should PX be from GX? Let us first consider
a "marginal" case where, as depicted in Fig. 10.9(a), GX is only slightly below PX; sharp
peak for example, at GX the phase equals - 175°. How does the closed-loop system respond
in this case? Noting that at GX, ,8 H (j w1) = 1 x exp(- j 175°), we have

Y . H(jwl)
(10.10)
X (Jwl) = 1 + ,BH(jw 1)

~ exp(-j175°)
- (10.11)
1 + exp(- j175°)
1 -0.9962- j0.0872
= - · (10.12)
,8 0.0038 - j0.0872 '

and hence
y 1 1
1
X (jw ) = fi ·
0.0872 (10.13)

11.5
rv
(10.14)
""T·
352 Chap. 10 Stability and Frequency Campen·. '

IPH(co)l IPH(co)l
GX GX

PX
0 . .
0 :
-180 ··· ········ ··-~ -180° ·············-~
fl!!(co) fl!!(ro)
I; (ro)l I; (co)l
1
~~-----

co

y(t)~
~ ~
t t
(a) (b)

Figure 10.9 Closed-loop frequency and time response for (a) small and (b) large margiu
between gain and phase crossover points.

Since at low frequencies, IY j XI ~ 1/ {3, the closed-loop frequency response exhibits a sha1p
peak in the vicinity of w = w1. In other words, the closed-loop system is near oscillation
and its step response exhibits a very underdamped behavior. This point also reveals that n
second-order system may suffer from ringing although it is stable.
Now suppose, as shown in Fig. 10.9(b ), GX precedes PX by a greater margin. Then, w'
expect a relatively "well-behaved" closed-loop response in both the frequency domain and
the time domain. It is therefore plausible to conclude that the greater the spacing between G\
and PX (while GX r_emains below PX), the more stable the feedback system. Alternative!\
the phase of f3 H at the gain crossover frequency can serve as a measure of stability: 1111
smaller ILfJHI at this point, the more stable the system.
This observation leads us to the concept of "phase margin" (PM), defined as PM
180° + LfJ.H(w = w1), where w1 is the gain crossover frequency.

Example 10.3 - - - - - -- -- - - - - - - - - - - - -- -"'

A two-pole feedback system is designed such that i,BH(wp2)i = 1 and lwp!l « lwp21 (Fig. 10. 10J
What is the phase margin?
, c. 10.3 Phase Margin 353

201og I ~ H(co) I

.,, co (log scale)

co (log scale)
0
-135

~(ro)

Figure 10.10

Solution
Since Lfi H reaches -135° at w = wp2• the phase margin is equal to 45°.

How much phase margin is adequate? It is instructive to examine the closed-loop fre-
quency response for different phase margins [1]. For PM = 45°, at the gain crossover
frequency L{JH(wt) = -135° and lf3H(w 1)1 = 1 (Fig. 10.11), yielding

Y H(jw 1)
- = (10.15)
X 1 + 1 x exp(- j 135°)

I~H(ro)l
GX

0 .
co

Figure 10.11 Closed-loop frequency

response for 45° phase margin.
354 Chap. 10 Stability and Frequency Compensall1 ""

H(jw1)
(10.1 c.
0.29- 0.71}

It follows that

y 1 1
(10.1'7)
X ~ 10.29 - 0.71) I

1.3
~ -p· (10.18)

Consequently, the frequency response of the feedback system suffers from a 30% peak 81
w = wr.
It can be shown that for PM = 60°, Y(j w1) I X(j w1) = 1I f3, suggesting a negligiblo
frequency peaking. This typically means that the step response of the feedback system
exhibits little ringing, providing a fast settling. For greater phase margins, the system il
more stable but the time response slows down (Fig. 10.12). Thus, PM = 60° is typically
considered the optimum value.
The concept of phase margin is well-suited to the design of circuits that process small
signals. In practice, the large-signal step response of feedback amplifiers does not follow tho
illustration of Fig. 10.12. This is not only due to slewing but also because of the nonlinear
behavior resulting from large excursions in the bias voltages and currents of the amplifier,
Such excursions in fact cause the pole and zero frequencies to vary during the transient,
leading to a complicated time response. Thus, for large-signal applications, time-domain
simulations of the closed-loop system prove more relevant and useful than small-signal ac
computations of the open-loop amplifier.

y( t) y( t) y( t)

t t t
(a) (b) (c)

Figure 10.12 Closed-loop time response for 45°, 60°, and 90° phase margins.

As an example of a feedback circuit exhibiting a reasonable phase margin but po01

settling behavior, consider the unity-gain amplifier of Fig. 10.13, where the aspect ratio oJ ...
all transistors is equal to 50 J-Lm I 0.6 f-Lm. With the choice of the device dimensions, bias
currents, and capacitor values shown here, SPICE yields a phase margin of approximately
65° and a unity-gain frequency of 150 MHz. The large-signal step response, however, suffers
from significant ringing.
10.4 Frequency Compensation 355

v,.j

t
-. -.
Figure 10.13 Unity-gain buffer.

Frequency Compensation
Typical op amp circuits contain many poles. In a folded-cascade topology, for example,
both the folding node and the output node contribute poles. For this reason, op amps must
usually be "compensated," that is, their open-loop transfer function must be modified such
that the closed-loop circuit is stable and the time response is well-behaved.
The need for compensation arises because lf3HI does not drop to unity well before Lf3H
reaches -180°. We then postulate that stability can be achieved by (1) minimizing the
overall phase shift, thus pushing the phase crossover out [Fig. 10.14(a)];· or (2) dropping
the gain, thereby pushing the gain crossover in [Fig. 10.14(b)]. The first approach requires
that we attempt to minimize the number of poles in the signal path by proper design. Since
each additional stage contributes at least one pole, this means the number of stages must be

201og I~ H(ro) I 201og I~ H(ro) I

0 0-+-----4-___;lr---•
log ro log ro

logro log ro.

0 .
-1--~-~.--r-----..

0 0
..
•
-180 ....•.......... -180 ···················
\ illt<ro)
Modified
Design
(a) (b)

Figure 10.14 Frequency compensation by (a) moving PX out, (b) pushing GX in.
356 Chap. 10 Stability and Frequency Compen:.. ''

minimized, a remedy that yields low voltage gain and/or limited output swings (Chaplc 1 •
The second approach, on the other hand, retains the low-frequency gain and the 01111
swings but it reduces the bandwidth by forcing the gain to fall at lower frequencies.
In practice, we first try to design an op amp so as to minimize the number of poles \\II
meeting other requirements. Since the resulting circuit may still suffer from insuffit l•
phase margin, we then compensate the op amp, i.e., modify the design so as to mow 1
gain crossover toward the origin.
Let us apply the above procedures to various op amp topologies. We begin with lh
telescopic cascade op amp shown in Fig. 10.15, where a PMOS current mirror perforu~
differential to single-ended conversion. We identify a number of poles in the signal path
path 1 contains a high-frequency pole at the source of M3 , a mirror pole at node A, Rll'l
another high-frequency pole at the source of M7, whereas path 2 contains a high-frequon1t
pole at the source of M4 • The two paths share a pole at the output.

Figure 10.15 Telescopic op amp with

single-ended output.

It is instructive to estimate the relative position of these poles. Since the output resistant'
of the op amp is much higher than the small-signal resistances seen at the other node,, '''
the circuit, we expect that, even with a moderate load capacitance, the output pole, wfl·""
is the closest to the origin. Called the "dominant pole," w p,out usually sets the open-lotlp
3-dB bandwidth.
We also surmise that the first "nondominant pole," i.e., the closest pole to the onl''"
after the dominant pole, arises at node A. This is because the total capacitance at this nod1
roughly equal to Cess+ Ccs6 + CDns + 2CcD6 + CD 83 + CcD3. is typically quite larr' 1
than that at nodes X, Y, and N and the small-signal resistance of M5 , approximately 11!f.,
is relatively large.
Which node yields the next nondominant pole: N or X (and Y)? Recall from Chaplet IJ
that, to obtain a low overdrive and consume a reasonable voltage headroom, the PM<l '.
devices in the op amp are typically quite wider than the NMOS transistors. Compar" ''
M4 and M1 and neglecting body effect, we note that since g111 = 2/DI IVcs - VnJ! , ''
• I 0.4 Frequency Compensation 357

the two transistors are designed to have the same overdrive, they also exhibit the same
transconductance. However, from square-law characteristics, we have W4 / W7 = Jlp/ /ln.
which is about 1/3 in today's technologies. Thus, nodes N and X (or Y) see roughly
equal small-signal resistances to ground but node N suffers from much more capacitance.
It is therefore plausible to assume that node N contributes the next nondominant pole.
Figure 10. ~ 6 illustrates the results, denoting the capacitance at nodes A, N, and X by
CA, CN, and Cx, respectively. The poles at nodes X and Y are nearly equal and their

jw

1 cr

Figure 10.16 Pole locations fortheopamp ofFig. 10.15.

corresponding terms in the transfer functions of path 1 and path 2 can be factored out. Thus,
they count as one pole rather than two.
With the position of the poles roughly determined, we can construct the magnitude and
phase plots for fi H, using fi = 1 for the worst case. Shown in Fig. 10.17, such characteristics
indicate that the mirror pole typically limits the phase margin because its phase contribution
occurs at lower frequencies than that of other nondominant poles.
Recall from Chapter 6 that differential pairs using active current mirrors exhibit a zero
located at twice the mirror pole frequency. The circuit of Fig. 10.15 contains such a zero as
well. Located at 2wp,A. the zero has some effect on the magnitude and phase characteristics.
The analysis is left to the reader.

201og I~ H (ro) I

0-+--~~<--~~~~--~
o: ro (log scale)
8

ro (log scale)
0
-180 --------·-····
0
-270 ------------------------
0
-360
LM<w)
Figure 10.17 Bode plots ofloop gain for op amp of Fig. 10.15.
 358 Chap. 10 Stability and Frequency Compensat1o1

How should we compensate the op amp? Let us assume that the number and location u l
the nondominant poles and hence the phase plot at frequencies higher than roughly lOwp "''
remain constant. Thus, we must force the loop gain to drop such that the gain crossovt '
point moves toward the origin. To accomplish this, we simply lower the frequency of tiH
dominant pole by increasing the load capacitance. The key point is that the phase contributiou
of the do~nant pole in the vicinity of the gain or phase crossover points is close to 90
and relatively independent of the location of the pole. That is, as illustrated in Fig. 10.1 H,
translating the dominant pole toward the origin affects the magnitude plot but not the criticul
part of the phase plot.
20iog !pH (ro)l
t-1:~--,....

log co

----
0 ~~--~--~.--~--~
.
I

.......... :•
log co

•
0
-180 .......................
Figure 10.18 Translating the domi·
~(CO)
nant pole toward origin.

• In order to understand how much the dominant pole must be shifted down as well UN
arrive at an important conclusion, let us assume (1) the second nondominant pole (wp ,N )
in Fig. 10.15 is quite higher than the mirror pole so that the phase shift at w = wp,A i ~
equal to - 135° and (2) a phase margin of 45° (which is usually inadequate) is necessary
To compensate the circuit, we first identify the frequency at which the phase plot yield11
the required phase margin, in this case, wp,A· Since the dominant pole must drop the gal11
to unity at wp,A with a slope of 20 dB/dec, we draw a straight line from wp ,A toward tht
origin with such a slope (Fig. 10.19), thus obtaining the new magnitude of the dominant
pole, w~,out· Therefore, the load capacitance must be increased by a factor of Wp,our /w~. oul
From the new magnitude plot, we note that the unity-gain bandwidth of the compensated
op amp is equal to the frequency ofthe first nondominant pole (of course with a phase margw
of 45°). This is a fundamental result, indicating that to achieve a wideband in a feedbad
system employing an op amp, the first nondominant pole must be as far as possible. Fo1
this reason, the mirror pole proves undesirable.
· We should also mention that although wp,out = (R 0111 CL)- 1, increasing Rour does not
compensate the op amp. As shown in Fig. 10.20, a higher R0111 results in a greater ga111
only affecting the low-frequency portion of the characteristics. Also, moving one of tlu
nondominant poles toward the origin does not improve the phase margin. (Why?)
Now consider the fully differential telescopic cascade depicted in Fig. 10.21. In additio11
to achieving various useful properties of differential operation, this topology avoids the mu
ror pole, thereby exhibiting stable behavior for a greater bandwidth. In fact, we can ident1ly
one dominant pole at each output node and only one nondominant pole arising from nod1
X (or Y) . This suggests that fully differential telescopic cascade circuits are quite stable
·•'c. 10.4 Frequency Compensation 359

0
I' co (log scale)

0 0

0
!
:
ro (log scale)
-135 ..................... '

~({!))

Figure 10.19 Translating the domi11ant pole toward the origin

for 45° phase margin.

201ogi~H(ro)l

ro (log scale)

ro (log scale)

~(ro)

Figure 10.20 Bode plots of loop gain for higher output re-
sistance.

But how about the pole at node N (or K) in Fig. 10.21? Considering one of the PMOS
cascades as shown in Fig. 10.22(a), we may think that the capacitance at node N, CN =
Cass + CsBs + CaD? + Cvs1, shunts the output resistance of M1 at high frequencies,
thereby dropping the output impe~ance of the cascade. To quantify this effect, we first
detennine Zour in Fig. 10.22(a):

(10.19)

where body effect is neglected and ZN = r 01 ii(CNs)- 1• Assuming the first tennis much
greater than the second, we have

(10.20)
360 Chap. 10 Stability and Frequency Compensitil·

Figure 10.21 Fully differential tele-

-. scopic op amp .

IcLI 1
'= Zoutll Cls
(a) (b)

Figure 10.22 Effect of device capacitance at internal node of a

cascade current source.

Now, as illustrated in Fig. 10.22(b), we take the output load capacitance into account:

rm 1
1 (1 +8msros) rm CNS + 1 CLs
Zoutii-C = r 1 (10.21)
LS 07
(1 + 8msros) r o? CN S + 1 + -C
LS

(1 + 8mSI'os)rm
(10. 2.1!

Thus, the parallel combination of Z0111 and the load capacitance still contains a single pol<
corresponding to a time constant (1 +8msro 5 )rmCL + r o1CN. Note that (1 +8msros)ro7( t
-
.ec. 10.5 Compensation of Two-Stage Op Amps 361

is simply due to the low-frequency output resistance of the cascade. In other words, the
overall time constant equals the "output" time constant plus r07 CN. The key point in this
calculation is that the pole in the PMOS cascode is merged with the output pole, thus creating
no additional pole. It merely lowers the dominant pole by a slight amount. For this reason,
we loosely say that the signal does not "see" the pole in the cascade current sources. 2
Comparison of the circuits shown in Figs. 10.15 and 10.21 now reveals that the fully
differential 'configuration avoids both the mirror pole and the pole at node N. With the
approximation made in (10.22), the circuit of Fig. 10.21 contains only one nondominant
pole located at relatively high frequencies owing to the high transconductance of the NMOS
transistors. This is a remarkable advantage of fully differential cascade op amps.
We have thus far observed that nondominant poles give rise to instability, requiring
frequency compensation. It is possible to cancel one or more of these poles by introducing
zeros in the transfer function? For e~ample, following the analysis of Fig. 6.31, we surmise
that if a low-gain but fast path is placed in parallel with the main amplifier, a zero is created
that can be positioned atop the first nondominant pole. However, cancellation of a pole by
a zero in the presence of mismatches leads to long settling components in the step response
of the closed-loop circuit. This effect is studied in Problem 10.19.

10.5 Compensation of Two-Stage Op Amps

Our study of op amps in Chapter 9 indicates that two-stage topologies may prove inevitable
if the output voltage swing must be maximized. Thus, the stability and compensation of
such op amps is of interest.
Consider the circuit shown in Fig. 10.23. We identify three poles: a pole at X (or Y),
another atE (or F), and a third at A (or B). From our foregoing discussions, we know that
the pole at X lies at relatively high frequencies. But how about the other two? Since the
small-signal resistance seen atE is quite high, even the capacitances of M3, Ms, and M9
can create a pole relatively close to the origin. At node A, the small-signal resistance is
lower but the value of CL may be quite high. Consequently, we say the circuit exhibits two
dominant poles.
From these observations, we can construct the magnitude and phase plots shown in
Fig. 10.24. Here, wp ,E is assumed more dominant but the relative position of Wp ,E and Wp,A
depends on the design and the load capacitance. Note that, since the poles at E and A are
relatively close to the origin, the phase approaches -180° well below the third pole. In other
words, the phase margin may be quite close to zero even before the third pole contributes
signific~nt phase shift.
Let us now investigate the frequency compensation of two-stage op amps. In Fig. 10.24,
one of the dominant poles must be moved toward the origin so as to place the gain crossover
well below the phase crossover. However, recall from Section 10.4 that the unity-gain
bandwidth after compensation cannot exceed the frequency of the second pole of the open-
loop system. Thus, if in Fig. 10.24 the magnitude of wp ,E is to be reduced, the available

2 If the second term in Eq. ( 10.1 9) is included in subsequent derivations, a pole and
a zero that are nearly equal
appear in the overall output impedance. Nonetheless, for gm r o » I and CL > CN, their effect is negligible.
362 Chap. 10 Stability and Frequency Compensat1

~------~------~------~ Voo

•'

-.
-.
Figure 10.23 Two-stage op amp.

201og I~H(ro)l

0
-1--.!-~---l'-l----'-"""---ro_..(log scale)
8 8

ro (log scale)
0
-180 ..............
0
-270 ·························
~{ro)

Figure 10.24 Bode plots ofloop gain of two-stage op amp.

bandwidth is limited to approximately wp,A• a low value. Furthennore, the very small
magnitude of the required dominant pole translates to a very large compensation capacitor. .....
·Fortunately, a more efficient method of compensation can be applied to the circuit of
Fig. 10.23. To arrive at this method, we note that, as illustrated in Fig. 10.25(a), the first
stage exhibits a high output impedance and the second stage provides a moderate gain,
thereby providing a suitable environment for Miller multiplication of capacitors. Shown in
Fig. 10.25(b), the idea is to createalargecapacitanceatnode E, equal to (1 +Au2)Cc,moving
the corresponding pole to R;u~ 1[ c E + (1 + Av2)Ccr 1' where c E denotes the capacitance
at node E before Cc is added. As a result, a low-frequency pole can be established with a
moderate capacitor value, saving considerable chip area. This technique is called "Miller
compensation."
rH 10.5 Compensation of Two-Stage Op Amps 363

Av1 Av2
A A

(a) (b)

Figure 10.25 Miller compensation of a two-stage op amp.

In addition to lowering the required capacitor value, Miller compensation entails a very
important property: it moves the output pole away from the origin. Illustrated in Fig. 10.26,
this effect is called "pole splitting." To understand the underlying principle, we simplify
the output stage of Fig. 10.23 as in Fig. 10.27, where Rs denotes the output resistance of
the first stage and Rr = r o9llr 011 • From our analysis in Chapter 6, we note that this circuit
contains two poles:

1
23
WpJ ~ Rs[(l + 8m9Rr)(Cc + Cavg) + CE] + RL(Cc + CaD9 + Cr) (10. )

Wp ~ Rs[(l +8m9Rr)(Cc + CaD9) + CE] + Rr(Cc + CaD9 + CL) . (10. )

2 24
RsRd(Cc + CaD9)CE + (Cc + CaD9)Cr + CECL)]

These expressions are based on the assumption lwp!l « lwp2 l. Before compensation,
however, wp 1 and wp2 are of the same order of magnitude. For Cc = 0 and relatively large
Cr. we may approximate the magnitude of the output pole as Wp2 ~ 1/ (RLCL).

j(J) }ro
Before
Compensation After
Compensation

Figure 10.26 Pole splitting as a result of Miller compensation.

Figure 10.27 Simplified circuit of a

two-stage op amp.
 364 Chap. 10 Stability and Frequency Compensalu

To compare the magnitudes of wp 2 before and after compensation, we consider a typ1l

case: Cc + CcD9 » C£, reducing (10.24) to wp2 R:: 8m9/(CE + CL). Noting that typical!
CE « CL· we conclude that Miller compensation increases the magnitude of the outp '
pole by roughly a factor of 8m9 RL, a relatively large value. Intuitively, this is becausl' ,,
high frequencies, Cc provides a low impedance between the gate and drain of M 9 , reduciu,
the resistance seen by CL from RL to roughly Rsiig,~~II RL R:: g,~~·
In summary, Miller compensation moves the interstage pole toward the origin ami
the output pole away from the origin, allowing a much greater bandwidth than that oh
tained by merely connecting the compensation capacitor from one node to ground. In
practice, the choice of the compensation capacitor for proper phase margin requires somr
iteration.
Our study of stability and compensation has thus far neglected the effect of zeros of thl'
transfer function. While in cascade topologies, the zeros are quite far from the origin, in
two-stage op amps incorporating Miller compensation, a nearby zero appears in the circuit
Recall from Chapter 6 that the circuit of Fig. 10.27 contains a right-half-plane zero nl
Wz = 8m9/(Cc +Ccvg). This is because Cc + Ccv9 forms a "parasitic" signal path from
the input to the output. What is the effect of such a zero? The numerator of the transfer
function reads (1- sfwz), yielding a phase of- tan- 1(w fwz), a negative value becaUSCI

• Wz is positive. In other words, as with poles in the left half plane, a zero in the right half'
plane contributes more phase shift, thus moving the phase crossover toward the origin,
Furthermore, from Bode approximations, the zero slows down the drop of the magnitude,
thereby pushing the gain crossover away from the origin. As a result, the stability degradoM
I considerably.
To better understand the foregoing discussion, let us construct the Bode plots for a third·
order system containing a dominant pole wp 1, two nondorninant poles Wp2 and Wp3• and 11
zero in the right half plane Wz. For two-stage op amps, typically lwptl < iwz I < lwp21· A'
shown in Fig. 10.28, the zero introduces significant phase shift while preventing the gain
from falling sufficiently.

201og IPH (ro) I

ro (log scale)
0
-180 ............

~(ro)
0
-270 .............. ..
r
Figure 10.28 Effect of right half plane zero.
.,.r. 10.5 Compensation of Two-Stage Op Amps 365

The right half plane zero in two-stage CMOS op amps, given by gmf(Cc +CoD), is a
serious issue because gm is relatively small and Cc is chosen large enough to position the
dominant pole properly. Various techniques of eliminating or moving the zero have been
invented. illustrated in Fig. 10.29, one approach places a resistor in series with the com-

Figure 10.29 Addition of R, to move

the right half plane zero.

pensation capacitor, thereby modifying the zero frequency. The output stage now exhibits
three poles, but for moderate values of R, the third pole is located at high frequencies and
the first two poles are close to the values calculated with Rz = 0. Moreover, it can be shown
(Problem 10.8) that the zero frequency is given by

1
(10.25)

Thus, if R, ~ g;~. then w, ,:::: 0. While R, = g;~ seems a natural choice, in practice we
may even move the zero well into the left half plane so as to cancel the first nondominant
pole. This occurs if

1 -gm9
(10.26)
Cc (g,~~ - Rz) - CL + CE '

that is,

CL + Ce + Cc
Rz= - - - - - (10.27)
gm9Cc
CL +Cc
~--- (10.28)
gm9Cc '

because Ce is typically much less than CL + Cc .

The possibility of canceling the nondominant pole makes this technique quite attractive,
but in reality two important drawbacks must be considered. First, it is difficult to guarantee
the relationship given by (10.28), especially if CL is unknown or variable. For example, as
explained in Chapter 12, the load capacitance seen by an op amp may vary from one part of
the period to another in switched-capacitor circuits, necessitating a corresponding change in
Rz and complicating the design. The second drawback relates to the actual implementation
of Rz. Typically realized by aMOS transistor in the triode region (Fig. 10.30), Rz changes
366 Chap. 10 Stability and Frequency Compensatt• '

•'

Figure 10.30 Effect of large output

': swings on Rz.

substantially as output voltage excursions are coupled through Cc to node X, thereby

degrading the large-signal settling response.
Generating Vb in Fig. 10.30 is not straightforward because Rz must remain equal to (1 ~
CL/ Cc )g,";;~ despite process and temperature variations. A common approach is illustrated
in Fig. 10.31 [2), where diode-connected devices M 13 and M14 are placed in series. It
It is chosen with respect to ID9 such that Yast3 = Vos9, then Vasts = Vost4· Sinco
gml4 = JLpCox(WI L)t4(Vost4- VTH14) and Ron15 = [JLpCox(W I L)ts(Vost5- VTHis)r 1,
we have Ronl5 = g,";;f4(W I L)t4I(W I L)t5· For pole-zero cancellation to occur,

-1 (WIL)t4- -1
gml4(WIL)t5 - gm9
(t + CL)
Cc '
(10.29)

and hence

&.
D9
(WI L)ts = y'(WI L)t4(WI L)9 - - C
Cc
C .
1Dl4 C + L
(10.30)

If CL is constant, (10.30) can be established with reasonable accuracy because it contain11

only the ratio of quantities.
Another method of guaranteeing Eq. (10.28) is to use a simple resistor for Rz and de
fine gm9 with respect to a resistor that closely matches Rz [3). Depicted in Fig. 10.32,
this technique incorporates Mb 1-Mb4 along with Rs to generate lb ex K/ . (This circuit
is studied in detail in Chapter 11.) Thus, gm 9 oc JTD9 oc ~ oc R-; 1• Proper ratio
ing of Rz and Rs therefore ensures (10.28) is valid even with temperature and proces~
variations.

Figure 10.31 Generation of Vb for

-. proper temperature and process tracking.
" 10.5 Compensation of Two-Stage Op Amps 367

~--------~----~----~~Voo

,,

Figure 10.32 Method of defining gm9 with respect to

Rs.

The principal drawback of the two methods described above is that they assume square-
law characteristics for all of the transistors. As described in Chapter 16, short-channel
MOSFETs may substantially deviate from the square-law regime, creating errors in the
foregoing calculations. In particular, transistor M9 is typically a short-channel device be-
cause it appears in the signal path and its raw speed is critical.
An attribute of two-stage op amps that makes them inferior to "one-stage" op amps is the
susceptibility to the load capacitance. Since Miller compensation establishes the dominant
pole at the output of the first stage, a higher load capacitance presented to the second
stage moves the second pole toward the origin, degrading the phase margin. By contrast,
in one-stage op amps, a higher load capacitance brings the dominant pole closer to the
origin, improving the phase margin (albeit making the feedback system more overdamped).
Illustrated in Fig. 10.33 is the step response of a unity-gain feedback amplifier employing
a one-stage or a two-stage op amp, suggesting that the response approaches an oscillatory
behavior if the load capacitance seen by the two-stage op amp increases.

Cc

-. -.
.·······=··--
'.
..
..
t t
Figure 10.33 Effect of increased load capacitance on step response of one- and
two-stage op amps.
 374 Chap. 10 Stability and Frequency Compens;''''

capacitances and assuming)... = y = 0, compute the phase margin of the circuit. (Hint: b1'
the loop at node X.)
10.6. In Problem 10.5, what is the phase margin if Rv is increased to 2 kQ?
10.7. If the phase margin required of the amplifier of Problem 10.5 is 45°, what is the maxiunu
value of (a) Cr, (b) CA, (c) Cx while the other two capacitances remain constant?
10.8. Pr0ve that the zero of the circuit shown in Fig. 10.29 is given by Eq. (10.25). Apply th
technique illustrated in Fig. 6.15.
10.9. Consider the amplifier of Fig. 10.42, where (WI L)I-4 = 5010.5 and Iss = h = 0.5 rnA

• Figure 10.42
(a) Estimate the poles at nodes X and Y by multiplying the small-signal resistance
capacitance to ground. Assume Cx == Cy = 0.5 pF. What is the phase margin f01
and

unity-gain feedback?
(b) If Cx = 0.5 pF, what is the maximum toleral:lle value of Cy that yields a phase margin
of 60° for unity-gain feedback?
10.10. Estimate the slew rate of the op amp of Problem 10.9(b) for both parts (a) and(~).
10.11. In the two-stage op amp of Fig. 10.43, WIL = 5010.5 for all transistors except for Ms,6, fm '
which WI L = 6010.5. Also, Iss = 0.25 rnA and each output branch is biased at 1 rnA.

-. -. -.
Figure 10.43
(a) Determine the CM level at nodes X andY.
(b) Calculate the maximum output voltage swing.
(c) If each output is loaded by a 1-pF capacitor, compensate the op amp by Miller mul11
plication for a phase margin of 60° in unity-gain feedback. Calculate the pole and zero
positions after compensation.
11Jiems 375

(d) Calculate the resistance that must be placed in series with the compensation capacitors to
position the zero atop the nondorninant pole.
(e) Detennine the slew rate.
10.12. In Problem 10.11 (e), the pole-zero cancellation resistor is implemented with a PMOS device
as in Fig. 10.31 . Calculate the dimensions of M13-M1s if Ir = 100 JJ,A.
10.13. Cakqlate the input-referred thermal noise voltage of the op amp shown in Fig. 10.43.
10.14. Figure 10.44 depicts a transimpedance amplifier employing voltage-current feedback. Note
that the feedback factor may exceed unity because of M3. Assume /1- [J are ideal, It = [z =
1 rnA, lJ = 10 JJ,A, (WI L)t,2 = 5010.5, and (WI Lh = 510.5.

-.

-. Figure 10.44
(a) Breaking the loop at the gate of M3, estimate the poles of the open-loop transfer function.
(b) If the circuit is compensated by adding a capacitor Cc between the gate and the drain
of M1, what value of Cc achieves a phase margin of 60°? Determine the poles after
compensation.
(c) What resistance must be placed in series with Cc to position the zero of the output stage
atop the first nondominant pole?
10.15. Repeat Problem 10.14(c) if the output node is loaded by a 0.5-pF capacitor.
10.16. Suppose in the circuit of Fig. 10.44 a large negative input current is applied such that M1
turns off momentarily. What is the slew rate at the output?
10.17. Explain why in the circuit of Fig. 10.44, the compensation capacitor should not be placed
between the gate and the drain of M2 or M3.
10.18. Determine the input-referred noise current of the circuit shown in Fig. 10.44 and described
in Problem 10.14(c).
10.19. The cancellation of a pole by a zero, e.g., in a two-stage op amp, entails an issue called
the "doublet" problem [5, 6]. If the pole and the zero do not exactly coincide, we say they
constitute a doublet. The step response of feedback circuits in the presence of doublets is of
great interest. Suppose the open-loop transfer function of a two-stage op amp is expressed as

(10.44)
Hope11 (s) = ( 1 + _s ) (
1
+ _s ) .
WpJ Wp2

Ideally, Wz = wp2 and the feedback circuit exhibits a first-order behavior, i.e., its step response
contains a single time constant and no overshoot.
376 Chap. 10 Stability and Frequency Com pens. 111

(a) Prove that the transfer function of the amplifier in a unity-gain feedback loop is giVlll '

(b) Determine the two poles of Hciosed(s), assuming they are widely spaced.
(c) Assuming Wz ~ WpZ and WpZ « (1 + Ao)WpJ, write Hciosed(s) in the fonn

Hciosed(S) =( s ) ( s ) •
1+- 1+-
WpA WpB

and determine the small-signal step response of the closed-loop amplifier.

(d) Prove that the step response contains an exponential tenn of the form (1 - wzfw~J)
exp( -wpzt). This is an important result, indicating that if the zero does not exactly can~tl
the pole, the step response exhibits an exponential with an amplitude proportional ltl
1- wz/wpz (which depends on the mismatch between Wz and Wp2) and a time const1nl
of 1/wz.
10.20. Using the results of Problem 10.19(d), determine the step response of the amplifier descrlbf4
in Problem lO.ll(e) with (a) perfect pole-zero cancellation, (b) 10% mismatch between tl
pole and the zero magnitudes.

References
1. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits, Third Ed., Nr\1
York: Wiley, 1993.
2. W. C. Black, D. J. Allstot, and R. A. Reed, "A High Performance Low Power CMOS Chann1l
Filter," IEEE J. of Solid-State Circuits, vol. 15, pp. 929-938, Dec. 1983.
3. R. M. Ziazadeh, H.-T. Ng, and D. J. Allstot, "A Multistage Amplifier Topology with Embed1~1
Tracking Compensation," CICC Proc., pp. 361-364, May 1998.
4. B. K. Ahuja, "An Improved Frequency Compensation Technique for CMOS Operational Ampll
tiers," IEEE J. of Solid-State Circuits, vol. 18, pp. 629-633, Dec. 1983.
5. P.R. Gray and R. G. Meyer, "MOS Operational Amplifier Design-A Tutorial Overview," /HI./
J. of Solid-State Circuits, vol. 17, pp. 969-982, Dec. 1982.
6. B. Y. Kamath, R. G. Meyer, and P. R. Gray, "~elationship between Frequency Response 111111
Settling Time of Operational Amplifiers," IEEE J. of Solid-State Circuits, vol. 9, pp. 347-J~ J
Dec. 1974.