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Arithmetic Logic Unit Technical Memo

This technical memo describes the design of a 16-bit arithmetic logic unit (ALU) using Verilog code. The ALU performs operations like addition, subtraction, logical operations on two 16-bit inputs and provides flags to indicate outputs. The author faced some difficulties in implementing rotate operations but was able to design a combinational ALU that passes all tests in the provided test bench. Verification was done through software simulation and the ALU design could benefit hardware applications.

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Christy George
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189 views6 pages

Arithmetic Logic Unit Technical Memo

This technical memo describes the design of a 16-bit arithmetic logic unit (ALU) using Verilog code. The ALU performs operations like addition, subtraction, logical operations on two 16-bit inputs and provides flags to indicate outputs. The author faced some difficulties in implementing rotate operations but was able to design a combinational ALU that passes all tests in the provided test bench. Verification was done through software simulation and the ALU design could benefit hardware applications.

Uploaded by

Christy George
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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ARITHMETIC LOGIC UNIT

Technical Memo

Prepared by
Christy Christy
8584799

Introduction
My name is Christy and I work in your company as Hardware Engineer, When I was going through the
projects list for outsourcing I saw one project called “16 bit ALU using Verilog code” and the expense
that can incur to our company I strongly felt to write this document to you.

16 bit ALU using Verilog code is not a complex design to be implemented and I have already done a
design work which passes almost all conditions of your proposed test bench. In this document I will
explain all the procedures and difficulties I faced when I was implementing this design.

What is ALU?

The Arithmetic Logic Unit is the fundamental central processing unit that performs tasks like addition,
subtraction, division, multiplication and logical operations like INVERT,AND,OR,XOR,SHIFT LEFT,SHIFT
RIGHT,ROTATE LEFT etc. Generally, all mathematical and logical operations for the processor occur in
this hardware.

DESIGN OBJECTIVE/PURPOSE
There is two 16 bit data buses ABUS and BBUS and one select line which is of 4 bits ,according to the
input at select line desired operation is performed between two inputs ABUS and BBUS

There are total 4 Inputs ABUS,BBUS,FSEL,CIN in this FSEL is a 4 bit variable which selects different
operations to perform for the ALU.CIN is the Carry in.

There are total 5 output lines FOUT which is also 16bit,C,Z,S,V

C-Carry Flag, Asserted when the ALU operations generates a carry

Z-Zero Flag Asserted when the ALU output is all Zero

S-Sign Bit Asserted when the ALU output is negative

V-Overflow flag Asserted when the ALU output has been overflowed

We need to save these flags in registers so that the previous state of the flags are stored can be utilized
with efficiency.

S-It is a copy of the MSB of FOUT

Z-Is 1 when Fout is 0

C-Is 1 when there is carry out from any operation

V-Is ‘1’ when there is an overflow condition present after an operation

The ALU which I implemented is combinational


Certain Conditions

Outputs are declared as reg inorder to written into

Temp variable is used to read from the output indirectly

There are two reserved codes

S.no Input value of FSEL operation


1 0000 Transfer Abus
2 0001 ABUS+1
3 0010 ABUS-1
4 0011 ABUS+BBUS+Cin
5 0100 ABUS-BBUS-Cin
6 0101 ABUS & BBUS
7 0110 ABUS | BBUS
8 0111 ABUS ^ BBUS
9 1000 ~ABUS
10 1001 <<ABUS
11 1010 >>BBUS
12 1011 >>>ABUS
13 1100 ROL through
Carry
14 1101 ROR through
Cary
15 1110 Reserved
16 1111 Reserved

Each operation is having a 4 bit value and the 4 bit value is assigned to different variables as follows

TSA =4'b0000,

INC =4'b0001,

DEC=4'b0010,

ADD=4'b0011,

SUB=4'b0100,

AND=4'b0101,

OR=4'b0110,

XOR=4'b0111,
NOT=4'b1000

SHL=4'b1001,

SHR=4'b1010,

ASR=4'b1011,

RLC=4'b1100,

RRC=4'b1101,

RSV1=4'b1110,

RSV2=4'b1111

These functions can be implemented by using a case statement by checking FSEL value

According to the FSEL value different operations will be performed and stored in a temporary variable
temp.

When the program comes out of case statement value at temp is assigned to FOUT.

Implementation Method

I will be using model sim 10.5 version to design and simulate the code.

Verification and Validation

There is a test bench which checks all the functions which is to be implemented and also displays the
failed operations and passed operations. This can also be checked by using a FPGA kit.

Software check is the most efficient way as it checks all the operations at a time.

I run the code and it passes all the conditions for the test bench and works perfect.

Benefit Assumptions Risks/Issues:

Reading the output at first was difficult and the use of temporary variable helped in this.

Use of case statement was very efficient as the code readability and program speed has also been
increased.

Rotate left with carry and ,Rotate right with carry was bit difficult to implement as it was not a direct
operation a bit of thinking and logic was required here.
Resources and reference section

https://conestoga.desire2learn.com/d2l/le/content/325226/viewContent/6785687/View

https://conestoga.desire2learn.com/d2l/le/content/325226/viewContent/6785686/View

https://www.researchgate.net/publication/271646895_Simulation_of_Arithmetic_Logic_Unit_and_Impl
ementation_using_FPGA

https://forums.xilinx.com/t5/General-Technical-Discussion/rotate-right-in-verilog/td-p/755517

http://robotics.ee.uwa.edu.au/courses/design/examples/example_design.pdf

http://www.ijeast.com/papers/30-34,TESMA302,IJEAST.pdf

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