Design & Verification of FIFO

Mohini Akhare1, Dr. Nitin Narkhede2

1
PG Scholar, 2Professor
Department of Electronics Engineering, Mtech VLSI Design, Shri Ramdeobaba College of Engineering &
Management (RCOEM), Nagpur, India
[email protected], [email protected]

Abstract:- In this paper, synchronous FIFO is Full and empty signals are used by the logic to
designed using Verilog and then after designing strangle the transmitter and receiver respectively,
this FIFO design under test kept for verification in order to avoid these critical conditions. The Fig.
using System Verilog coding technique. As the 1 shows the functionality of the FIFO. We can
designing of modules get bigger it is becoming represent the FIFO as a pipe that means we can
more difficult to check that design as it takes imagine a FIFO as a pipe where the first element
entering into the pipe is the first element that
longer time to check all the combinations of design
output from the pipe [4].
inputs. This problem can be solved by adding
assertions and cover group. So by putting This paper describes the implementation of
assertions and adding cover groups we can constrained random test stimuli, functional
increase the coverage of code. In this paper we are coverage, also describes an approach for creating
checking code coverage, functional coverage and test cases that allow the use of both constrained
assertion coverage. random tests within a single environment. The
Keywords: Verification, Synchronous FIFO, environment built should also have the capability
Functional coverage, Assertions to be easily modified where a Device under Test
(DUT) of similar structure can be verified. With this
in mind the main goal is to develop a new and
I. Introduction more effective intuitive way of designing test
benches [5]. The more capable verification tools
Nowadays, testing as a word has been substituted must be used, as circuits become more complex.
with check. Confirmation specialists need to This verification should takes place much earlier
guarantee what goes to the plant for assembling is than the fabrication process. In this paper a
an exact representation of the specification of verification environment is comprehend and
configuration [1]. The modem, systematic and implemented which may detect the maximum
automated approaches has been required because errors for proper functioning of the synchronous
of the continuous growth and complexity for FIFO model.
creating test benches [2], given that up to 70% of
the design period is spent in the authentication
process [3], it has become even more critical that
verification engineers design test benches that are
at the advanced of the verification industry.

The FIFO (First in First Out) is a genus of

memory that is ordinarily used to holds the
information, has to utilize consistently between Figure 1:- Functional diagram of FIFO
various systems at distinct deferrals. The FIFO
model permits the transmitter to send
information, while the collector is in not
functioning stage. The data or information is filled II. Design and Working
the FIFO memory until the recipient starts
emptying it. An overflow occurs as soon as the Here we have taken the synchronous FIFO for
transmitter fills up the FIFO model and attempts to designing. The synchronous FIFO consists of dual
store more data before the receiver has read the port RAM, write logic, read logic. Dual-port RAM or
data out. An underflow occurs when the receiver DPRAM is a type of RAM that allow multiple reads
attempts to read data from the FIFO structure, but and writes in chorus at unlike addresses. In this
the transmitter did not fed any data into it. The
design the write operation is accessed through memory data is read out from the Read control
port 1 where as read operation is accessed logic block. This program steps forward when the
through port 2. The basic block diagram which read enable signal and the read select signal of the
demonstrates the architecture of FIFO mode has block are high. Whenever there is unavailability for
been shown in Fig. 2. This Design consists of the writing data in the FIFO, FULL signal goes high and
Dual Port RAM, Read control logic and Write indicates that the memory is full and there is no
control logic blocks. Here the memory arrays with space for writing further data. The EMPTY signal
the help of flip flops can also be implemented as a indicates that there is no single data filled in the
substitute of dual port RAM but to keep the design memory and vacant locations are available in the
simple dual port RAM has been chosen. memory. Whenever any single data will get into
Instantaneous access is provided to read and write the memory, EMPTY signal goes low.
ports by this dual port RAM i.e. Read and Write
operations can be performed simultaneously. The
limitation with this design is that Read and Write
operations cannot take place from the same
memory location.

Figure 3:-Block diagram of Dual port RAM

The functionality of the dual port RAM can be

articulated with three conditions, the first
condition transpire when the reset signal is high
and all the output signals i.e. output data (d_out),
Figure 2:- Block Diagram of FIFO write pointer (w_ptr), read pointer (r_ptr) and
status counter (s_cnt) reset to zero value. The next
So the key role of dual port RAM element has been condition occur when write enable (w_e) signal is
to write and read the data simultaneously but not high and the incoming input data (d_in) is written
at the same memory location. This particular type in the memory block with the write addresses
of RAM has two unidirectional data ports, an input generated by the write pointer.But this will take
port for writing data and an output port for the place only on the next rising edge of the clock. The
reading data where each port is assigned to have
write enable signal is only generated when the
their own data and address buses. The
FIFO is not full so as to avoid corruption of data.
write port has signals named write chip
select and write enable (wr_cs_1, The third stage show up when read enable (r_e)
wr_en_1) to allow writing of the data. The signal is high, then the data that is written in the
read port has signals known as read chip memory is read out form the memory. The read
select and read enable (rd_cs_2, rd_en_2) pointer will generate the read address through
to enable the data output. The dual port RAM which the data can be read, this stage also can
which is examined in this paper is synchronous and only exists at the next rising edge of the clock. The
has a single clock for both ports, as depicted in Fig Read enable signal is only generated when the
3. At the rising or positive edge of clock both the FIFO is not empty so that any corrupted data could
reading and writing of data has been occurred. not be read out from the memory.

The synchronous FIFO has an exclusive clock In the presented Fig. 2, the block on the left
port for both the Read and Write operations. The side is the Write control logic block. This block is
data which is given on the data input port is used to control the write operation of the
written on the next empty location. This happens implemented FIFO design. The block basically
only on the positive edge of the clock, when write generates a binary coded write pointer and this
enables and the write select signals of the write pointer gets incremented by one location every
control logic block are high. Then the written
time, the input data is written into the design. write and reset transactions are done in the Driver
Also, this block generates a full signal to avoid block itself. Each implemented transaction will
overwriting a data in the memory block. The block generate a test case that is a random data which
on the right side is the read control logic block, this will initiate by the driver and given to the DUT to
block is used to control the read operation of the perform the specific operation utilizing the
implemented FIFO design. The subunit generates a functioning of the incoming signals. The driver is
the block that deciphers the transactions in to
binary coded read pointer which gets incremented
random inputs i.e. test cases. These are given to
by one location every time, the written data is read
the DUT and the DUT performs specific operation
from the design. Also, this block generates an depending upon the input given. The transaction
empty signal such that no invalid data can be read generator generates a high level transaction like
from memory. The verification phase is most read, write or reset. The driver basically converts
significant step for any successful design. these transactions into actual inputs. A driver gets
the information from the generator and drives it to
III. Verification Process the DUT by inspecting and driving the DUT signals
[10]. It contains the hidden validation to drive the
pins of the DUT as indicated by situation gave to it
The verification plan must consist of the entire from the sequencer.
verification process [6] and formation of a good
plan will save a lot of tedious and unprofitable
time later. The whole plan should include the time
for the completion of process as well as the
authentication of the coverage result [7]. The
verification planning are growing in a speedy
manner hence it becomes more and more
competently requirements to create a good plan
before the verification has been finally started [8].
The theory about verification planning has been
reported in a well organised and systematic
manner [9], which proposes a five-day approach Figure 4:- Verification plan
for the complete verification planning process.
The scoreboard is used to record the
operations of the driver and then displays these
The Block diagram of the verification plan has operations systematically. A screen, a distant
been shown in Fig. 4 and all its components are commodity, is just to monitor the examples of the
explained in this section. The very first component DUT signals [11] but cannot be used to drive them.
comes under verification environment is A monitor collects information, extracts occasions,
Transactor. Transaction class is used to declare performs checking, scope and optionally prints
fields required generating the stimulus, so first follow data. It utilized the screen to sign sent to
step is to declare the 'Fields' in the transaction the pins of the DUT from the driver. As the name
class. Different transactions depending on the test suggests, it basically monitors the operations
case configurations field selection has been performed by the driver and then it passes its data
generated in the transaction class. For the FIFO to the scoreboard to display the information. The
design which has to be implemented, the scoreboard can also be named as tracker as it
transactions are RESET, WRITE and READ tracks all the operations. The dynamic data types
operations and the fields which has been declared and dynamic memory allocation makes the task
here are d_in, w_s, w_e, r_s, r_e, full, empty, much easier to implement scoreboard in the
d_out. Also the input signals (w_s, w_e, r_s, r_e) system Verilog. Normally, a scoreboard confirms
are randomized so that to drive Random stimulus whether there has been fitting operation of the
to DUT by changing the characteristics of data. configuration at a practical level. The Scoreboard
basically stores the data and address when the
After Transactor, Generator class comes which write operation is done and displays the results.
is responsible for, Generating the stimulus by Furthermore, it also records the data and
randomizing the transaction class & sending the addresses that had been previously read. It
randomized class to driver. Using the above matches the similarity of the data and display the
environment, the transaction generator is defined outcome [1].
within the Driver block i.e. the coding to the read,
 Further the Environment class comes which is
a container class contains Mailbox, Generator and
Driver. It creates the mailbox, generator and
driver, shares the mailbox handle across the
Generator and Driver. Then Test class is present
which is responsible for creating the environment.
Also it configures the testbench i.e. setting the
type and number of transactions to be generated
as well as initiate the stimulus driving. The
Interface block is one of the essential modules
throughout the verification plan. In this particular
block all the commonly used signals in both the
design and the verification environment. The Figure 5:- The Reset Condition
interconnect block bridge as an interfaced to the
design under-test and the check environment. The This status has forced the value 1 as such that all
interface assimilates all the pin-level associations the output signals would be reset to zero. The
that are made to the DUT [12]. Basically an output signals d_out, rd_ptr, wr_ptr and the s_cnt
interface is a bundle of nets or variables. The are set to zero.
coverage collector mainly covers the coverage
related issues of the block. This block has covers
the groups and cover points that are used to
estimate the functional coverage of the design.
Assertions has been inserted which helps to
shorten the time to debug. Assertions are very
handy and highly useful asset when we talk about
Functional Verification i.e. finding the bugs in the
given RTL design & ensuring Verification
completeness.

IV. Design Outcomes and Figure 6:- Write Condition Waveform

Analysis The Fig. 6 shows the scenario in which all data
is written in the FIFO through waveform
Initially the outcomes embraced of the Reset, Read generated by the Questa Sim tool. As exhibited in
and Write condition results. Fig. 5 illustrates the the figure the first signal is the clock signal that is a
scenario in which all the output signals are reset to free running signal. All other signals will change
zero which is shown with the help of waveform the values on the rising edge of the clock. The
generated in the Questa Sim tool. reset signal in this case has forced to zero. The
depth of the memory is 8 i.e. up to eight locations
As reported in the waveform the initial signal is FIFO can write the data in the memory. The data is
the clock signal. This is a free running signal and all given on the d_in signal (00001000). This data is
other signals will have to change their values only the input data that is given in the FIFO memory.
on the rising edge of this signal. The next signal is The w_s and w_e signals are also set to 1, to
the reset signal this is the signal that dictates the activate the write control logic of the design. This
reset condition for all other signals. block is responsible for writing the data in the
memory. The FIFO full signal becomes 1 as the
FIFO memory is filled with all the locations of
memory and no space has been available to write
more data. The w_ptr which is write pointer signal
has been binary coded, gets incremented as it goes
on filling the memory locations. As many times the
rising edge of the clock is coming, the w_ptr gets
incremented and the incoming data gets written
into the FIFO memory on that write pointer
location.
 Figure 8:- Coverage Report

Initially the code includes, the type of cover groups

to screen the stimuli being put on the DUT. The
Figure 7:- Read Condition Waveform responses and reaction to the stimuli are
additionally checked to figure out what usefulness
The Fig. 7 configured the scenario in which the has been worked out. The cover groups ought to
incoming data is read out from the FIFO. As be indicated in the plan of verification. Inside a
depicted through the waveform, the first signal is scenario of test, their handiness is learned by
the clock signal as convoluted in the write status dissecting the RTL code and comprehension of the
explanation. The data that was written in the data. The cover points turn out to be all the more
memory (00001000) with the help of d_in signal is capable inside the recreation when they are
now read out form the FIFO memory. The r_s and crossed together to inside recognize more
r_e signals are set to 1 so to activate the read noteworthy levels of reflection of an outline. The
control logic of the design. This block is cover groups give an effective and valuable system
fundamentally responsible for reading data from in distinguishing zones of useful scope inside of a
the memory. The FIFO empty signal is 1 and FIFO configuration [14]. The coding portion of the
full signal becomes 0 in this circumstances as the coverage report has been given below:
FIFO is not full in this scenario. In this case, now
the r_ptr that is the read pointer signal gets covergroup cg@(posedge clk);
incremented by 1 value. Now the read pointer will
traverse through all those locations on which the cover_point_d_in : coverpoint
data was written by the write pointer. When all d_in;
the data written would be read out then the FIFO cover_point_w_s : coverpoint w_s;
will again be completely empty. The written data is cover_point_w_e : coverpoint w_e;
read out from the FIFO with the help of d_out cover_point_r_s : coverpoint r_s;
signal. cover_point_r_e : coverpoint r_e;

endgroup
V. Verification Results and
cg cg_inst = new();
Analysis
initial // or task or function or
The coverage report is shows in the Fig. 8 which is always block
the foremost result in the verification analysis. In foreach(values[i])
the coding, a covergroup is created that is begin
generated which is clearly visible through the d_in = values[i];
coverage report. The coverpoints are created so as w_s = values[i];
to cover the each important aspect of the design w_e = values[i];
[13]. The practical coverage is the determination r_s = values[i];
of the amount of the design usefulness having r_e = values[i];
induced by the verification environment [14].
cg_inst.sample();

end

A covergroup in the coding is created that is

generated which is clearly visible through the
coverage report. The coverpoints are created so as
to cover the each important aspect of the design scoreboard report has been generated. The
[13]. scoreboard report generated in this case records the
transactions that are taking place in the verification
Covergroups report of the plan demonstrates in environment. For the above design it records the
the Fig. 9. This report essentially demonstrates the Reset, Write or Read scenario are being executed
coverpoints that has been made to cover the by the verification environment. It records the
different conditions of the design continuously. random test case data that is generated by the Write
control logic to be written in the FIFO memory. It
The cover_point_r_s and cover_point_r_e
also records the test case data that is read out form
coverpoint has covered both the situations in
the memory with the help of Read Control Logic.
which the Read control logic is selected in one In addition, it compares both the data being written
situation and not selected in the other. It covers matches with the data read out. The Driver requests
these conditions as these signals are given 0 and 1 are given to the scoreboard through the monitor
value randomly so as to cover both the scenarios. block. The generated scoreboard report for the
This is the reason that the coverage for these design has been given as follows:
signals is coming 100%. The cover_point_w_s and
cover_point_r_e covers both the scenarios in # Driver : transaction no : 0
which the Write control logic is selected in one and # Monitor : transaction no : 0
not selected in the other phase. Both the # Result is as Expected
situations are cover by the signals which are given # -------------------------
0 and 1 value. Due to this same reason that the # - [ Scoreboard ]
coverage for these signals also are showing to be # -------------------------
100 %.The most essential coverpoint of these is # - d_in = 1, w_s = 1, w_e = 1,
the first one i.e. cover_point_d_in. This coverpoint r_s = 0, r_e = 0
basically cover the scenarios in which random test # - d_out = 0, - full = 0, -
data is generated automatically and is given to the empty = 0
FIFO design. This coverpoint basically covers the # Driver : transaction no : 1
conditions whether all types of data are given to # Monitor : transaction no : 1
the design or not in the specified range that is # Result is as Expected
from 0 to 255. This range can also be visible # -------------------------
through the coding. It checks whether all the types # - [ Scoreboard ]
of data being written in the design and the same # -------------------------
data that was written is read out form the design. # - d_in = 3, w_s = 0, w_e = 0,
The random data that is being written and read r_s = 1, r_e = 1
out form the design can be seen in the scoreboard # - d_out = 1, - full = 0, -
report that is given in the next section. empty = 0
# -------------------------

VI. Conclusion
The design and verification of FIFO was the main
objective of this paper. The initial objective was to
design and implement the FIFO design using
Verilog language. Further the next step was to
verify the DUT i.e. the FIFO module in verification
environment using System Verilog language which
was the last and most crucial target of this work.

The test cases which are the input data that

need to be given have been randomized and
automated using the implemented verification
model. Here all the components of verification
environment had been implemented using system
Figure 9:- Covergroups Report
verilog language. The system Verilog functional
coverage methodology is approved that verifies
The scoreboard report [14] is the next portion
the functionality of the design in most effective
explained in this section. With the help of
way. The outcomes were obtained as functional
Scoreboard block of the verification plan, the
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