Features

• High-performance and Low-power AVR® 8-bit RISC Architecture

– 118 Powerful Instructions - Most Single Cycle Execution
– 32 x 8 General Purpose Working Registers
– Up to 8 MIPS Throughput at 8 MHz
• Data and Nonvolatile Program Memory
– 2K/4K Bytes of In-System Programmable Flash
Endurance 1,000 Write/Erase Cycles
– 128 Bytes of SRAM
– 128/256 Bytes of In-System Programmable EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
8-bit
• Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler
Microcontroller
– Expanded 16-bit Timer/Counter with Separate Prescaler,
Compare, Capture Modes and 8-, 9- or 10-bit PWM with 2K/4K bytes
– On-chip Analog Comparator
– Programmable Watchdog Timer with Separate On-chip Oscillator In-System
– Programmable UART
– 6-channel, 10-bit ADC Programmable
– Master/Slave SPI Serial Interface
• Special Microcontroller Features
– Brown-Out Reset Circuit
Flash
– Enhanced Power-on Reset Circuit
– Low-Power Idle and Power Down Modes

•
– External and Internal Interrupt Sources
Specifications
AT90S2333
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
AT90LS2333
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 3.4 mA AT90S4433
– Idle Mode: 1.4 mA
– Power Down Mode: <1 µA AT90LS4433
• I/O and Packages
– 20 Programmable I/O Lines
– 28-pin PDIP and 32-pin TQFP
• Operating Voltage Preliminary
– 2.7V - 6.0V (AT90LS2333 and AT90LS4433)
– 4.0V - 6.0V (AT90S2333 and AT90S4433)
• Speed Grades
– 0 - 4 MHz (AT90LS2333 and AT90LS4433)
– 0 - 8 MHz (AT90S2333 and AT90S4433)

Pin Configurations
TQFP Top View PDIP
PC5 (ADC5)
PC4 (ADC4)
PC3 (ADC3)
PC2 (ADC2)
PD2 (INT0)

PD0 (RDX)
PD1 (TXD)

RESET 1 28 PC5 (ADC5)

RESET

(RXD) PD0 2 27 PC4 (ADC4)

(TXD) PD1 3 26 PC3 (ADC3)
32
31
30
29
28
27
26
25

(INT0) PD2 4 25 PC2 (ADC2)

(INT1) PD3 1 24 PC1 (ADC1)
(INT1) PD3 5 24 PC1 (ADC1)
(T0) PD4 2 23 PC0 (ADC0) (T0) PD4 6 23 PC0 (ADC0)
NC 3 22 NC VCC 7 22 AGND
VCC 4 21 AGND GND 8 21 AREF
GND 5 20 AREF
XTAL1 9 20 AVCC
NC 6 19 NC
XTAL1 7 18 AVCC XTAL2 10 19 PB5 (SCK)
XTAL2 8 17 PB5 (SCK) (T1) PD5 11 18 PB4 (MISO)
(AIN0) PD6 12 17 PB3 (MOSI)
10
11
12
13
14
15
16
9

(AIN1) PD7 13 16 PB2 (SS) Rev. 1042DS–04/99

(T1) PD5
(AIN0) PD6
(AIN1) PD7
(ICP) PB0
(OC1) PB1
(SS) PB2
(MOS1) PB3
(MOS0) PB4

(ICP) PB0 14 15 PB1 (OC1)

Note: This is a summary document. For the complete 103 page

document, please visit our Web site at www.atmel.com or e-mail1
at [email protected] and request literature #1042D.
Description
The AT90S2333/4433 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing pow-
erful instructions in a single clock cycle, the AT90S2333/4433 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly
connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times
faster than conventional CISC microcontrollers.
The AT90S2333/4433 provides the following features: 2K/4K bytes of In-System Programmable Flash, 128/256 bytes
EEPROM, 128 bytes SRAM, 20 general purpose I/O lines, 32 general purpose working registers, two flexible
timer/counters with compare modes, internal and external interrupts, a programmable serial UART, 6-channel, 10-bit ADC,
programmable Watchdog Timer with internal oscillator, an SPI serial port and two software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue function-
ing. The Power Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the
next interrupt or hardware reset.
The device is manufactured using Atmel’s high density nonvolatile memory technology. The on-chip Flash program mem-
ory can be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer.
By combining a RISC 8-bit CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S2333/4433 is a
powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The AT90S2333/4433 AVR is supported with a full suite of program and system development tools including: C compilers,
macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Table 1. Comparison Table

Device Flash EEPROM SRAM Voltage Range Frequency
AT90S2333 2K 128B 128B 4.0V - 6.0V 0 - 8 MHz
AT90LS2333 2K 128B 128B 2.7V - 6.0V 0 - 4 MHz
AT90S4433 4K 256B 128B 4.0V - 6.0V 0 - 8 MHz
AT90LS4433 4K 256B 128B 2.7V - 6.0V 0 - 4 MHz

2 AT90S/LS2333 and AT90S/LS4433

 AT90S/LS2333 and AT90S/LS4433

Block Diagram

Figure 1. The AT90S2333/4433 Block Diagram

PC0 - PC5

VCC

PORTC DRIVERS

GND
DATA REGISTER DATA DIR.
PORTC REG. PORTC

8-BIT DATA BUS

AVCC

ANALOG MUX ADC

AGND
XTAL1
AREF

INTERNAL
OSCILLATOR
OSCILLATOR

XTAL2
PROGRAM STACK WATCHDOG TIMING AND
RESET
COUNTER POINTER TIMER CONTROL

PROGRAM MCU CONTROL

SRAM
FLASH REGISTER

INSTRUCTION GENERAL TIMER/

REGISTER PURPOSE COUNTERS
REGISTERS

X
INSTRUCTION Y INTERRUPT
DECODER Z UNIT

CONTROL
LINES ALU EEPROM

STATUS
REGISTER

PROGRAMMING
SPI UART
LOGIC

DATA REGISTER DATA DIR. DATA REGISTER DATA DIR.

PORTB REG. PORTB PORTD
+

REG. PORTD
-

ANALOG
COMPARATOR

PORTB DRIVERS PORTD DRIVERS

PB0 - PB5 PD0 - PD7

3
Pin Descriptions

VCC
Supply voltage

GND
Ground

Port B (PB5..PB0)
Port B is a 6-bit bi-directional I/O port with internal pullup resistors. The Port B output buffers can sink 20 mA. As inputs,
Port B pins that are externally pulled low will source current if the pull-up resistors are activated.
Port B also serves the functions of various special features of the AT90S2333/4433.
The port B pins are tristated when a reset condition becomes active, even if the clock is not running.

Port C (PC5..PC0)
Port C is a 6-bit bi-directional I/O port with internal pullup resistors. The Port C output buffers can sink 20 mA. As inputs,
Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Port C also serves as the
analog inputs to the A/D Converter.
The port C pins are tristated when a reset condition becomes active, even if the clock is not running.

Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs,
Port D pins that are externally pulled low will source current if the pull-up resistors are activated.
Port D also serves the functions of various special features of the AT90S2333/4433.
The port D pins are tristated when a reset condition becomes active, even if the clock is not running.

RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset pulses longer than 50 ns will generate
a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset.

XTAL1
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL2
Output from the inverting oscillator amplifier

AVCC
This is the supply voltage pin for the A/D Converter. It should be externally connected to V CC via a low-pass filter. See
Datasheet for details on operation of the ADC.

AREF
This is the analog reference input for the A/D Converter. For ADC operations, a voltage in the range 2.7V to AVCC must be
applied to this pin.

AGND
If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to
GND.

4 AT90S/LS2333 and AT90S/LS4433

 AT90S/LS2333 and AT90S/LS4433

Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access
time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands
are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock
cycle.
Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing - enabling
efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table
look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register
operations are also executed in the ALU. Figure 2 shows the AT90S2333/4433 AVR RISC microcontroller architecture.
In addition to the register operation, the conventional memory addressing modes can be used on the register file as well.
This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 - $1F), allowing
them to be accessed as though they were ordinary memory locations.

Figure 2. The AT90S2333/4433 AVR RISC Architecture

AVR AT90S2333/4433 Architecture

Data Bus 8-bit

Program Status Interrupt

1K/2K X 16
Counter and Control Unit
Program
Memory

SPI
32 x 8
Unit
Instruction General
Register Purpose
Registrers
Serial
UART
Instruction
Decoder
Indirect Addressing
Direct Addressing

8-bit
ALU Timer/Counter
Control Lines
16-bit
Timer/Counter
with PWM

128 x 8
Data Watchdog
SRAM Timer

Analog to Digital
128/256 x 8 Converter
EEPROM

20 Analog
I/O Lines Comparator

5
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-
converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following
those of the register file, $20 - $5F.
The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program
memory is executed with a two stage pipeline. While one instruction is being executed, the next instruction is pre-fetched
from the program memory. This concept enables instructions to be executed in every clock cycle.
The program memory is In-System Programmable Flash memory.
With the relative jump and call instructions, the whole 1K/2K word address space is directly accessed. Most AVR instruc-
tions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effec-
tively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the
usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are exe-
cuted). The 8-bit stack pointer SP is read/write accessible in the I/O space.
The 128 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR
architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.

Figure 3. AT90S2333/4433 Memory Maps

Program Memory Data Memory

$000 32 Gen. Purpose $0000

Working Registers $001F
$0020

64 I/O Registers
Program Flash
(1K/2K x 16)
$005F
$0060

Internal SRAM
(128 x 8)

$00DF

$3FF/ $7FF

A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status
register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the pro-
gram memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the
interrupt vector address, the higher the priority.

6 AT90S/LS2333 and AT90S/LS4433

 AT90S/LS2333 and AT90S/LS4433

Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$3F ($5F) SREG I T H S V N Z C
$3E ($5E) Reserved - - - - - - - -
$3D ($5D) SP SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
$3C ($5C) Reserved
$3B ($5B) GIMSK INT1 INT0 - - - - - -
$3A ($5A) GIFR INTF1 INTF0
$39 ($59) TIMSK TOIE1 OCIE1 - - TICIE1 - TOIE0 -
$38 ($58) TIFR TOV1 OCF1 - - ICF1 - TOV0 -
$37 ($57) Reserved
$36 ($56) Reserved
$35 ($55) MCUCR - SE SM ISC11 ISC10 ISC01 ISC00
$34 ($54) MCUSR - - - - WDRF BORF EXTRF PORF
$33 ($53) TCCR0 - - - - - CS02 CS01 CS00
$32 ($52) TCNT0 Timer/Counter0 (8 Bits)
$31 ($51) Reserved
$30 ($50) Reserved
$2F ($4F) TCCR1A COM11 COM10 - - - - PWM11 PWM10
$2E ($4E) TCCR1B ICNC1 ICES1 - - CTC1 CS12 CS11 CS10
$2D ($4D) TCNT1H Timer/Counter1 - Counter Register High Byte
$2C ($4C) TCNT1L Timer/Counter1 - Counter Register Low Byte
$2B ($4B) OCR1H Timer/Counter1 - Output Compare Register High Byte
$2A ($4A) OCR1L Timer/Counter1 - Output Compare Register Low Byte
$29 ($49) Reserved
$28 ($48) Reserved
$27 ($47) ICR1H Timer/Counter1 - Input Capture Register High Byte
$26 ($46) ICR1L Timer/Counter1 - Input Capture Register Low Byte
$25 ($45) Reserved
$24 ($44) Reserved
$23 ($43) Reserved
$22 ($42) Reserved
$21 ($41) WDTCR - - - WDTOE WDE WDP2 WDP1 WDP0
$20 ($40) Reserved
$1F ($3F) Reserved
$1E ($3E) EEAR EEPROM Address Register
$1D ($3D) EEDR EEPROM Data Register
$1C ($3C) EECR - - - - EERIE EEMWE EEWE EERE
$1B ($3B) Reserved
$1A ($3A) Reserved
$19 ($39) Reserved
$18 ($38) PORTB - - PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0
$17 ($37) DDRB - - DDB5 DDB4 DDB3 DDB2 DDB1 DDB0
$16 ($36) PINB - - PINB5 PINB4 PINB3 PINB2 PINB1 PINB0
$15 ($35) PORTC - - PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0
$14 ($34) DDRC - - DDC5 DDC4 DDC3 DDC2 DDC1 DDC0
$13 ($33) PINC - - PINC5 PINC4 PINC3 PINC2 PINC1 PINC0
$12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0
$11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0
$10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0
$0F ($2F) SPDR SPI Data Register
$0E ($2E) SPSR SPIF WCOL - - - - - -
$0D ($2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0
$0C ($2C) UDR UART I/O Data Register
$0B ($2B) UCSRA RXC TXC UDRE FE OR - - -
$0A ($2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8
$09 ($29) UBRR UART Baud Rate Register
$08 ($28) ACSR ACD AINBG ACO ACI ACIE ACIC ACIS1 ACIS0
$07 ($27) ADMUX - ADCBG - - - MUX2 MUX1 MUX0
$06 ($26) ADCSR ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0
$05 ($25) ADCH - - - - - - ADC9 ADC8
$04 ($24) ADCL ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0
$03 ($23) UBRRHI UART Baud Rate Register High

7
Register Summary (Continued)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
$02 ($22) Reserved
$01 ($21) Reserved
$00 ($20) Reserved
Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.

8 AT90S/LS2333 and AT90S/LS4433

 AT90S/LS2333 and AT90S/LS4433

Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← $FF None 1
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ← Z None 3
RET Subroutine Return PC ← STACK None 4
RETI Interrupt Return PC ← STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

9
Instruction Set Summary (Continued)
Mnemonics Operands Description Operation Flags #Clocks
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
LDI Rd, K Load Immediate Rd ← K None 1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memory R0 ← (Z) None 3
IN Rd, P In Port Rd ← P None 1
OUT P, Rr Out Port P ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← T None 1
SEC Set Carry C←1 C 1
CLC Clear Carry C←0 C 1
SEN Set Negative Flag N←1 N 1
CLN Clear Negative Flag N←0 N 1
SEZ Set Zero Flag Z←1 Z 1
CLZ Clear Zero Flag Z←0 Z 1
SEI Global Interrupt Enable I←1 I 1
CLI Global Interrupt Disable I←0 I 1
SES Set Signed Test Flag S←1 S 1
CLS Clear Signed Test Flag S←0 S 1
SEV Set Twos Complement Overflow. V←1 V 1
CLV Clear Twos Complement Overflow V←0 V 1
SET Set T in SREG T←1 T 1
CLT Clear T in SREG T←0 T 1
SEH Set Half Carry Flag in SREG H←1 H 1
CLH Clear Half Carry Flag in SREG H←0 H 1
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 3
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

10 AT90S/LS2333 and AT90S/LS4433

 AT90S/LS2333 and AT90S/LS4433

Ordering Information
Power Supply Speed (MHz) Ordering Code Package Operation Range
2.7 - 6.0V 4 AT90LS2333-4AC 32A Commercial
AT90LS2333-4PC 28P3 (0°C to 70°C)
AT90LS2333-4AI 32A Industrial
AT90LS2333-4PI 28P3 (-40°C to 85°C)
4.0 - 6.0V 8 AT90S2333-8AC 32A Commercial
AT90S2333-8PC 28P3 (0°C to 70°C)
AT90S2333-8AI 32A Industrial
AT90S2333-8PI 28P3 (-40°C to 85°C)
2.7 - 6.0V 4 AT90LS4433-4AC 32A Commercial
AT90LS4433-4PC 28P3 (0°C to 70°C)
AT90LS4433-4AI 32A Industrial
AT90LS4433-4PI 28P3 (-40°C to 85°C)
4.0 - 6.0V 8 AT90S4433-8AC 32A Commercial
AT90S4433-8PC 28P3 (0°C to 70°C)
AT90S4433-8AI 32A Industrial
AT90S4433-8PI 28P3 (-40°C to 85°C)

Package Type
28P3 28-lead, 0.300” Wide, Plastic Dual in Line Package (PDIP)
32A 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

11
Packaging Information
28P3, 28-lead, 0.300” Wide, 32A, 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad
Plastic Dual Inline Package (PDIP) Flat Package (TQFP)
Dimensions in Inches and (Millimeters) Dimensions in Millimeters and (Inches)

PIN 1 ID 9.00 (0.354) BSC

0.45 (0.018)
0.30 (0.012)

0.80 (0.031) BSC 9.00 (0.354) BSC

7.00 (0.276) BSC

1.20 (0.047) MAX

0˚
0.20 (0.008) 7˚
0.10 (0.004)

0.75 (0.030) 0.15 (0.006)

0.45 (0.018) 0.05 (0.002)

12 AT90S/LS2333 and AT90S/LS4433

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© Atmel Corporation 1999.

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1042DS–04/99/xM
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