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EEE 446 ISA Design Report: Instruction Formats

The document describes an instruction set architecture (ISA) design with three instruction formats: R-type for register-based operations, I-type for immediate values, and J-type for jumps. R-type uses a 4-bit function field to specify operations like addition and multiplication between registers. I-type uses a 7-bit immediate field, limiting branch ranges. Memory is divided into 16 sections to allow byte-level access within 128-byte regions using the section base and 7-bit immediate. J-type uses the full 13-bit instruction for absolute jumps.

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Андрей Малахов
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49 views4 pages

EEE 446 ISA Design Report: Instruction Formats

The document describes an instruction set architecture (ISA) design with three instruction formats: R-type for register-based operations, I-type for immediate values, and J-type for jumps. R-type uses a 4-bit function field to specify operations like addition and multiplication between registers. I-type uses a 7-bit immediate field, limiting branch ranges. Memory is divided into 16 sections to allow byte-level access within 128-byte regions using the section base and 7-bit immediate. J-type uses the full 13-bit instruction for absolute jumps.

Uploaded by

Андрей Малахов
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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EEE 446

ISA design report

Instruction formats
While deciding on the structure of the instructions in each type, we followed one of the ISA
design principles “Simplicity favors regularity” which can be seen since the location of the
opcode and the registers were the same in different instruction formats. Different addressing
modes will be used in this ISA. For example, in R-type instructions, register addressing will be
used since the result of the operation done between the two registers will be put into another
register. In addition, immediate addressing will be used for I-type instructions for some
instructions that uses an immediate value for arithmetic operations and relative addressing will
be used as well for branch operations. Absolute addressing will be used for jump operation since
the last 13 bits of the instruction is enough to cover the entire memory.

R-type:
opcode [15...13] Rs [12 ...10] Rt [9...7] Rd [6...4] Function [3...0]

We used 3 bits for each of the registers (Rs, Rt & Rd) since there will be 8 registers in the
register file. R-type instructions will use register addressing such as add (addition), sub
(subtraction), mul (Multiplication) & div (Division). When using R-type instruction the opcode
will be ‘000’ and then the 4 bits in function will determine what kind of function will be done.

Instruction opcode function Assembly code format Operation


add 000 0000 add $rd, $rs, $rt Rd = Rs + Rt
sub 000 0001 Sub $rd, $rs, $rt Rd = Rs - Rt
mul 000 0010 mul $rd, $rs, $rt Rd = Rs * Rt
div 000 0011 div $rd, $rs, $rt Rd = Rs / Rt

I-type:
Op-code [15...13] Rs [12 ...10] Rt [9...7] Immediate [6…0]

In I-type instructions, we will be using 3 bits for each of the registers Rs & Rt. Some instructions
that will be implemented are addi, beq & bne. However, these instructions will be limited by the
7 bits of immediate which is 128 in decimal, this means branch addressing will be in the range of
-27 to 27-1.

In the case of lw and sw instructions we want to make possible accessing all of the provided
memory. Our memory has 16-bit words, but registers are 8 bits. Hence, we want to make loading
and storing one byte at a time. In our memory we have 2048 bytes in total (even though they are
stored as 2 bytes at each address). Another obstacle is having only 7 bits for the offset. We can’t
access 2048 bytes using 7 bits only. Our solution is to virtually divide memory (2048 bytes) into
16 sections each containing 128 bytes as shown in the picture below.
To access a given byte, the programmer will need to specify the section in a base register and
one of the 128 bytes in that section.

For example, to access the 142s byte, he will need to make r1=2 and

lw r2, 15(r1).

It will choose the 15th byte of section 2. For this implementation, we will need to add a special
hardware that would solve byte addressing problems. This hardware would take last 4 bits from
the base register value (16 sections) and 7 immediate bits from instruction. First 10 bits would be
used for word accessing of memory, and the last bit for choosing between 2 bytes in the word.
Certainly, the programmers only concern is to choose the right section and byte. Same steps are
also valid for store operation.

Instruction Opcode Assembly code Operation


format
addi 0001 addi $rs, $rt, Imm Rt = Rs + Imm
bne 0010 bne $rs, $rt, Imm PC=PC+1+offset
beq 0011 beq $rs, $rt, Imm PC=PC+1+offset
lw 0100 lw $rt, Imm($rs) $Rt = MEM [section and byte]
sw 0101 sw $rt, Imm($rs) MEM [section and byte] = $Rt

J-type:
Op-code [15...13] Immediate [12 …0]

This operation type is used for jump instruction. For the jump instruction, absolute addressing
will be used to directly go to a certain address in the instruction memory.

Instruction Opcode Assembly code format


Jump 1111 J target

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