Chapter 9: 8086/8088 Hardware Specifications

Introduction
• In this chapter, the pin functions of both the
8086 and 8088 microprocessors are detailed
and information is provided on the following
hardware topics: clock generation, bus
buffering, bus latching, timing, wait states, and
minimum mode operation versus maximum
mode operation.
• These simple microprocessors are explained
as an introduction to the Intel microprocessor
family.
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Chapter Objectives
Upon completion of this chapter, you will be able to:

• Describe function of each 8086 & 8088 pin.

• Understand the microprocessor's DC
characteristics and indicate its fan-out to
common logic families.
• Use the clock generator chip (8284A) to
provide the clock for the microprocessor.
• Connect buffers and latches to the buses.

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Chapter Objectives (cont.)
Upon completion of this chapter, you will be able to:

• Interpret the timing diagrams.

• Describe wait states and connect the circuitry
required to cause various numbers of waits.
• Explain the difference between minimum and
maximum mode operation.

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9–1 PIN-OUTS AND THE PIN
FUNCTIONS
• In this section, we explain the function and
the multiple functions of each of the
microprocessor’s pins.

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The Pin-Out
• Figure 9–1 illustrates pin-outs of 8086 & 8088.
– both are packaged in 40-pin dual in-line
packages (DIPs)

• 8086 is a 16-bit microprocessor with a 16-bit

data bus; 8088 has an 8-bit data bus.
– 8086 has pin connections AD0–AD15
– 8088 has pin connections AD0–AD7
• Data bus width is the only major difference.
• thus 8086 transfers 16-bit data more efficiently
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Figure 9–1 (a) The pin-out of the 8086 in maximum mode; (b)
the pin-out of the 8086 in minimum mode.

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Pin Connections AD7 - AD0
• 8088 address/data bus lines are multiplexed
– and contain the rightmost 8 bits of the memory
address or I/O port number whenever ALE is
active (logic 1)
– or data whenever ALE is inactive (logic 0)
• These pins are at their high-impedance state
during a hold acknowledge.

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Pin Connections A15 - A8
• 8088 address bus provides the upper-half
memory address bits that are present
throughout a bus cycle.
• These address connections go to their high-
impedance state during a hold acknowledge.

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Pin Connections AD15 - AD8
• 8086 address/data bus lines compose upper
multiplexed address/data bus on the 8086.
• These lines contain address bits A15–A8
whenever ALE is a logic 1, and data bus
connections D15–D8 when ALE is a logic 0.
• These pins enter a high-impedance state
when a hold acknowledge occurs.

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Pin Connections A19/S6 - A16/S3
• Address/status bus bits are multiplexed to
provide address signals A19–A16 and status
bits S6–S3.
– high-impedance state during hold acknowledge
– status bit S6 is always logic 0,
– bit S5 indicates the condition of the IF flag bit
• S4 and S3 show which segment is accessed
during the current bus cycle.
– these status bits can address four separate 1M
byte memory banks by decoding as A21 and A20
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Pin Connections RD
• When read signal is logic 0, the data bus is
receptive to data from memory or I/O devices
– pin floats high-impedance state during a hold
acknowledge

Ready
• Inserts wait states into the timing.
– if placed at a logic 0, the microprocessor enters
into wait states and remains idle
– if logic 1, no effect on the operation
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Pin Connections INTR
• Interrupt request is used to request a
hardware interrupt.
– If INTR is held high when IF = 1, 8086/8088
enters an interrupt acknowledge cycle after the
current instruction has completed execution

NMI
• The non-maskable interrupt input is similar
to INTR.
– does not check IF flag bit for logic 1
– if activated, uses interrupt vector 2
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Pin Connections TEST
• The Test pin is an input that is tested by the
WAIT instruction.
• If TEST is a logic 0, the WAIT instruction
functions as an NOP.
• If TEST is a logic 1, the WAIT instruction
waits for TEST to become a logic 0.
• The TEST pin is most often connected to
the 8087 numeric coprocessor.

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Pin Connections RESET
• Causes the microprocessor to reset itself if
held high a minimum of four clocking periods.
– when 8086/8088 is reset, it executes instructions
at memory location FFFFOH
– also disables future interrupts by clearing IF flag
CLK
• The clock pin provides the basic timing signal.
– must have a duty cycle of 33 % (high for one third
of clocking period, low for two thirds) to provide
proper internal timing
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Pin Connections VCC
• This power supply input provides a +5.0 V,
±10 % signal to the microprocessor.

GND
• The ground connection is the return for the
power supply.
– 8086/8088 microprocessors have two pins
labeled GND—both must be connected to
ground for proper operation

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Pin Connections MN/MX
• Minimum/maximum mode pin selects either
minimum or maximum mode operation.
– if minimum mode selected, the MN/MX pin must
be connected directly to +5.0 V

BHE S7
• The bus high enable pin is used in 8086 to
enable the most-significant data bus bits
(D15–D8) during a read or a write operation.
• The state of S7 is always a logic 1.
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Minimum Mode Pins
• Minimum mode operation is obtained by
connecting the MN/MX pin directly to +5.0 V.
– do not connect to +5.0 V through a pull-up register;
it will not function correctly

IO/M or M/IO
• The IO/M (8088) or M/IO (8086) pin selects
memory or I/O.
– indicates the address bus contains either a
memory address or an I/O port address.
– high-impedance state during hold acknowledge
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Minimum Mode Pins WR
• Write line indicates 8086/8088 is outputting
data to a memory or I/O device.
– during the time WR is a logic 0, the data bus
contains valid data for memory or I/O
– high-impedance during a hold acknowledge

INTA
• The interrupt acknowledge signal is a
response to the INTR input pin.
– normally used to gate the interrupt vector number
onto the data bus in response to an interrupt
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Minimum Mode Pins ALE
• Address latch enable shows the 8086/8088
address/data bus contains an address.
– can be a memory address or an I/O port number
– ALE signal doesn’t float during hold acknowledge

DT/R
• The data transmit/receive signal shows that
the microprocessor data bus is transmitting
(DT/R = 1) or receiving (DT/R = 0) data.
– used to enable external data bus buffers
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Minimum Mode Pins DEN
• Data bus enable activates external data bus
buffers.

HOLD
• Hold input requests a direct memory access
(DMA).
– if HOLD signal is a logic 1, the microprocessor
stops executing software and places address,
data, and control bus at high-impedance
– if a logic 0, software executes normally
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Minimum Mode Pins HLDA
• Hold acknowledge indicates the 8086/8088
has entered the hold state.

SS0
• The SS0 status line is equivalent to the S0
pin in maximum mode operation.
• Signal is combined with IO/M and DT/R to
decode the function of the current bus cycle.

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Maximum Mode Pins
• In order to achieve maximum mode for use
with external coprocessors, connect the
MN/MX pin to ground.

S2, S1, and S0

• Status bits indicate function of the current
bus cycle.
– normally decoded by the 8288 bus controller

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Maximum Mode Pins RQ/GT1
• The request/grant pins request direct
memory accesses (DMA) during maximum
mode operation.
– bidirectional; used to request and grant a DMA
operation

LOCK
• The lock output is used to lock peripherals off
the system. This pin is activated by using the
LOCK: prefix on any instruction.
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Maximum Mode Pins QS1 and QS0
• The queue status bits show the status of the
internal instruction queue.
– provided for access by the 8087 coprocessor

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9–4 BUS TIMING
• It is essential to understand system bus timing
before choosing memory or I/O devices for
interfacing to 8086 or 8088 microprocessors.
• This section provides insight into operation
of the bus signals and the basic read/write
timing of the 8086/8088.

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Basic Bus Operation
• The three buses of 8086/8088 function the
same way as any other microprocessor.
• If data are written to memory the processor:
– outputs the memory address on the address bus
– outputs the data to be written on the data bus
– issues a write (WR) to memory
– and IO/M= 0 for 8088 and IO/M = 1 for 8086
• See simplified timing for write in Fig 9–9.

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Figure 9–9 Simplified 8086/8088 write bus cycle.

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• If data are read from the memory the
microprocessor:
– outputs the memory address on the address bus
– issues a read memory signal (RD)
– and accepts the data via the data bus
• See simplified timing for read in Fig 9–10.

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Figure 9–10 Simplified 8086/8088 read bus cycle.

The Intel Microprocessors: 8086/8088, 80186/80188, 80286, 80386, 80486 Pentium,

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