DIGITAL LOGIC DESIGN

Subject Code: CS304ES

Regulations : R16 - JNTUH
Class : II Year B.Tech CSE I Semester

Department of Computer Science and Engineering

BHARAT INSTITUTE OF ENGINEERING AND TECHNOLOGY
Ibrahimpatnam - 501 510, Hyderabad
 DIGITAL LOGIC DESIGN [CS304ES]
COURSE PLANNER

I. COURSE OVERVIEW:
The course addresses the concepts, principles and techniques of designing digital systems.
The course teaches the fundamentals of digital systems applying the logic design and
development techniques. This course forms the basis for the study of advanced subjects like
Computer Architecture and Organization, Microprocessor through Interfacing and VLSI
Design. Students will learn principles of digital systems logic design and distinguish between
analog and digital representations. They will be able to analyze a given combinational or
sequential circuit using k-map and Boolean algebra as a tool to simplify and design logic
circuits. Construct and analyze the operation of a latch, flip-flop and its application in
synchronous circuits.

II. PREREQUISITE:
Knowledge on number systems is the main prerequisite of digital logic design

III. COURSE OBJECTIVE:

1 To understand basic number systems, codes and logical gates.
2 To understand the concepts of Boolean algebra.
3 To understand the use of minimization logic to solve the Boolean logic expressions.
4 To understand the design of combinational and sequential circuits.
5 To understand the state reduction methods for Sequential circuits.
6 To understand the basics of various types of memories.

IV. COURSE OUTCOME:

S.No Description Bloom’s Taxonomy Level
1 Able to understand number systems and codes Understand
2 Able to solve Boolean expressions using Identify , Apply
Minimization methods.
3 Able to design the sequential and combinational Understand, Design ,
circuits Evaluate
4 Able to apply state reduction methods to solve Design , Analyze
sequential circuits.

V. HOW PROGRAM OUTCOMES ARE ASSESSED:

Program Outcomes Level Proficiency
assessed by
Engineering knowledge: Apply the knowledge of
Assignments,
PO1 mathematics, science, engineering fundamentals, and
3 Tutorials
an engineering specialization to the solution of
complex engineering problems.
Problem analysis: Identify, formulate, review
research literature, and analyze complex engineering
PO2 Assignments
problems reaching substantiated conclusions using 3
first principles of mathematics, natural sciences, and
engineering sciences.
 Design/development of solutions: Design solutions
for complex engineering problems and design system
PO3 components or processes that meet the specified Mini Projects
1
needs with appropriate consideration for the public
health and safety, and the cultural, societal, and
environmental considerations.
Conduct investigations of complex problems: Use
research-based knowledge and research methods
PO4 Projects
including design of experiments, analysis and 1
interpretation of data, and synthesis of the
information to provide valid conclusions.
Modern tool usage: Create, select, and apply
appropriate techniques, resources, and modern
PO5 Mini Projects
engineering and IT tools including prediction and 1
modeling to complex engineering activities with an
understanding of the limitations.
The engineer and society: Apply reasoning informed
by the contextual knowledge to assess societal,
PO6 --
health, safety, legal and cultural issues and the --
consequent responsibilities relevant to the
professional engineering practice.
Environment and sustainability: Understand the
impact of the professional engineering solutions in
PO7 --
societal and environmental contexts, and demonstrate --
the knowledge of, and need for sustainable
development.
Ethics: Apply ethical principles and commit to
PO8 Assignments
professional ethics and responsibilities and norms 1
ofthe engineering practice.
Individual and team work: Function effectively as
PO9 Mini Projects
an individual, and as a member or leader in diverse 1
teams, and in multidisciplinary settings.
Communication: Communicate effectively on
complex engineering activities with the engineering
PO10 community and with society at large, such as, being --
--
able to comprehend and write effective reports and
design documentation, make effective presentations,
and give and receive clear instructions.
Project management and finance: Demonstrate
knowledge and understanding of the engineering and
PO11 Projects
management principles and apply these to one’s own 1
work, as a member and leader in a team, to manage
projects and in multidisciplinary environments.
Life-long learning: Recognize the need for, and have
PO12 the preparation and ability to engage in independent Projects
1
and life-long learning in the broadest context of
technological change.
1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) - : None

VI. HOW PROGRAM SPECIFIC OUTCOMES ARE ASSESSED

 Program Specific Outcomes Level Proficiency assessed
by
Professional Skills: The ability to research,
understand and implement computer programs in the
Lectures,
PSO1 areas related to algorithms, system software,
3 Assignments
multimedia, web design, big data analytics, and
networking for efficient analysis and design of
computer-based systems of varying complexity
Problem-Solving Skills: The ability to apply
standard practices and strategies in software project
PSO2 Projects
development using open-ended programming 3
environments to deliver a quality product for
business success.
Successful Career and Entrepreneurship: The
ability to employ modern computer languages,
PSO3 Guest Lectures
environments, and platforms in creating innovative 1
career paths, to be an entrepreneur, and a zest for
higher studies.
1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) - : None
VII. SYLLABUS:

UNIT – I: Digital Systems, Binary Numbers, Number base conversions, Octal, Hexadecimal
and other base numbers, complements, signed binary numbers, Floating point number
representation, binary codes, Error detection and correction, binary storage and registers,
binary logic, Boolean algebra and logic gates , Basic theorems and properties of Boolean
Algebra, Boolean functions, canonical and standard forms, Digital Logic Gates.

UNIT – II: Gate–Level Minimization, The K-Map Method, Three-Variable Map, Four-
Variable Map, Five-Variable Map , sum of products , product of sums simplification, Don’t
care conditions , NAND and NOR implementation and other two level implementations,
Exclusive-OR function.

UNIT – III: Combinational Circuits (CC), Analysis procedure, Design Procedure,

Combinational circuit for different code converters and other problems, Binary Adder-
Subtractor, Decimal Adder, Binary Multiplier, Magnitude Comparator, Decoders, Encoders,
Multiplexers, Demultiplexers.

UNIT – IV: Synchronous Sequential Circuits, Latches, Flip-flops, analysis of clocked

sequential circuits, Registers, Shift registers, Ripple counters, Synchronous counters, other
counters. Asynchronous Sequential Circuits -Introduction, Analysis procedure, Circuits with
latches, Design procedure, Reduction of state and follow tables, Race- free state assignment,
Hazards.

UNIT – V: Memory: Introduction, Random-Access memory, Memory decoding, ROM,

Programmable Logic Array, Programmable Array Logic, Sequential programmable devices.
Register Transfer and Microoperations - Register Transfer Language, Register Transfer, Bus
and Memory Transfers, Arithmetic Microoperations, Logic Microoperations, Shift
Microoperations, Arithmetic Logic Shift Unit.

TEXT BOOKS:
 1. Digital Design, M. Morris Mano, M.D.Ciletti, 5th edition, Pearson.(Units I, II, III, IV, Part
of Unit V)
2. Computer System Architecture, M.Morris Mano, 3rd edition, Pearson.(Part of Unit V)
REFERENCE BOOKS:
1. Switching and Finite Automata Theory, Z. Kohavi, Tata McGraw Hill.
2. Fundamentals of Logic Design, C. H. Roth, L. L. Kinney, 7th edition, Cengage Learning.
3. Fundamentals of Digital Logic & Micro Computer Design, 5TH Edition, M.
Rafiquzzaman, John Wiley.

NPTEL LECTURES
http://nptel.ac.in/courses/117105080/

UGC-NET Syllabus
Computer Arithmetic:
Propositional (Boolean) Logic, Predicate Logic, Well-formed-formulae (WFF), Satisifiability
and Tautology.
Logic Families: TTL, ECL and C-MOS gates. Boolean algebra and Minimization of Boolean
functions, Flip-flops – types, race condition and comparison. Design of combinational and
sequential circuits.
Representation of Integers: Octal, Hex, Decimal, and Binary. 2’s Complement and 1’s
complement arithmetic. Floating point representation.

Gate Syllabus
Digital Logic: Logic functions, Boolean algebra; minimization of Boolean functions; logic
gates, Combinational circuits: arithmetic circuits, code converters, multiplexers and decoders.
Sequential circuits: latches and flip-flops, counters and shift-registers. Comparators, Design
and synthesis of combinational and sequential circuits; Number representation and computer
arithmetic (fixed and floating point).

IESsyllabus
Boolean algebra, simplification of Boolean functions, Karnaguh map and applications; IC
Logic gates and their characteristics; IC logic families Combinational logic Circuits; Half
adder, Full adder; Digital comparator; Multiplexer Demulti-plexer; ROM an their
applications. Flip flops. R-S, J-K, D and T flip-flops; Different types of counters and registers
Semiconductor memories
VIII. COURSE SCHEDULE:

Outcomes
Learning

Reference
Session

Course
Topic
Week
Unit

1 Digital Systems, Binary Numbers Understand the

2 Number Base Conversions need for
3 1 Octal, Hexadecimal and other Base Numbers digital systems
4 Complements, Signed Binary Numbers Understand the
5 Floating point number representation arithmetic
binary codes operations
carried by
6 digital
systems
Digital
Discuss error
Desig
detection and
1 n- M.
7 2 Error detection and correction correction in
Morris
digital
Mano
systems.
8 binary storage and registers, binary logic Learn Boolean
9 Boolean algebra and logic gates algebra and
1 Basic theorems and properties of Boolean logical
0 Algebra operations in
1 Boolean functions, canonical and standard Boolean
1 forms algebra.
1 Digital Logic Gates Identify basic
2 building
Gate–Level Minimization blocks of
1
3 digital
3
systems.
1 The K-Map Method
4
1 Three-Variable Map
5 Analyze to avoid
Digital
1 Four-Variable Map the redundant
Desig
6 terms in
2 n- M.
Boolean
1 Five-Variable Map Morris
functions.
7 Mano
1 sum of products , product of sums
4 simplification, Don’t care conditions
8
1 NAND and NOR implementation Design functions
9 using
2 other two level implementations, Exclusive- universal
0 OR function gates.
2 Combinational Circuits (CC), Analysis Discuss the Digital
5 3
1 procedure availability of Desig
2 Design Procedure different logic n- M.
2 circuits. Morris
2 Combinational circuit for different code Mano
3 converters
2 other problems
4
2 Binary Adder-Subtractor
5
2 Decimal Adder
6
2 Binary Multiplier Designdifferent
7 combinational
2 Magnitude Comparator and sequential
6
8 logic circuits.
2 Decoders, Encoders
9
3 Multiplexers, Demultiplexers.
0
3 Synchronous Sequential Circuits
Understand
1
construction
3 Latches
of sequential
2
programmable
3 Flip-flops
7 devices.
3
3 analysis of clocked sequential circuits
4 Analyze the
3 Registers concepts of
5 multiplexers,
3 Shift registers encoders
6
3 Ripple counters
Digital
7 Differentiate types
Desig
3 Synchronous counters other counters of counters.
8 4 n- M.
8
Morris
3 Asynchronous Sequential Circuits
Mano
9
Demonstratethe
4 Introduction, Analysis procedure
working of
0
asynchronous
4 Circuits with latches
sequential
1
circuits.
4 Design procedure
2
4 Reduction of state and follow tables
9
3 Demonstrate the
4 Race- free state assignment design of
4 sequential
4 Hazards logic circuits..
5
4 1 5 Memory: Introduction Understand the Digital
 6 0 concept of Desig
4 Random-Access memory memory n- M.
7 hierarchy. Morris
4 Memory decoding Mano
8
4 ROM
9
Learn various
5 Programmable Logic Array
types of data
0
storages
5 Programmable Array Logic
1
5 Sequential programmable devices
2
5 1 Register Transfer and Microoperations
3 1
5 Register Transfer Language Understand the
4 concepts of
5 Register Transfer Micro- Computer
5 operations & Syste
5 Bus and Memory Transfers Register m
6 Transfer Archit
5 Arithmetic Microoperations, Languages(Tr ecture,
7 anslating High M.Mo
5 1 Logic Microoperations Level to rris
8 2 Mechine Mano
5 Shift Microoperations Level
9 Language)
6 Arithmetic Logic Shift Unit
0
IX. MAPPING COURSE OBJECTIVES LEADING TO THE ACHIEVEMENT
OF PROGRAM OUTCOMES AND PROGRAM SPECIFIC OUTCOMES:
Program
Cours Specific
Program Outcomes (PO)
e Outcomes
Outco (PSO)
me P P P P P P P P P PO PO PO PS PS PS
O1 O2 O3 O4 O5 O6 O7 O8 O9 10 11 12 O1 O2 O3
CO1 2 2 - - - 2 - 1 3 2 - - 2 2 -
CO2 1 2 - - - 2 - 1 3 2 - - 1 2 -
CO3 1 2 2 1 - - 1 1 2 - 1 1 2 2
CO4 1 1 2 1 1 - - - 1 1 1 1 1 1 2
CO5 2 2 - - - 2 - 1 3 2 - - 2 2 -
CO6 1 2 - - - 2 - 1 3 2 - - 1 2 -
1.3 1.8 2.3 1.3 1.8
AVG 2 1 1 2 - 1 1.8 1 1 2
3 3 3 3 3

1: Slight (Low) 2: Moderate (Medium) 3: Substantial (High) - : None

Question Bank:
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UNIT-I DIGITAL SYSTEMS
Part - A (Short Answer Questions)
Write short notes on binary number systems? Understa
1 1
nd
Discuss 1’s and 2’s complement methods of subtraction? Understa
2 1
nd
Discuss octal number system? Understa
3 1
nd
State and prove transposition theorem? Knowled
4 1
ge
Explain how do you convert AOI logic to NAND logic? Understa
5 2
nd
Write a short note on five bit BCD codes? Understa
6 2
nd
Explain the specialty of unit–distance code? State where they are used? Understa
7 2
nd
Write a short note on error correcting codes? Understa
8 2
nd
State and prove De-Morgan theorem? Knowled
9 3
ge
Discuss what a logic design is and what do u mean by positive logic Understa
10 2
system? nd
Part - B (Long Answer Questions)
a) Solve the subtraction with the following unsigned binary numbers by
taking the 2's complement of the subtrahend: i.100 – 110000 ii.
1 11010 - 1101. Apply 2
b) Construct a table for 4 -3 -2 -1 weighted code and write 9154 using
this code .Write short notes on binary number systems.
a) Solve arithmetic operation indicated below. Follow signed bit notation:
2 i. 001110 + 110010 ii. 101011 - 100110. b) Explain the importance of Apply 1
gray code?
3 Solve (3250 - 72532)10using 10's complement? Apply 1
As part of an aircraft's functional monitoring system, a circuit is when the
\gear down" switch has been activated in preparation for landing. Red
LED display turns on if any of the gears fail to extend properly prior to
landing. When a landing gear is extended, its sensor produces a LOW Understa
4 1
voltage. When a landing gear is retracted, its sensor produces a HIGH nd
voltage. Design a circuit to meet this requirement? required to indicate
the status of the landing gears prior to landing. Green LED display
turns on if all three gears are properly extended
Solve (a) Divide 01100100 by 00011001 (b) Given that (292)10 =(1204)b
5. Apply 1
determine `b'
Part - C (Problem Solving and Critical Thinking Questions)
In a 32 bit computer, what are the maximum and minimum possible binary Understa
1. 1
numbers? Convert these into maximum and minimum possible nd
 positive decimal numbers?

Convert the octal numbers into binary,decimal,BCD and Hexadecimal

Understa
2. numbers 1
nd
(3600)octal,(1200)octal,(0200)octal,(0777)octal.
Convert the decimal numbers into binary, BCD and Hexadecimal numbers Understa
3. 1
(3600)d, (1200)d, (0200)d, (0777)d. nd
Suppose you have a cheque for RS.10000/-.what is the number system
Knowled
4. used? Define base system used and what are the weights of the digits 1
ge
1,0,0,0,0 and 0 now?
Illustrate why is (0.5252)octal twice of (0.2525)octal when (0.5050)d is
5. Apply 1
twice of (0.2525)d.

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UNIT-II GATE LEVEL MINIMIZATION AND COMBINATION CIRCUITS
Part - A (Short Answer Questions)
1 Define K-map? Name its advantages and disadvantages? Knowledge 5
2 Write the block diagram of 2-4 and 3-8 decoders? Understand 8
3 Define magnitude comparator? Knowledge 5
4 Describe what do you mean by look-ahead carry? Understand 5
5 Summarize the Boolean functionx′yz + x′yz′ + xy′z′ + xy′zusing K- map? Understand 4
Part - B (Long Answer Questions)
A combinational circuit has 4 inputs(A,B,C,D) and three
outputs(X,Y,Z)XYZ represents a binary number whose value equals
1. Knowledge 3
the number of 1's at the input istate the minterm expansion for the
X,Y,Z ii. state the maxterm expansion for the Y and Z
A combinational circuit has four inputs (A,B,C,D), which represent a
binarycoded-decimal digit. The circuit has two groups of four outputs -
S,T,U,V(MSB digit) and W,X,Y,Z.(LSB digit)Each group represents a
2. Apply 3
BCD digit. The output digits represent a decimal number which is five
times the input number. Illustrate the minimum expression for all the
outputs?
Summarize the following Boolean expressions using K-map and
implement them using NOR gates: (a) F (A, B, C, D) = AB’C’ + AC +
3. Understand 4
A’CD’ (b) F (W, X, Y, Z) = W’X’Y’Z’ + WXY’Z’ + W’X’YZ +
WXYZ.
4. Design BCD to Gray code converter and realize using logic gates? Understand 4
5. Design EX-OR using NAND gates? Understand 4
Part - C (Problem Solving and Critical Thinking Questions)
1. Use De-morgan theorem to simplify F=A+B+C.D.E. Apply 3
2. State that for constructing XOR from NANDs we need four NAND gates? Knowledge 3
State X+ (Y.Z) = (X+Y). (X+Z) = (X+Y).(X+Y+Z) a distributive law
3. Knowledge 5
using De-Morgan theorem?
4. Convert A.B.C+A.D expression into standard SOP format? Understand 4
5. Convert (A+B+C).(A+D) expression into standard POS format? Understand 4
6. Construct XOR from NOR gates? Understand 3
 Construct SOP expression and POS expression for a four input NAND
7. Understand 4
gate?
8. Understand Excess-3 codes for 3 and 7? Understand 3
9. Find the logic function F using AND-OR two level realization? Understand 4
10 Find transmitted 11 bits for 0110001 when hamming code is used? Understand 4

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UNIT-III COMBINATIONAL CIRCUITS
Part - A (Short Answer Questions)
1 Explain the design procedure for combinational circuits? Understand 7
2 Apply various code conversion methods? Apply 7
3 Design a 4-bit binary to BCD converter? Understand 7
4 Design and implement a 8421 Gray code converter? Understand 7
Design a combinational logic circuit with 3 input variables that will
5 produce logic 1 output when more than one input variables are logic Understand 7
1?

Part - B (Long Answer Questions)

Design a combinational circuit that generates the 9’s complement of BCD
1. Understand 7
digit?
Design a combinational circuit to find the 2’s complement of given binary
2. Understand 7
number and realize using NAND gates?
3. Design a logic circuit to convert gray code to binary code? Understand 7
Design circuit to detect invalid BCD number and implement using NAND
4. Understand 7
gate only?
Explain the design procedure for code converter with the help of
5. Understand 7
example?
Part - C (Problem Solving and Critical Thinking Questions)
Design a combinational logic circuit that produces the product of 2 binary
1. number ? Understand 7
A=(A1,A0)*B=(B2, B1, B0)
2. Solve the function using multiplexer F(x,y,z)=∑(0,2,6,7) Apply 7
A combinational circuit has 4 inputs(A,B,C,D) and three
outputs(X,Y,Z)XYZ represents a binary number whose value equals
3. Understand 7
the number of 1's at the input: i. Find the minterm expansion for the
X,Y,Z ii. Find the maxterm expansion for the Y and Z
Design a combinational logic circuit with 4 inputs A, B, C, D. The output
Y goes High if and only if A and C inputs go High. Draw the truth
4. table. Understand 7
Minimize the Boolean function using K-map. Draw the circuit
diagram?
5. Design a logic circuit to convert excess-3 code to BCD code? Understand 7
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UNIT-IV SYNCHRONOUS SEQUENTIAL CIRCUITS
Part - A (Short Answer Questions)
1 Differentiate combinational and sequential logic circuits? Apply 6
2 Explain basic difference between a shift register and counter? Understand 6
3 Illustrate applications of shift registers? Apply 6
4 Define bidirectional shift register? Knowledge 6
5 Describe dynamic shift register? Knowledge 6
Part - B (Long Answer Questions)
Explain the design of Sequential circuit with an example. Show the state
1. Understand 6
reduction, state assignment?
Write short notes on shift register? Mention its application along with the
2. Understand 6
Serial Transfer in 4-bit shift Registers?
3. Design a 4-bit BCD Ripple Counter by using T-FF? Understand 6
4. Define BCD Down Counter and Draw its State table for BCD Counter? Knowledge 6
Explain the state reduction and state assignment in designing sequential
5. Understand 10
circuit. Consider one example in the above process?
Part - C (Problem Solving and Critical Thinking Questions)
1. Design Universal Shift Register Analyze 7
A sequential circuit has 3 flip-flops, A,B and C and one input ,X .it is
described by the following flip flop input functions? 𝐷𝐴 = (𝐵𝐶 𝐼 +
2. 𝐵 𝐼 𝐶)𝑋 + (𝐵𝐶 + 𝐵 𝐼 𝐶 𝐼 )𝑋 𝐼 𝐷𝐵 = 𝐴 𝐷𝐶 = 𝐵 Apply 6
i)Derive the state table for circuit ii)Draw two state diagrams: One
for x=0 and for x=1
Design and implement 4-bit binary counter(using D flip flops) which
3. Understand 6
counts all possible odd numbers only?
4. Find the state assignments for sequence 1101011? Understand 10
Design a MOD-5 synchronous counter using flip flops and implement it?
5. Understand 6
Also draw the timing diagram?

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UNIT-V MEMORY
Part - A (Short Answer Questions)
1 Explain the block diagram of memory unit? Understand 9
2 Explain in detail about RAM and types of RAM? Understand 9
3 Illustrate the features of a ROM cell? Apply 9
4 Explain in detail about ROM and types of ROM? Understand 9
5 Explain coincident memory decoding? Understand 9
Part - B (Long Answer Questions)
1 Explain the internal construction of 4*4 RAM Understand 9
2 Draw the Two-Dimensional Decoding Structure for a 1K Word Memory Understand 9
 Tabulate the truth table for an 8*4 ROM that implements the Boolean
functions
A(x,y,z) = Σm(1,2,4) B(x,y,z) = Σm(0,1,6,7) C(x,y,z) = Σm(2,6)
3 Analyze 7
D(x,y,z) = Σm(1,2,3,5,7) Considering now the ROM as a memory,
Specify the
memory contents at Addresses 1 and 4.
Derive the Programmable Logic Array Programming Table for the
4 combinational circuit that squares a 3-bit number. Minimize the Analyze 7
number of Product Terms.
5 List the differences between Read Only Memories? Understand 9
Part - C (Problem Solving and Critical Thinking Questions)
Solve the following two Boolean functions using a PLA having 3-
1 inputs,4 product terms and 2 outputs? F1(A,B,C)=∑(0,1,2,4), Apply 9
F2(A,B,C)=∑(0,5,6,7)
Solve the following multi boolean function using 3- inputs 4 Product
2 terms 2 outputs PLA PLD? Apply 9
F1(a2, a1, a0)=∑m(0,1,3,5), F2(a2, a1, a0)=∑m(3,5,7)
3 Design and implement 3-bit binary to gray code converter using PLA? Understand 9
Design a combinational circuit using PAL. The circuit accepts 3-bit
4 number and generates an output binary number equal to square of Understand 9
input
Design and implement Full Adder using PAL?
5 Understand 9

OBJECTIVE-TYPE QUESTIONS

1. The smallest integer than can be represented by an 8-bit number in 2’s

Complement form is
(A) -256 (B) -128 (C) -127 (D) 0
2. A bulb in a staircase has two switches, one switch being at the ground floor
and the other one at the first floor. The bulb can be turned ON and also can
be turned OFF by any one of the switches irrespective of the state of the
other switch. The logic of switching of the bulb resembles
(A) an AND gate (B) an OR gate (C) an XOR gate (D) a NAND

3.
4.

5. The output Y in the circuit below is always ‘1’ when

(A) two or more of the inputs P,Q,R are ‘0’
(B) two or more of the inputs P,Q,R are ‘1’
(C) any odd number of the inputs P,Q,R is ‘0’
(D) any odd number of the inputs P,Q,R is ‘1’

6. When the output Y in the circuit below is ‘1’, it implies that data has
(A) changed from 0 to 1 (B) changed from 1 to 0
(C) changed in either direction (D) not changed

7. The minimum number of D flip-flops needed to design a mod-258 counter is

(A) 9 (B) 8 (C) 512 (D) 258
8. Consider the following circuit involving three D-type flip-flops used in a certain
type of counter configuration

i .If all the flip-flops were reset to 0 at power on, what is the total number of
distinct outputs (states) represented by PQR generated by the counter?
(A) 3 (B) 4 (C) 5 (D) 6
ii. If at some instance prior to the occurrence of the clock edge, P. Q and R have a
value 0, 1 and 0 respectively, what shall be the value of PQR after the clock
edge?
(A) 000 (B) 001 (C) 010 (D) 011
9. The Boolean expression for the output f of the multiplexer shown below is

10. In the sequential circuit shown below, if the initial value of the output Q1Q0 is 00,
what are the next four values of Q1Q0?
(A) 11,10,01,00
(B) 10,11,01,00
(C) 10,00,01,11
(D) 11,10,00,01

11.

12. Match the logic ga5tes in Column A with their equivalents in Column B.

(A) P–2, Q-4, R-1, S-3 (B) P-4, Q-2, R-1, S-3
(C) P–2, Q-4, R-3, S-1 (D) P-4, Q-2, R-3, S-1
13. For the output F to be 1 in the logic circuit shown, the input combination should be

(A) A = 1, B= 1. C = 0 (B) A = 1, B= 0,C = 0

(C) A = 0, B= 1. C = 0 (D) A = 0, B= 0, C = 1
14.Assuming that flip-flops are in reset condition initially, the count sequence
observed at QA in the circuit shown is

(A) 0010111… (B) 0001011… (C) 0101111… (D) 0110100…

15. The Boolean function realized by the logic circuit shown is
(A) F=Σm(0,1,3,5,9,10,14) (B) F=Σm(2,3,5,7,8,12,13)
(C) F=Σm(1,2,4,5,11,14,15) (D) F=Σm(2,3,5,7,8,9,12)
16. (1217)8 is equivalent to
(A) (1217)16 (B) (028F)16 (C) (2297)10 (D) (0B17)16
17. What is the minimum number of gates required to implement the Boolean
function (AB+C) if we have to use only 2-input NOR gates?
(A) 2 (B) 3 (C) 4 (D) 5
18. How many 32K x 1 RAM chips are needed to provide a memory capacity of 256Kbytes?
(A) 8 (B) 32 (C) 64 (D) 128
19. For the circuit shown in the following figure I0-I3 are inputs to the 4:1 multiplexer
R(MSB) and S are control bits

20.For each of the positive edge-triggered J-K flip flop used in the following figure,
the propagation delay is T

Which of the following waveforms correctly represents the output at Q1?

21. For the circuit shown in the figure, D has a transition from 0 to 1 after CLK
changes from 1 to 0. Assume gate delays to be negligible

Which of the following statements is true?

(A) Q goes to 1 at the CLK transition and stays at 1
(B) Q goes to 0 at the CLK transition and stays at 0
(C) Q goes to 1 at the CLK transition and goes to 0 when D goes to 1
(D) Q goes to 0 at the CLK transition and goes to 1 when D goes to 1
LIST OF WEBSITES:
Binary Systems
www.mathsisfun.com/binary-number-system.html
www.technologystudent.com/elec1/biny1.htm
www.cut-the-knot.org/do_you_know/BinaryHistory.shtml
tibasicdev.wikidot.com/binandhex
Boolean Algebra and Logic Gates
www.facstaff.bucknell.edu/mastascu/elessonshtml/logic/logic1.html
www.electronics-tutorials.ws/boolean/bool_7.html
www.ni.com/white-paper/14493/en/
www.wiziq.com/online-class/235559-boolean-algebra-logic-gates
Gate – Level Minimization
fullchipdesign.com/kmap2v.htm
world.xppoints.com/implicant.html
celeb.instacrypt.com/isVertical-interrupted.html
www.allaboutcircuits.com › Volume IV - Digital › Karnaugh Mapping
trade.nosis.com/es/fullchipdesign.com/4463993/s
Combinational Logic
www.electronics-tutorials.ws/combination/comb_1.html
www.tutorialspoint.com/computer_logical.../combinational_circuits.htm
www.allaboutcircuits.com › ... › Combinational Logic Functions
www.indiabix.com › Digital Electronics
Sequential Logic
https://www.princeton.edu/~achaney/tmve/.../docs/Sequential_logic.htm
psut.edu.jo/sites/.../Logic.../Chapter_5_Synchronous_Sequential_Logic.p
pc-vlsi18.ceid.upatras.gr/logic_design_ii.html
Registers and Counters
www.ee.usyd.edu.au/tutorials/digital_tutorial/part2/register07.html
www.electronics-tutorials.ws/
www.edutek.ltd.uk/Tutorials.htm
www.eecs.tufts.edu/~dsculley/tutorial/flopsandcounters/flopsFrame.html
Programmable Logic Devices
www.altera.com/literature/ug/ug_ram_rom.pdf
www.pcs.cnu.edu/~gerousis/courses/CPEN214/Memory.pdf
 search.edaboard.com/rom-ram.html
List of Experts
1. Hauser, John R-member of IEEE from North Carolina State Univ
2. Sheng-Fu Wu --member of IEEE from Michigan State Univ
3. IBM Thomas- member of IEEE from from Watson Research Center
List of Topics for Student Seminars
 demorgans law
 Standard sop &pos
 Binary adders
 Encoder& Decoder
 Multiplexer
Case Studies / Small Projects
List of Design Projects
 Design of MSB-detector (combinational logic)
 Four-bit comparator