Flip-flop (electronics) 1

Flip-flop (electronics)
In electronics, a flip-flop or latch is a circuit that has two stable states
and can be used to store state information. A flip-flop is a bistable
multivibrator. The circuit can be made to change state by signals
applied to one or more control inputs and will have one or two outputs.
It is the basic storage element in sequential logic. Flip-flops and latches
are a fundamental building block of digital electronics systems used in
computers, communications, and many other types of systems.

Flip-flops and latches are used as data storage elements. Such data
storage can be used for storage of state, and such a circuit is described
as sequential logic. When used in a finite-state machine, the output and
next state depend not only on its current input, but also on its current
An animated interactive SR latch (R1, R2 = 1 kΩ
state (and hence, previous inputs). It can also be used for counting of R3, R4 = 10 kΩ).
pulses, and for synchronizing variably-timed input signals to some
reference timing signal.

Flip-flops can be either simple (transparent or opaque) or clocked

(synchronous or edge-triggered); the simple ones are commonly called
latches. The word latch is mainly used for storage elements, while
clocked devices are described as flip-flops. A latch is level-sensitive,
whereas a flip-flop is edge-sensitive. That is, when a latch is enabled it
becomes transparent, while a flip flop's output only changes on a single
type (positive going or negative going) of clock edge.

An SR latch, constructed from a pair of

cross-coupled NOR gates.
Flip-flop (electronics) 2

History
The first electronic flip-flop was invented in 1918 by
William Eccles and F. W. Jordan.[1][2] It was initially called
the Eccles–Jordan trigger circuit and consisted of two
active elements (vacuum tubes). Such circuits and their
transistorized versions were common in computers even
after the introduction of integrated circuits, though
flip-flops made from logic gates are also common now.
Early flip-flops were known variously as trigger circuits or
multivibrators.

According to P. L. Lindley, a JPL engineer, the flip-flop

types discussed below (RS, D, T, JK) were first discussed in
a 1954 UCLA course on computer design by Montgomery
Phister, and then appeared in his book Logical Design of
Digital Computers.[3] Lindley was at the time working at
Hughes Aircraft under Dr. Eldred Nelson, who had coined
the term JK for a flip-flop which changed states when both
inputs were on. The other names were coined by Phister.
They differ slightly from some of the definitions given
below. Lindley explains that he heard the story of the JK
flip-flop from Dr. Eldred Nelson, who is responsible for
coining the term while working at Hughes Aircraft.
Flip-flops in use at Hughes at the time were all of the type
that came to be known as J-K. In designing a logical Flip-flop schematics from the Eccles and Jordan patent filed
system, Dr. Nelson assigned letters to flip-flop inputs as 1918, one drawn as a cascade of amplifiers with a positive
feedback path, and the other as a symmetric cross-coupled pair
follows: #1: A & B, #2: C & D, #3: E & F, #4: G & H, #5: J
& K. Nelson used the notations "j-input" and "k-input" in a
patent application filed in 1953.
Flip-flop (electronics) 3

Implementation
Flip-flops can be either simple (transparent
or asynchronous) or clocked (synchronous);
the transparent ones are commonly called
latches. The word latch is mainly used for
storage elements, while clocked devices are
described as flip-flops.[]

Simple flip-flops can be built around a pair

of cross-coupled inverting elements:
vacuum tubes, bipolar transistors, field
effect transistors, inverters, and inverting
logic gates have all been used in practical
circuits. Clocked devices are specially
designed for synchronous systems; such
devices ignore their inputs except at the
A traditional flip-flop circuit based on bipolar junction transistors
transition of a dedicated clock signal
(known as clocking, pulsing, or strobing).
Clocking causes the flip-flop to either change or retain its output signal based upon the values of the input signals at
the transition. Some flip-flops change output on the rising edge of the clock, others on the falling edge.

Since the elementary amplifying stages are inverting, two stages can be connected in succession (as a cascade) to
form the needed non-inverting amplifier. In this configuration, each amplifier may be considered as an active
inverting feedback network for the other inverting amplifier. Thus the two stages are connected in a non-inverting
loop although the circuit diagram is usually drawn as a symmetric cross-coupled pair (both the drawings are initially
introduced in the Eccles–Jordan patent).

Flip-flop types
Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or "delay"), T ("toggle"), and JK types
are the common ones. The behavior of a particular type can be described by what is termed the characteristic
equation, which derives the "next" (i.e., after the next clock pulse) output, Qnext in terms of the input signal(s) and/or
the current output, .

Simple set-reset latches

SR NOR latch
Flip-flop (electronics) 4

When using static gates as building blocks, the most fundamental latch
is the simple SR latch, where S and R stand for set and reset. It can be
constructed from a pair of cross-coupled NOR logic gates. The stored
bit is present on the output marked Q.
While the S and R inputs are both low, feedback maintains the Q and Q
outputs in a constant state, with Q the complement of Q. If S (Set) is
pulsed high while R (Reset) is held low, then the Q output is forced
high, and stays high when S returns to low; similarly, if R is pulsed
high while S is held low, then the Q output is forced low, and stays low An SR latch, constructed from a pair of
when R returns to low. cross-coupled NOR gates (an animated picture).
Red and black mean logical '1' and '0',
respectively.

[4]
SR latch operation

Characteristic table Excitation table

S R Qnext Action Q Qnext S R

0 0 Q hold state 0 0 0 X

0 1 0 reset 0 1 1 0

1 0 1 set 1 0 0 1

1 1 X not allowed 1 1 X 0

The R = S = 1 combination is called a restricted combination or a forbidden state because, as both NOR gates
then output zeros, it breaks the logical equation Q = not Q. The combination is also inappropriate in circuits where
both inputs may go low simultaneously (i.e. a transition from restricted to keep). The output would lock at either 1 or
0 depending on the propagation time relations between the gates (a race condition).
To overcome the restricted combination, one can add gates to the inputs that would convert (S,R) = (1,1) to
one of the non-restricted combinations. That can be:
• Q = 1 (1,0) – referred to as an S (dominated)-latch
• Q = 0 (0,1) – referred to as an R (dominated)-latch
This is done in nearly every Programmable logic controller.
• Keep state (0,0) – referred to as an E-latch
Alternatively, the restricted combination can be made to toggle the output. The result is the JK latch.
Characteristic: Q+ = R'Q + R'S or Q+ = R'Q + S.
Flip-flop (electronics) 5

SR NAND latch

This is an alternate model of the simple SR latch which is built with

NAND logic gates. Set and reset now become active low signals,
denoted S and R respectively. Otherwise, operation is identical to that
of the SR latch. Historically, SR-latches have been predominant
despite the notational inconvenience of active-low inputs.[citation needed]

An SR latch

SR latch operation

S R Action

0 0 Restricted combination

0 1 Q=1

1 0 Q=0
Symbol for an SR
1 1 No Change NAND latch

JK latch
The JK latch is much less frequently used than the JK flip-flop. The JK latch follows the following state table:

JK latch truth table

J K Qnext Comment

0 0 Q No change

0 1 0 Reset

1 0 1 Set

1 1 Q Toggle

Hence, the JK latch is an SR latch that is made to toggle its output when passed the restricted combination of 11.
Unlike the JK flip-flop, the 11 input combination for the SR latch is not useful because there is no clock that directs
toggling.

Gated latches and conditional transparency

Latches are designed to be transparent. That is, input signal changes cause immediate changes in output; when
several transparent latches follow each other, using the same enable signal, signals can propagate through all of
them at once. Alternatively, additional logic can be added to a simple transparent latch to make it non-transparent or
opaque when another input (an "enable" input) is not asserted. By following a transparent-high latch with a
transparent-low (or opaque-high) latch, a master–slave flip-flop is implemented.
Flip-flop (electronics) 6

Gated SR latch

A synchronous SR latch (sometimes clocked SR flip-flop) can be made

by adding a second level of NAND gates to the inverted SR latch (or a
second level of AND gates to the direct SR latch). The extra gates
further invert the inputs so the simple SR latch becomes a gated SR
latch (and a simple SR latch would transform into a gated SR latch
with inverted enable).
A gated SR latch circuit diagram constructed
With E high (enable true), the signals can pass through the input gates from NOR gates.
to the encapsulated latch; all signal combinations except for (0,0) =
hold then immediately reproduce on the (Q,Q) output, i.e. the latch is transparent.
With E low (enable false) the latch is closed (opaque) and remains in the state it was left the last time E was high.
The enable input is sometimes a clock signal, but more often a read or write strobe.

E/C Action

0 No action (keep state)

1 The same as non-clocked SR latch

|+ Gated SR latch operation

Symbol for a gated SR latch

Gated D latch

This latch exploits the fact that, in the two active input combinations
(01 and 10) of a gated SR latch, R is the complement of S. The input
NAND stage converts the two D input states (0 and 1) to these two
input combinations for the next SR latch by inverting the data input
signal. The low state of the enable signal produces the inactive "11"
combination. Thus a gated D-latch may be considered as a one-input
synchronous SR latch. This configuration prevents application of the A D-type transparent latch based on an SR
restricted input combination. It is also known as transparent latch, NAND latch

data latch, or simply gated latch. It has a data input and an enable
signal (sometimes named clock, or control). The word transparent
comes from the fact that, when the enable input is on, the signal
propagates directly through the circuit, from the input D to the output
Q.

Transparent latches are typically used as I/O ports or in asynchronous

systems, or in synchronous two-phase systems (synchronous systems
A gated D latch based on an SR NOR latch
that use a two-phase clock), where two latches operating on different
clock phases prevent data transparency as in a master–slave flip-flop.
Flip-flop (electronics) 7

Latches are available as integrated circuits, usually with multiple latches per chip. For example, 74HC75 is a
quadruple transparent latch in the 7400 series.

E/C D Q Q Comment

0 X Qprev Qprev No change

1 0 0 1 Reset

1 1 1 0 Set

|+ Gated D latch truth table

Symbol for a gated D latch

The truth table shows that when the enable/clock input is 0, the D input has no effect on the output. When E/C is
high, the output equals D.

Earle latch

The classic gated latch designs have some undesirable characteristics.

They require double-rail logic or an inverter. The input-to-output
propagation may take up to three gate delays. The input-to-output
propagation is not constant – some outputs take two gate delays while
others take three.
Designers looked for alternatives. A successful alternative is the Earle
latch. It requires only a single data input, and its output takes a constant
two gate delays. In addition, the two gate levels of the Earle latch can
be merged with the last two gate levels of the circuits driving the
latch.Wikipedia:Please clarify Merging the latch function can Earle latch uses complementary enable inputs:
enable active low (E_L) and enable active high
implement the latch with no additional gate delays.
(E_H)
The Earle latch is hazard free. If the middle NAND gate is omitted,
then one gets the polarity hold latch, which is commonly used because it demands less logic. However, it is
susceptible to logic hazard. Intentionally skewing the clock signal can avoid the hazard.
Flip-flop (electronics) 8

D flip-flop
The D flip-flop is widely used. It is also known as a data or delay
flip-flop.
The D flip-flop captures the value of the D-input at a definite portion
of the clock cycle (such as the rising edge of the clock). That captured
value becomes the Q output. At other times, the output Q does not
change.[5][6] The D flip-flop can be viewed as a memory cell, a
zero-order hold, or a delay line.[citation needed]
Truth table:

D flip-flop symbol

Clock D Qnext

Rising edge 0 0

Rising edge 1 1

Non-Rising X Q

('X' denotes a Don't care condition, meaning the signal is irrelevant)

Most D-type flip-flops in ICs have the capability to be forced to the set or reset state (which ignores the D and clock
inputs), much like an SR flip-flop. Usually, the illegal S = R = 1 condition is resolved in D-type flip-flops. By setting
S = R = 0, the flip-flop can be used as described above. Here is the truth table for the others S and R possible
configurations:

Inputs Outputs

S R D > Q Q'

0 1 X X 0 1

1 0 X X 1 0

1 1 X X 1 1

These flip-flops are very useful, as they form the basis for shift
registers, which are an essential part of many electronic devices. The
advantage of the D flip-flop over the D-type "transparent latch" is that
the signal on the D input pin is captured the moment the flip-flop is
4-bit serial-in, parallel-out (SIPO) shift register
clocked, and subsequent changes on the D input will be ignored until
the next clock event. An exception is that some flip-flops have a
"reset" signal input, which will reset Q (to zero), and may be either asynchronous or synchronous with the clock.

The above circuit shifts the contents of the register to the right, one bit position on each active transition of the clock.
The input X is shifted into the leftmost bit position.
Flip-flop (electronics) 9

Classical positive-edge-triggered D flip-flop

This circuit[7] consists of two stages implemented by SR NAND

latches. The input stage (the two latches on the left) processes the clock
and data signals to ensure correct input signals for the output stage (the
single latch on the right). If the clock is low, both the output signals of
the input stage are high regardless of the data input; the output latch is
unaffected and it stores the previous state. When the clock signal
changes from low to high, only one of the output voltages (depending
on the data signal) goes low and sets/resets the output latch: if D = 0,
the lower output becomes low; if D = 1, the upper output becomes low.
If the clock signal continues staying high, the outputs keep their states
regardless of the data input and force the output latch to stay in the
corresponding state as the input logical zero remains active while the
clock is high. Hence the role of the output latch is to store the data only A positive-edge-triggered D flip-flop
while the clock is low.

The circuit is closely related to the gated D latch as both the circuits convert the two D input states (0 and 1) to two
input combinations (01 and 10) for the output SR latch by inverting the data input signal (both the circuits split the
single D signal in two complementary S and R signals). The difference is that in the gated D latch simple NAND
logical gates are used while in the positive-edge-triggered D flip-flop SR NAND latches are used for this purpose.
The role of these latches is to "lock" the active output producing low voltage (a logical zero); thus the
positive-edge-triggered D flip-flop can be thought of as a gated D latch with latched input gates.

Master–slave edge-triggered D flip-flop

A master–slave D flip-flop is created by connecting two gated D latches in series, and inverting the enable input to
one of them. It is called master–slave because the second latch in the series only changes in response to a change in
the first (master) latch.
For a positive-edge triggered master–slave D flip-flop, when the clock
signal is low (logical 0) the "enable" seen by the first or "master" D
latch (the inverted clock signal) is high (logical 1). This allows the
"master" latch to store the input value when the clock signal transitions
from low to high. As the clock signal goes high (0 to 1) the inverted
"enable" of the first latch goes low (1 to 0) and the value seen at the A master–slave D flip-flop. It responds on the
falling edge of the enable input (usually a clock)
input to the master latch is "locked". Nearly simultaneously, the twice
inverted "enable" of the second or "slave" D latch transitions from low
to high (0 to 1) with the clock signal. This allows the signal captured at
the rising edge of the clock by the now "locked" master latch to pass
through the "slave" latch. When the clock signal returns to low (1 to 0),
the output of the "slave" latch is "locked", and the value seen at the last
rising edge of the clock is held while the "master" latch begins to An implementation of a master–slave D flip-flop
accept new values in preparation for the next rising clock edge. that is triggered on the rising edge of the clock

By removing the leftmost inverter in the circuit at side, a D-type

flip-flop that strobes on the falling edge of a clock signal can be obtained. This has a truth table like this:
Flip-flop (electronics) 10

D Q > Qnext

0 X Falling 0

1 X Falling 1

Edge-triggered dynamic D storage

element

An efficient functional alternative to a D

flip-flop can be made with dynamic circuits
(where information is stored in a
capacitance) as long as it is clocked often
enough; while not a true flip-flop, it is still
called a flip-flop for its functional role.
While the master–slave D element is
triggered on the edge of a clock, its
components are each triggered by clock
levels. The "edge-triggered D flip-flop", as A CMOS IC implementation of a "true single-phase edge-triggered flip-flop with
reset"
it is called even though it is not a true
flip-flop, does not have the master–slave
properties.

Edge-triggered D flip-flops are often implemented in integrated high-speed operations using dynamic logic. This
means that the digital output is stored on parasitic device capacitance while the device is not transitioning. This
design of dynamic flip flops also enables simple resetting since the reset operation can be performed by simply
discharging one or more internal nodes. A common dynamic flip-flop variety is the true single-phase clock (TSPC)
type which performs the flip-flop operation with little power and at high speeds. However, dynamic flip-flops will
typically not work at static or low clock speeds: given enough time, leakage paths may discharge the parasitic
capacitance enough to cause the flip-flop to enter invalid states.

T flip-flop
If the T input is high, the T flip-flop changes state ("toggles")
whenever the clock input is strobed. If the T input is low, the flip-flop
holds the previous value. This behavior is described by the
characteristic equation:

(expanding the XOR

operator)
and can be described in a truth table:

A circuit symbol for a T-type flip-flop

Flip-flop (electronics) 11

T flip-flop operation

Characteristic table Excitation table

Comment Comment

0 0 0 hold state (no clk) 0 0 0 No change

0 1 1 hold state (no clk) 1 1 0 No change

1 0 1 toggle 0 1 1 Complement

1 1 0 toggle 1 0 1 Complement

When T is held high, the toggle flip-flop divides the clock frequency by two; that is, if clock frequency is 4 MHz, the
output frequency obtained from the flip-flop will be 2 MHz. This "divide by" feature has application in various types
of digital counters. A T flip-flop can also be built using a JK flip-flop (J & K pins are connected together and act as
T) or D flip-flop (T input and Qprevious is connected to the D input through an XOR gate).

JK flip-flop
The JK flip-flop augments the behavior of the SR flip-flop (J=Set,
K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle
command. Specifically, the combination J = 1, K = 0 is a command to
set the flip-flop; the combination J = 0, K = 1 is a command to reset the
flip-flop; and the combination J = K = 1 is a command to toggle the
flip-flop, i.e., change its output to the logical complement of its current
value. Setting J = K = 0 does NOT result in a D flip-flop, but rather,
will hold the current state. To synthesize a D flip-flop, simply set K
equal to the complement of J. Similarly, to synthesize a T flip-flop, set
K equal to J. The JK flip-flop is therefore a universal flip-flop, because
it can be configured to work as an SR flip-flop, a D flip-flop, or a T
flip-flop. A circuit symbol for a positive-edge-triggered JK
The characteristic equation of the JK flip-flop is: flip-flop

and the corresponding truth table is:

JK flip-flop timing diagram

Flip-flop (electronics) 12

JK flip-flop operation

Characteristic table Excitation table

J K Comment Qnext Q J K Comment Qnext

0 0 hold state Q 0 0 X No Change 0

0 1 reset 0 0 1 X Set 1

1 0 set 1 1 X 1 Reset 0

1 1 toggle Q 1 X 0 No Change 1

Metastability
Flip-flops are subject to a problem called metastability, which can happen when two inputs, such as data and clock or
clock and reset, are changing at about the same time. When the order is not clear, within appropriate timing
constraints, the result is that the output may behave unpredictably, taking many times longer than normal to settle to
one state or the other, or even oscillating several times before settling. Theoretically, the time to settle down is not
bounded. In a computer system, this metastability can cause corruption of data or a program crash, if the state is not
stable before another circuit uses its value; in particular, if two different logical paths use the output of a flip-flop,
one path can interpret it as a 0 and the other as a 1 when it has not resolved to stable state, putting the machine into
an inconsistent state.

Timing considerations

Setup, hold, recovery, removal times

Setup time is the minimum amount of time the data signal should be
held steady before the clock event so that the data are reliably sampled
by the clock. This applies to synchronous input signals to the flip-flop.
Hold time is the minimum amount of time the data signal should be
held steady after the clock event so that the data are reliably sampled.
This applies to synchronous input signals to the flip-flop.
Synchronous signals (like Data) should be held steady from the set-up
time to the hold time, where both times are relative to the clock signal.
Recovery time is like setup time for asynchronous ports (set, reset). It
is the time available between the asynchronous signals going inactive
and the active clock edge. Flip-flop setup, hold and clock-to-output timing
Removal time is like hold time for asynchronous ports (set, reset). It is parameters

the time between active clock edge and asynchronous signal going
inactive.[8]
Short impulses applied to asynchronous inputs (set, reset) should not be applied completely within the
recovery-removal period, or else it becomes entirely indeterminable whether the flip-flop will transition to the
appropriate state. In another case, where an asynchronous signal simply makes one transition that happens to fall
between the recovery/removal time, eventually the asynchronous signal will be applied, but in that case it is also
possible that a very short glitch may appear on the output, dependent on the synchronous input signal. This second
situation may or may not have significance to a circuit design.
Flip-flop (electronics) 13

Set and Reset (and other) signals may be either synchronous or asynchronous and therefore may be characterized
with either Setup/Hold or Recovery/Removal times, and synchronicity is very dependent on the TTL design of the
flip-flop.
Differentiation between Setup/Hold and Recovery/Removal times is often necessary when verifying the timing of
larger circuits because asynchronous signals may be found to be less critical than synchronous signals. The
differentiation offers circuit designers the ability to define the verification conditions for these types of signals
independently.
The metastability in flip-flops can be avoided by ensuring that the data and control inputs are held valid and constant
for specified periods before and after the clock pulse, called the setup time (tsu) and the hold time (th) respectively.
These times are specified in the data sheet for the device, and are typically between a few nanoseconds and a few
hundred picoseconds for modern devices.
Unfortunately, it is not always possible to meet the setup and hold criteria, because the flip-flop may be connected to
a real-time signal that could change at any time, outside the control of the designer. In this case, the best the designer
can do is to reduce the probability of error to a certain level, depending on the required reliability of the circuit. One
technique for suppressing metastability is to connect two or more flip-flops in a chain, so that the output of each one
feeds the data input of the next, and all devices share a common clock. With this method, the probability of a
metastable event can be reduced to a negligible value, but never to zero. The probability of metastability gets closer
and closer to zero as the number of flip-flops connected in series is increased.
So-called metastable-hardened flip-flops are available, which work by reducing the setup and hold times as much as
possible, but even these cannot eliminate the problem entirely. This is because metastability is more than simply a
matter of circuit design. When the transitions in the clock and the data are close together in time, the flip-flop is
forced to decide which event happened first. However fast we make the device, there is always the possibility that
the input events will be so close together that it cannot detect which one happened first. It is therefore logically
impossible to build a perfectly metastable-proof flip-flop.

Propagation delay
Another important timing value for a flip-flop is the clock-to-output delay (common symbol in data sheets: tCO) or
propagation delay (tP), which is the time a flip-flop takes to change its output after the clock edge. The time for a
high-to-low transition (tPHL) is sometimes different from the time for a low-to-high transition (tPLH).
When cascading flip-flops which share the same clock (as in a shift register), it is important to ensure that the tCO of
a preceding flip-flop is longer than the hold time (th) of the following flip-flop, so data present at the input of the
succeeding flip-flop is properly "shifted in" following the active edge of the clock. This relationship between tCO and
th is normally guaranteed if the flip-flops are physically identical. Furthermore, for correct operation, it is easy to
verify that the clock period has to be greater than the sum tsu + th.

Generalizations
Flip-flops can be generalized in at least two ways: by making them 1-of-N instead of 1-of-2, and by adapting them to
logic with more than two states. In the special cases of 1-of-3 encoding, or multi-valued ternary logic, these elements
may be referred to as flip-flap-flops.[9]
In a conventional flip-flop, exactly one of the two complementary outputs is high. This can be generalized to a
memory element with N outputs, exactly one of which is high (alternatively, where exactly one of N is low). The
output is therefore always a one-hot (respectively one-cold) representation. The construction is similar to a
conventional cross-coupled flip-flop; each output, when high, inhibits all the other outputs. Alternatively, more or
less conventional flip-flops can be used, one per output, with additional circuitry to make sure only one at a time can
be true.
Flip-flop (electronics) 14

Another generalization of the conventional flip-flop is a memory element for multi-valued logic. In this case the
memory element retains exactly one of the logic states until the control inputs induce a change. In addition, a
multiple-valued clock can also be used, leading to new possible clock transitions.

References
[1] William Henry Eccles and Frank Wilfred Jordan, " Improvements in ionic relays (http:/ / v3. espacenet. com/ origdoc?DB=EPODOC&
IDX=GB148582& F=0& QPN=GB148582)" British patent number: GB 148582 (filed: 21 June 1918; published: 5 August 1920).
[2] W. H. Eccles and F. W. Jordan (19 September 1919) "A trigger relay utilizing three-electrode thermionic vacuum tubes," The Electrician, vol.
83, page 298. Reprinted in: Radio Review, vol. 1, no. 3, pages 143–146 (December 1919).
[3] P. L. Lindley, Aug. 1968, EDN (magazine), (letter dated June 13, 1968).
[4] Roth, Charles H. Jr. "Latches and Flip-Flops." Fundamentals of Logic Design. Boston: PWS, 1995. Print.
[5] The D Flip-Flop (http:/ / www. play-hookey. com/ digital/ d_nand_flip-flop. html)
[6] Edge-Triggered Flip-flops (http:/ / www. ee. usyd. edu. au/ tutorials/ digital_tutorial/ part2/ flip-flop02. html)
[7] SN7474 TI datasheet (http:/ / focus. ti. com/ lit/ ds/ symlink/ sn7474. pdf)
[8] https:/ / solvnet. synopsys. com/ retrieve/ customer/ application_notes/ attached_files/ 026030/ App_Note_generic_constraint. pdf
[9] Often attributed to Don Knuth (1969) (see ), the term flip-flap-flop actually appeared much earlier in the computing literature, for example, ,
and in

External links
• FlipFlop Hierarchy (http://teahlab.com/Multivibrators_FlipFlop/), shows interactive flipflop circuits.
Article Sources and Contributors 15

Article Sources and Contributors

Flip-flop (electronics)  Source: https://en.wikipedia.org/w/index.php?oldid=572862273  Contributors: 15turnsm, 2001:A60:108D:3501:224:1DFF:FE77:8DF5,
2002:18AB:75CE:1234:79A0:99A4:C01C:1C72, 2620:0:2820:2002:35D7:C533:70F5:3143, 32X, A. di M., A876, AJim, Acerperi, Adas0693, Adir Zevulun, Aeons, Ahoerstemeier,
Airconswitch, Aitias, Ajd4no, Altruism, Aminhungryboy, Amplitude101, Ancheta Wis, Anderson, Andonic, Anidemun, Anonymous Dissident, Anwar saadat, Apcolvin, Apolkhanov,
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Image Sources, Licenses and Contributors

File:Transistor Bistable interactive animated EN.svg  Source: https://en.wikipedia.org/w/index.php?title=File:Transistor_Bistable_interactive_animated_EN.svg  License: Creative Commons
Attribution-Sharealike 3.0  Contributors: User:DrJolo
File:R-S mk2.gif  Source: https://en.wikipedia.org/w/index.php?title=File:R-S_mk2.gif  License: Creative Commons Attribution 2.0  Contributors: Napalm Llama
File:Eccles-Jordan trigger circuit flip-flip drawings.png  Source: https://en.wikipedia.org/w/index.php?title=File:Eccles-Jordan_trigger_circuit_flip-flip_drawings.png  License: Public Domain
 Contributors: Eccles and Jordan
File:TTL flip-flop.svg  Source: https://en.wikipedia.org/w/index.php?title=File:TTL_flip-flop.svg  License: Creative Commons Attribution-Sharealike 3.0  Contributors: User:Nolanjshettle
File:SR Flip-flop Diagram.svg  Source: https://en.wikipedia.org/w/index.php?title=File:SR_Flip-flop_Diagram.svg  License: Public Domain  Contributors: jjbeard
File:Inverted SR latch symbol.png  Source: https://en.wikipedia.org/w/index.php?title=File:Inverted_SR_latch_symbol.png  License: GNU Free Documentation License  Contributors:
Fresheneesz
File:SR (Clocked) Flip-flop Diagram.svg  Source: https://en.wikipedia.org/w/index.php?title=File:SR_(Clocked)_Flip-flop_Diagram.svg  License: Public Domain  Contributors: Inductiveload
File:Gated SR flip-flop Symbol.svg  Source: https://en.wikipedia.org/w/index.php?title=File:Gated_SR_flip-flop_Symbol.svg  License: Public Domain  Contributors: Inductiveload
File:D-Type Transparent Latch.svg  Source: https://en.wikipedia.org/w/index.php?title=File:D-Type_Transparent_Latch.svg  License: Public Domain  Contributors: Inductiveload
File:D-type Transparent Latch (NOR).svg  Source: https://en.wikipedia.org/w/index.php?title=File:D-type_Transparent_Latch_(NOR).svg  License: Public Domain  Contributors:
Inductiveload
File:Transparent Latch Symbol.svg  Source: https://en.wikipedia.org/w/index.php?title=File:Transparent_Latch_Symbol.svg  License: Public Domain  Contributors: Inductiveload
File:SVG Earle Latch.svg  Source: https://en.wikipedia.org/w/index.php?title=File:SVG_Earle_Latch.svg  License: Public Domain  Contributors: Glrx
File:D-Type Flip-flop.svg  Source: https://en.wikipedia.org/w/index.php?title=File:D-Type_Flip-flop.svg  License: Public Domain  Contributors: Inductiveload
File:4 Bit Shift Register 001.svg  Source: https://en.wikipedia.org/w/index.php?title=File:4_Bit_Shift_Register_001.svg  License: unknown  Contributors: MichaelFrey
File:Edge triggered D flip flop.svg  Source: https://en.wikipedia.org/w/index.php?title=File:Edge_triggered_D_flip_flop.svg  License: GNU Free Documentation License  Contributors:
Nolanjshettle
File:Negative-edge triggered master slave D flip-flop.svg  Source: https://en.wikipedia.org/w/index.php?title=File:Negative-edge_triggered_master_slave_D_flip-flop.svg  License: GNU Free
Documentation License  Contributors: Nolanjshettle
File:D-Type Flip-flop Diagram.svg  Source: https://en.wikipedia.org/w/index.php?title=File:D-Type_Flip-flop_Diagram.svg  License: Public Domain  Contributors: jjbeard
File:True single-phase edge-triggered flip-flop with reset.svg  Source: https://en.wikipedia.org/w/index.php?title=File:True_single-phase_edge-triggered_flip-flop_with_reset.svg  License:
Creative Commons Attribution-Sharealike 3.0  Contributors: User:Nolanjshettle
File:T-Type Flip-flop.svg  Source: https://en.wikipedia.org/w/index.php?title=File:T-Type_Flip-flop.svg  License: Public Domain  Contributors: Inductiveload
File:JK Flip-flop (Simple) Symbol.svg  Source: https://en.wikipedia.org/w/index.php?title=File:JK_Flip-flop_(Simple)_Symbol.svg  License: Public Domain  Contributors: Inductiveload
File:JK timing diagram.svg  Source: https://en.wikipedia.org/w/index.php?title=File:JK_timing_diagram.svg  License: Creative Commons Attribution-Sharealike 3.0  Contributors: Stefan
Engvall
File:FF Tsetup Thold Toutput.svg  Source: https://en.wikipedia.org/w/index.php?title=File:FF_Tsetup_Thold_Toutput.svg  License: GNU Free Documentation License  Contributors: Dicklyon,
Michagal, 2 anonymous edits

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