Esp32 Technical Reference Manual en
Esp32 Technical Reference Manual en
Version 4.1
Espressif Systems
Copyright © 2019
www.espressif.com
About This Manual
The ESP32 Technical Reference Manual is addressed to application developers. The manual provides detailed
and complete information on how to use the ESP32 memory and peripherals.
For pin definition, electrical characteristics and package information, please see ESP32 Datasheet.
Document Updates
Please always refer to the latest version on https://www.espressif.com/en/support/download/documents.
Revision History
For any changes to this document over time, please refer to the last page.
Related Resources
Additional documentation and other resources about ESP32 can be accessed here: ESP32 Resources.
Certification
Download certificates for Espressif products from www.espressif.com/en/certificates.
2 Interrupt Matrix 32
2.1 Overview 32
2.2 Features 32
2.3 Functional Description 32
2.3.1 Peripheral Interrupt Source 32
2.3.2 CPU Interrupt 35
2.3.3 Allocate Peripheral Interrupt Sources to Peripheral Interrupt on CPU 35
2.3.4 CPU NMI Interrupt Mask 36
2.3.5 Query Current Interrupt Status of Peripheral Interrupt Source 36
5 DPort Register 85
5.1 Introduction 85
5.2 Features 85
5.3 Functional Description 85
5.3.1 System and Memory Register 85
5.3.2 Reset and Clock Registers 85
5.3.3 Interrupt Matrix Register 86
5.3.4 DMA Registers 90
5.3.5 PID/MPU/MMU Registers 90
5.3.6 APP_CPU Controller Registers 93
5.3.7 Peripheral Clock Gating and Reset 93
5.4 Register Summary 96
5.5 Registers 102
6 DMA Controller 116
6.1 Overview 116
6.2 Features 116
6.3 Functional Description 116
6.3.1 DMA Engine Architecture 116
6.3.2 Linked List 117
6.4 UART DMA (UDMA) 118
6.5 SPI DMA Interface 119
6.6 I2S DMA Interface 120
7 SPI 121
7.1 Overview 121
7.2 SPI Features 122
7.3 GP-SPI 122
7.3.1 GP-SPI Four-line Full-duplex Communication 123
7.3.2 GP-SPI Four-line Half-duplex Communication 123
7.3.3 GP-SPI Three-line Half-duplex Communication 124
7.3.4 GP-SPI Data Buffer 124
7.4 GP-SPI Clock Control 125
7.4.1 GP-SPI Clock Polarity (CPOL) and Clock Phase (CPHA) 125
7.4.2 GP-SPI Timing 126
7.5 Parallel QSPI 127
7.5.1 Communication Format of Parallel QSPI 128
7.6 GP-SPI Interrupt Hardware 128
7.6.1 SPI Interrupts 128
7.6.2 DMA Interrupts 129
7.7 Register Summary 129
7.8 Registers 132
12 I²S 306
12.1 Overview 306
12.2 Features 307
12.3 The Clock of I²S Module 308
12.4 I²S Mode 309
12.4.1 Supported Audio Standards 309
12.4.1.1 Philips Standard 309
12.4.1.2 MSB Alignment Standard 310
12.4.1.3 PCM Standard 310
12.4.2 Module Reset 310
12.4.3 FIFO Operation 310
12.4.4 Sending Data 311
12.4.5 Receiving Data 312
12.4.6 I²S Master/Slave Mode 314
12.4.7 I²S PDM 314
12.5 LCD Mode 317
12.5.1 LCD Master Transmitting Mode 317
12.5.2 Camera Slave Receiving Mode 318
12.5.3 ADC/DAC mode 319
12.6 I²S Interrupts 320
12.6.1 FIFO Interrupts 320
12.6.2 DMA Interrupts 320
12.7 Register Summary 320
12.8 Registers 323
14 LED_PWM 383
14.1 Introduction 383
14.2 Functional Description 383
14.2.1 Architecture 383
14.2.2 Timers 383
14.2.3 Channels 385
14.2.4 Interrupts 386
14.3 Register Summary 386
14.4 Registers 389
16 MCPWM 408
16.1 Introduction 408
16.2 Features 408
16.3 Submodules 410
16.3.1 Overview 410
16.3.1.1 Prescaler Submodule 410
16.3.1.2 Timer Submodule 410
16.3.1.3 Operator Submodule 411
16.3.1.4 Fault Detection Submodule 413
16.3.1.5 Capture Submodule 413
16.3.2 PWM Timer Submodule 413
16.3.2.1 Configurations of the PWM Timer Submodule 413
16.3.2.2 PWM Timer’s Working Modes and Timing Event Generation 414
16.3.2.3 PWM Timer Shadow Register 418
16.3.2.4 PWM Timer Synchronization and Phase Locking 418
16.3.3 PWM Operator Submodule 418
16.3.3.1 PWM Generator Submodule 419
16.3.3.2 Dead Time Generator Submodule 429
16.3.3.3 PWM Carrier Submodule 432
16.3.3.4 Fault Handler Submodule 435
16.3.4 Capture Submodule 437
16.3.4.1 Introduction 437
16.3.4.2 Capture Timer 437
16.3.4.3 Capture Channel 437
16.4 Register Summary 438
16.5 Registers 440
17 PULSE_CNT 487
17.1 Overview 487
17.2 Functional Description 487
17.2.1 Architecture 487
17.2.2 Counter Channel Inputs 488
17.2.3 Watchpoints 488
17.2.4 Examples 489
17.2.5 Interrupts 489
17.3 Register Summary 490
17.4 Registers 491
26 PID/MPU/MMU 559
26.1 Introduction 559
26.2 Features 559
26.3 Functional Description 559
26.3.1 PID Controller 559
26.3.2 MPU/MMU 560
26.3.2.1 Embedded Memory 560
26.3.2.2 External Memory 567
26.3.2.3 Peripheral 573
1.1 Introduction
The ESP32 is a dual-core system with two Harvard Architecture Xtensa LX6 CPUs. All embedded memory,
external memory and peripherals are located on the data bus and/or the instruction bus of these CPUs.
With some minor exceptions (see below), the address mapping of two CPUs is symmetric, meaning that they use
the same addresses to access the same memory. Multiple peripherals in the system can access embedded
memory via DMA.
The two CPUs are named “PRO_CPU” and “APP_CPU” (for “protocol” and “application”), however, for most
purposes the two CPUs are interchangeable.
1.2 Features
• Address Space
– 4 GB (32-bit) address space for both data bus and instruction bus
– Some embedded and external memory regions can be accessed by either data bus or instruction bus
• Embedded Memory
• External Memory
Off-chip SPI memory can be mapped into the available address space as external memory. Parts of the
embedded memory can be used as transparent cache for this external memory.
• Peripherals
– 41 peripherals
• DMA
The block diagram in Figure 1 illustrates the system structure, and the block diagram in Figure 2 illustrates the
address map structure.
Addresses below 0x4000_0000 are serviced using the data bus. Addresses in the range 0x4000_0000 ~
0x4FFF_FFFF are serviced using the instruction bus. Finally, addresses over and including 0x5000_0000 are
shared by the data and instruction bus.
The data bus and instruction bus are both little-endian: for example, byte addresses 0x0, 0x1, 0x2, 0x3 access
the least significant, second least significant, second most significant, and the most significant bytes of the 32-bit
word stored at the 0x0 address, respectively. The CPU can access data bus addresses via aligned or non-aligned
byte, half-word and word read-and-write operations. The CPU can read and write data through the instruction
bus, but only in a word aligned manner; non-word-aligned access will cause a CPU exception.
Each CPU can directly access embedded memory through both the data bus and the instruction bus, external
memory which is mapped into the address space (via transparent caching & MMU), and peripherals. Table 1
illustrates address ranges that can be accessed by each CPU’s data bus and instruction bus.
Some embedded memories and some external memories can be accessed via the data bus or the instruction
bus. In these cases, the same memory is available to either of the CPUs at two address ranges.
Boundary Address
Bus Type Size Target
Low Address High Address
0x0000_0000 0x3F3F_FFFF Reserved
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Memory
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External Memory
0x3FC0_0000 0x3FEF_FFFF 3 MB Reserved
Data 0x3FF0_0000 0x3FF7_FFFF 512 KB Peripheral
Data 0x3FF8_0000 0x3FFF_FFFF 512 KB Embedded Memory
Instruction 0x4000_0000 0x400C_1FFF 776 KB Embedded Memory
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Memory
0x40C0_0000 0x4FFF_FFFF 244 MB Reserved
Data / Instruction 0x5000_0000 0x5000_1FFF 8 KB Embedded Memory
0x5000_2000 0xFFFF_FFFF Reserved
The 448 KB internal ROM is divided into two parts: Internal ROM 0 (384 KB) and Internal ROM 1 (64 KB). The
520 KB internal SRAM is divided into three parts: Internal SRAM 0 (192 KB), Internal SRAM 1 (128 KB), and
Internal SRAM 2 (200 KB). RTC FAST Memory and RTC SLOW Memory are both implemented as SRAM.
Table 2 lists all embedded memories and their address ranges on the data and instruction buses.
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3FF8_0000 0x3FF8_1FFF 8 KB RTC FAST Memory PRO_CPU Only
0x3FF8_2000 0x3FF8_FFFF 56 KB Reserved -
Data 0x3FF9_0000 0x3FF9_FFFF 64 KB Internal ROM 1 -
0x3FFA_0000 0x3FFA_DFFF 56 KB Reserved -
Data 0x3FFA_E000 0x3FFD_FFFF 200 KB Internal SRAM 2 DMA
Data 0x3FFE_0000 0x3FFF_FFFF 128 KB Internal SRAM 1 DMA
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Instruction 0x4000_0000 0x4000_7FFF 32 KB Internal ROM 0 Remap
Instruction 0x4000_8000 0x4005_FFFF 352 KB Internal ROM 0 -
0x4006_0000 0x4006_FFFF 64 KB Reserved -
Instruction 0x4007_0000 0x4007_FFFF 64 KB Internal SRAM 0 Cache
Instruction 0x4008_0000 0x4009_FFFF 128 KB Internal SRAM 0 -
Instruction 0x400A_0000 0x400A_FFFF 64 KB Internal SRAM 1 -
Instruction 0x400B_0000 0x400B_7FFF 32 KB Internal SRAM 1 Remap
Instruction 0x400B_8000 0x400B_FFFF 32 KB Internal SRAM 1 -
Instruction 0x400C_0000 0x400C_1FFF 8 KB RTC FAST Memory PRO_CPU Only
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data Instruc-
0x5000_0000 0x5000_1FFF 8 KB RTC SLOW Memory -
tion
The capacity of Internal ROM 0 is 384 KB. It is accessible by both CPUs through the address range
0x4000_0000 ~ 0x4005_FFFF, which is on the instruction bus.
The address range of the first 32 KB of the ROM 0 (0x4000_0000 ~ 0x4000_7FFF) can be remapped in order to
access a part of Internal SRAM 1 that normally resides in a memory range of 0x400B_0000 ~ 0x400B_7FFF.
While remapping, the 32 KB SRAM cannot be accessed by an address range of 0x400B_0000 ~ 0x400B_7FFF
any more, but it can still be accessible through the data bus (0x3FFE_8000 ~ 0x3FFE_FFFF). This can be done
on a per-CPU basis: setting bit 0 of register DPORT_PRO_BOOT_REMAP_CTRL_REG or
DPORT_APP_BOOT_REMAP_CTRL_REG will remap SRAM for the PRO_CPU and APP_CPU,
respectively.
The capacity of Internal ROM 1 is 64 KB. It can be read by either CPU at an address range 0x3FF9_0000 ~
0x3FF9_FFFF of the data bus.
The capacity of Internal SRAM 0 is 192 KB. Hardware can be configured to use the first 64 KB to cache external
memory access. When not used as cache, the first 64 KB can be read and written by either CPU at addresses
0x4007_0000 ~ 0x4007_FFFF of the instruction bus. The remaining 128 KB can always be read and written by
either CPU at addresses 0x4008_0000 ~ 0x4009_FFFF of instruction bus.
The capacity of Internal SRAM 1 is 128 KB. Either CPU can read and write this memory at addresses
0x3FFE_0000 ~ 0x3FFF_FFFF of the data bus, and also at addresses 0x400A_0000 ~ 0x400B_FFFF of the
instruction bus.
The address range accessed via the instruction bus is in reverse order (word-wise) compared to access via the
data bus. That is to say, address
0x3FFE_0000 and 0x400B_FFFC access the same word
0x3FFE_0004 and 0x400B_FFF8 access the same word
0x3FFE_0008 and 0x400B_FFF4 access the same word
……
0x3FFF_FFF4 and 0x400A_0008 access the same word
0x3FFF_FFF8 and 0x400A_0004 access the same word
0x3FFF_FFFC and 0x400A_0000 access the same word
The data bus and instruction bus of the CPU are still both little-endian, so the byte order of individual words is not
reversed between address spaces. For example, address
0x3FFE_0000 accesses the least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0001 accesses the second least significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0002 accesses the second most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0003 accesses the most significant byte in the word accessed by 0x400B_FFFC.
0x3FFE_0004 accesses the least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0005 accesses the second least significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0006 accesses the second most significant byte in the word accessed by 0x400B_FFF8.
0x3FFE_0007 accesses the most significant byte in the word accessed by 0x400B_FFF8.
……
0x3FFF_FFF8 accesses the least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFF9 accesses the second least significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFA accesses the second most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFB accesses the most significant byte in the word accessed by 0x400A_0004.
0x3FFF_FFFC accesses the least significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFD accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFE accesses the second most significant byte in the word accessed by 0x400A_0000.
0x3FFF_FFFF accesses the most significant byte in the word accessed by 0x400A_0000.
Part of this memory can be remapped onto the ROM 0 address space. See Internal Rom 0 for more
information.
The capacity of Internal SRAM 2 is 200 KB. It can be read and written by either CPU at addresses 0x3FFA_E000
~ 0x3FFD_FFFF on the data bus.
1.3.2.6 DMA
DMA uses the same addressing as the CPU data bus to read and write Internal SRAM 1 and Internal SRAM 2.
This means DMA uses an address range of 0x3FFE_0000 ~ 0x3FFF_FFFF to read and write Internal SRAM 1 and
an address range of 0x3FFA_E000 ~ 0x3FFD_FFFF to read and write Internal SRAM 2.
In the ESP32, 13 peripherals are equipped with DMA. Table 3 lists these peripherals.
RTC FAST Memory is 8 KB of SRAM. It can be read and written by PRO_CPU only at an address range of
0x3FF8_0000 ~ 0x3FF8_1FFF on the data bus or at an address range of 0x400C_0000 ~ 0x400C_1FFF on the
instruction bus. Unlike most other memory regions, RTC FAST memory cannot be accessed by the
APP_CPU.
The two address ranges of PRO_CPU access RTC FAST Memory in the same order, so, for example, addresses
0x3FF8_0000 and 0x400C_0000 access the same word. On the APP_CPU, these address ranges do not
provide access to RTC FAST Memory or any other memory location.
RTC SLOW Memory is 8 KB of SRAM which can be read and written by either CPU at an address range of
0x5000_0000 ~ 0x5000_1FFF. This address range is shared by both the data bus and the instruction bus.
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3F40_0000 0x3F7F_FFFF 4 MB External Flash Read
Data 0x3F80_0000 0x3FBF_FFFF 4 MB External SRAM Read and Write
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Instruction 0x400C_2000 0x40BF_FFFF 11512 KB External Flash Read
1.3.4 Cache
As shown in Figure 3, each of the two CPUs in ESP32 has 32 KB of cache for accessing external storage. PRO
CPU uses bit PRO_CACHE_ENABLE in register DPORT_PRO_CACHE_CTRL_REG to enable the Cache, while
APP CPU uses bit APP_CACHE_ENABLE in register DPORT_APP_CACHE_CTRL_REG to enable the same
function.
ESP32 uses a two-way set-associative cache. When the Cache function is to be used either by PRO CPU or
APP CPU, bit CACHE_MUX_MODE[1:0] in register DPORT_CACHE_MUX_MODE_REG can be set to select
POOL0 or POOL1 in the Internal SRAM0 as the cache memory. When both PRO CPU and APP CPU use the
Cache function, POOL0 and POOL1 in the Internal SRAM0 will be used simultaneously as the cache memory,
while they can also be used by the instruction bus. This is depicted in table 5 below.
As described in table 5, when bit CACHE_MUX_MODE is set to 1 or 2, PRO CPU and APP CPU cannot enable
the Cache function at the same time. When the Cache function is enabled, POOL0 or POOL1 can only be used
as the cache memory, and cannot be used by the instruction bus as well.
ESP32 Cache supports the Flush function. It is worth noting that when the Flush function is used, the data
written in the cache will be disposed rather than being rewritten into the External SRAM. To enable the Flush
function, first clear bit x_CACHE_FLUSH_ENA in register DPORT_x_CACHE_CTRL_REG, then set this bit to 1.
Afterwards, the system hardware will set bit x_CACHE_FLUSH_DONE to 1, where x can be ”PRO” or ”APP”,
indicating that the cache flush operation has been completed.
For more information about the address mapping of ESP32 Cache, please refer to Embedded Memory and
External Memory.
1.3.5 Peripherals
The ESP32 has 41 peripherals. Table 6 specifically describes the peripherals and their respective address
ranges. Nearly all peripheral modules can be accessed by either CPU at the same address with just a single
exception; this being the PID Controller.
Boundary Address
Bus Type Size Target Comment
Low Address High Address
Data 0x3FF0_0000 0x3FF0_0FFF 4 KB DPort Register
Data 0x3FF0_1000 0x3FF0_1FFF 4 KB AES Accelerator
Data 0x3FF0_2000 0x3FF0_2FFF 4 KB RSA Accelerator
Data 0x3FF0_3000 0x3FF0_3FFF 4 KB SHA Accelerator
Data 0x3FF0_4000 0x3FF0_4FFF 4 KB Secure Boot
0x3FF0_5000 0x3FF0_FFFF 44 KB Reserved
Data 0x3FF1_0000 0x3FF1_3FFF 16 KB Cache MMU Table
0x3FF1_4000 0x3FF1_EFFF 44 KB Reserved
Data 0x3FF1_F000 0x3FF1_FFFF 4 KB PID Controller Per-CPU peripheral
0x3FF2_0000 0x3FF3_FFFF 128 KB Reserved
Data 0x3FF4_0000 0x3FF4_0FFF 4 KB UART0
0x3FF4_1000 0x3FF4_1FFF 4 KB Reserved
Data 0x3FF4_2000 0x3FF4_2FFF 4 KB SPI1
Data 0x3FF4_3000 0x3FF4_3FFF 4 KB SPI0
Data 0x3FF4_4000 0x3FF4_4FFF 4 KB GPIO
0x3FF4_5000 0x3FF4_7FFF 12 KB Reserved
Data 0x3FF4_8000 0x3FF4_8FFF 4 KB RTC
Data 0x3FF4_9000 0x3FF4_9FFF 4 KB IO MUX
0x3FF4_A000 0x3FF4_AFFF 4 KB Reserved
Data 0x3FF4_B000 0x3FF4_BFFF 4 KB SDIO Slave One of three parts
Data 0x3FF4_C000 0x3FF4_CFFF 4 KB UDMA1
0x3FF4_D000 0x3FF4_EFFF 8 KB Reserved
Data 0x3FF4_F000 0x3FF4_FFFF 4 KB I2S0
Data 0x3FF5_0000 0x3FF5_0FFF 4 KB UART1
Boundary Address
Bus Type Size Target Comment
Low Address High Address
0x3FF5_1000 0x3FF5_2FFF 8 KB Reserved
Data 0x3FF5_3000 0x3FF5_3FFF 4 KB I2C0
Data 0x3FF5_4000 0x3FF5_4FFF 4 KB UDMA0
Data 0x3FF5_5000 0x3FF5_5FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_6000 0x3FF5_6FFF 4 KB RMT
Data 0x3FF5_7000 0x3FF5_7FFF 4 KB PCNT
Data 0x3FF5_8000 0x3FF5_8FFF 4 KB SDIO Slave One of three parts
Data 0x3FF5_9000 0x3FF5_9FFF 4 KB LED PWM
Data 0x3FF5_A000 0x3FF5_AFFF 4 KB Efuse Controller
Data 0x3FF5_B000 0x3FF5_BFFF 4 KB Flash Encryption
0x3FF5_C000 0x3FF5_DFFF 8 KB Reserved
Data 0x3FF5_E000 0x3FF5_EFFF 4 KB PWM0
Data 0x3FF5_F000 0x3FF5_FFFF 4 KB TIMG0
Data 0x3FF6_0000 0x3FF6_0FFF 4 KB TIMG1
0x3FF6_1000 0x3FF6_3FFF 12 KB Reserved
Data 0x3FF6_4000 0x3FF6_4FFF 4 KB SPI2
Data 0x3FF6_5000 0x3FF6_5FFF 4 KB SPI3
Data 0x3FF6_6000 0x3FF6_6FFF 4 KB SYSCON
Data 0x3FF6_7000 0x3FF6_7FFF 4 KB I2C1
Data 0x3FF6_8000 0x3FF6_8FFF 4 KB SDMMC
Data 0x3FF6_9000 0x3FF6_AFFF 8 KB EMAC
0x3FF6_B000 0x3FF6_BFFF 4 KB Reserved
Data 0x3FF6_C000 0x3FF6_CFFF 4 KB PWM1
Data 0x3FF6_D000 0x3FF6_DFFF 4 KB I2S1
Data 0x3FF6_E000 0x3FF6_EFFF 4 KB UART2
Data 0x3FF6_F000 0x3FF6_FFFF 4 KB PWM2
Data 0x3FF7_0000 0x3FF7_0FFF 4 KB PWM3
0x3FF7_1000 0x3FF7_4FFF 16 KB Reserved
Data 0x3FF7_5000 0x3FF7_5FFF 4 KB RNG
0x3FF7_6000 0x3FF7_FFFF 40 KB Reserved
There are two PID Controllers in the system. They serve the PRO_CPU and the APP_CPU, respectively. The
PRO_CPU and the APP_CPU can only access their own PID Controller and not that of their counterpart.
Each CPU uses the same memory range 0x3FF1_F000 ~ 3FF1_FFFF to access its own PID Controller.
The SDIO Slave peripheral consists of three parts and the two CPUs use non-contiguous addresses to access
these. The three parts are accessed at the address ranges 0x3FF4_B000 ~ 3FF4_BFFF, 0x3FF5_5000 ~
3FF5_5FFF and 0x3FF5_8000 ~ 3FF5_8FFF of each CPU’s data bus. Similarly to other peripherals, access to
this peripheral is identical for both CPUs.
The ROM as well as the SRAM are both clocked from CPU_CLK and can be accessed by the CPU in a single
cycle. The RTC FAST memory is clocked from the APB_CLOCK and the RTC SLOW memory from the
FAST_CLOCK, so access to these memories may be slower. DMA uses the APB_CLK to access memory.
Internally, the SRAM is organized in 32K-sized banks. Each CPU and DMA channel can simultaneously access
the SRAM at full speed, provided they access addresses in different memory banks.
2. Interrupt Matrix
2.1 Overview
The Interrupt Matrix embedded in the ESP32 independently allocates peripheral interrupt sources to the two
CPUs’ peripheral interrupts. This configuration is made to be highly flexible in order to meet many different needs.
2.2 Features
• Accepts 71 peripheral interrupt sources as input.
The four remaining peripheral interrupt sources are CPU-specific, two per CPU. GPIO_INTERRUPT_PRO and
GPIO_INTERRUPT_PRO_NMI can only be allocated to PRO_CPU. GPIO_INTERRUPT_APP and
GPIO_INTERRUPT_APP_NMI can only be allocated to APP_CPU. As a result, PRO_CPU and APP_CPU each
have 69 peripheral interrupt sources.
2. Interrupt Matrix
PRO_CPU APP_CPU
Peripheral Interrupt Source
Peripheral Interrupt Peripheral Interrupt
Status Register Status Register
Configuration Register No. Name No. Configuration Register
Bit Name Name Bit
PRO_MAC_INTR_MAP_REG 0 0 MAC_INTR 0 0 APP_MAC_INTR_MAP_REG
PRO_MAC_NMI_MAP_REG 1 1 MAC_NMI 1 1 APP_MAC_NMI_MAP_REG
PRO_BB_INT_MAP_REG 2 2 BB_INT 2 2 APP_BB_INT_MAP_REG
PRO_BT_MAC_INT_MAP_REG 3 3 BT_MAC_INT 3 3 APP_BT_MAC_INT_MAP_REG
PRO_BT_BB_INT_MAP_REG 4 4 BT_BB_INT 4 4 APP_BT_BB_INT_MAP_REG
PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 APP_BT_BB_NMI_MAP_REG
PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 APP_RWBT_IRQ_MAP_REG
PRO_BT_BB_NMI_MAP_REG 5 5 BT_BB_NMI 5 5 APP_BT_BB_NMI_MAP_REG
PRO_RWBT_IRQ_MAP_REG 6 6 RWBT_IRQ 6 6 APP_RWBT_IRQ_MAP_REG
PRO_RWBLE_IRQ_MAP_REG 7 7 RWBLE_IRQ 7 7 APP_RWBLE_IRQ_MAP_REG
PRO_RWBT_NMI_MAP_REG 8 8 RWBT_NMI 8 8 APP_RWBT_NMI_MAP_REG
PRO_RWBLE_NMI_MAP_REG 9 9 RWBLE_NMI 9 9 APP_RWBLE_NMI_MAP_REG
PRO_SLC0_INTR_MAP_REG 10 10 SLC0_INTR 10 10 APP_SLC0_INTR_MAP_REG
PRO_SLC1_INTR_MAP_REG 11 11 SLC1_INTR 11 11 APP_SLC1_INTR_MAP_REG
PRO_UHCI0_INTR_MAP_REG 12 12 UHCI0_INTR 12 12 APP_UHCI0_INTR_MAP_REG
PRO_UHCI1_INTR_MAP_REG 13 13 UHCI1_INTR 13 13 APP_UHCI1_INTR_MAP_REG
PRO_INTR_STATUS_REG_0 APP_INTR_STATUS_REG_0
Submit Documentation Feedback
PRO_CPU APP_CPU
2. Interrupt Matrix
Peripheral Interrupt Source
Peripheral Interrupt Peripheral Interrupt
Status Register Status Register
Configuration Register No. Name No. Configuration Register
Bit Name Name Bit
PRO_SPI2_DMA_INT_MAP_REG 21 53 SPI2_DMA_INT 53 21 APP_SPI2_DMA_INT_MAP_REG
PRO_SPI3_DMA_INT_MAP_REG 22 54 SPI3_DMA_INT 54 22 APP_SPI3_DMA_INT_MAP_REG
PRO_WDG_INT_MAP_REG 23 55 WDG_INT 55 23 APP_WDG_INT_MAP_REG
PRO_TIMER_INT1_MAP_REG 24 56 TIMER_INT1 56 24 APP_TIMER_INT1_MAP_REG
PRO_TIMER_INT2_MAP_REG 25 57 TIMER_INT2 57 25 APP_TIMER_INT2_MAP_REG
PRO_TG_T0_EDGE_INT_MAP_REG 26 PRO_INTR_STATUS_REG_1 58 TG_T0_EDGE_INT 58 APP_INTR_STATUS_REG_1 26 APP_TG_T0_EDGE_INT_MAP_REG
PRO_TG_T1_EDGE_INT_MAP_REG 27 59 TG_T1_EDGE_INT 59 27 APP_TG_T1_EDGE_INT_MAP_REG
PRO_TG_WDT_EDGE_INT_MAP_REG 28 60 TG_WDT_EDGE_INT 60 28 APP_TG_WDT_EDGE_INT_MAP_REG
PRO_TG_LACT_EDGE_INT_MAP_REG 29 61 TG_LACT_EDGE_INT 61 29 APP_TG_LACT_EDGE_INT_MAP_REG
PRO_TG1_T0_EDGE_INT_MAP_REG 30 62 TG1_T0_EDGE_INT 62 30 APP_TG1_T0_EDGE_INT_MAP_REG
PRO_TG1_T1_EDGE_INT_MAP_REG 31 63 TG1_T1_EDGE_INT 63 31 APP_TG1_T1_EDGE_INT_MAP_REG
PRO_TG1_WDT_EDGE_INT_MAP_REG 0 64 TG1_WDT_EDGE_INT 64 0 APP_TG1_WDT_EDGE_INT_MAP_REG
PRO_TG1_LACT_EDGE_INT_MAP_REG 1 65 TG1_LACT_EDGE_INT 65 1 APP_TG1_LACT_EDGE_INT_MAP_REG
PRO_MMU_IA_INT_MAP_REG 2 PRO_INTR_STATUS_REG_2 66 MMU_IA_INT 66 APP_INTR_STATUS_REG_2 2 APP_MMU_IA_INT_MAP_REG
PRO_MPU_IA_INT_MAP_REG 3 67 MPU_IA_INT 67 3 APP_MPU_IA_INT_MAP_REG
PRO_CACHE_IA_INT_MAP_REG 4 68 CACHE_IA_INT 68 4 APP_CACHE_IA_INT_MAP_REG
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34
ESP32 Technical Reference Manual V4.1
2. Interrupt Matrix
• PRO_X_MAP_REG (or APP_X_MAP_REG) stands for any particular peripheral interrupt configuration
register of the PRO_CPU (or APP_CPU). The peripheral interrupt configuration register corresponds to the
peripheral interrupt source Source_X. In Table 7 the registers listed under “PRO_CPU (APP_CPU) -
Peripheral Interrupt Configuration Register” correspond to the peripheral interrupt sources listed in
“Peripheral Interrupt Source - Name”.
• Interrupt_P stands for CPU peripheral interrupt, numbered as Num_P. Num_P can take the ranges 0 ~ 5, 8
~ 10, 12 ~ 14, 17 ~ 28, 30 ~ 31.
• Interrupt_I stands for the CPU internal interrupt numbered as Num_I. Num_I can take values 6, 7, 11, 15,
16, 29.
Using this terminology, the possible operations of the Interrupt Matrix controller can be described as
follows:
• Allocate multiple peripheral sources Source_Xn ORed to PRO_CPU (APP_CPU) peripheral interrupt
Set multiple PRO_Xn_MAP_REG (APP_Xn_MAP_REG) to the same Num_P. Any of these peripheral
interrupts will trigger CPU Interrupt_P.
• CPU reset: Only resets the registers of one or both of the CPU cores.
• Core reset: Resets all the digital registers, including CPU cores, external GPIO and digital GPIO. The RTC is
not reset.
• System reset: Resets all the registers on the chip, including those of the RTC.
– XTL_CLK is a clock signal generated using an external crystal with a frequency range of 2 ~ 40 MHz.
– RTC8M_CLK is an internal clock with a default frequency of 8 MHz. This frequency is adjustable.
– RTC8M_D256_CLK is divided from RTC8M_CLK 256. Its frequency is (RTC8M_CLK / 256). With the
default RTC8M_CLK frequency of 8 MHz, this clock runs at 31.250 KHz.
– RTC_CLK is an internal low power clock with a default frequency of 150 KHz. This frequency is
adjustable.
• Audio Clock
– APLL_CLK is an internal Audio PLL clock with a frequency range of 16 ~ 128 MHz.
The CPU_CLK clock source is determined by the RTC_CNTL_SOC_CLK_SEL register. PLL_CLK, APLL_CLK,
RTC8M_CLK and XTL_CLK can be set as the CPU_CLK source; see Table 10 and 11.
The APB_CLK is derived from CPU_CLK as detailed in Table 13. The division factor depends on the CPU_CLK
source.
REF_TICK is derived from APB_CLK via a divider. The divider value used depends on the APB_CLK source,
which in turn depends on the CPU_CLK source.
By configuring correct divider values for each APB_CLK source, the user can ensure that the REF_TICK
frequency does not change when CPU_CLK changes source, causing the APB_CLK frequency to change.
The LEDC_SCLK clock source is selected by the LEDC_APB_CLK_SEL register, as shown in Table 15.
The APLL_CLK is sourced from PLL_CLK, with its output frequency configured using the APLL configuration
registers.
Most peripherals will operate using the APB_CLK frequency as a reference. When this frequency changes, the
peripherals will need to update their clock configuration to operate at the same frequency after the change.
Peripherals accessing REF_TICK can continue operating normally when switching clock sources, without
changing clock source. Please see Table 12 for details.
The LED PWM module can use RTC8M_CLK as a clock source when APB_CLK is disabled. In other words,
when the system is in low-power consumption mode (see Power Management Chapter), normal peripherals will
be halted (APB_CLK is turned off), but the LED PWM can work normally via RTC8M_CLK.
For LOW_POWER_CLK, one of RTC_CLK, SLOW_CLK, RTC8M_CLK or XTL_CLK can be selected as the
low-power consumption mode clock source for Wi-Fi and BT.
SLOW_CLK is used to clock the Power Management module. It can be sourced from RTC_CLK, XTL32K_CLK
or RTC8M_D256_CLK
FAST_CLK is used to clock the On-chip Sensor module. It can be sourced from a divided XTL_CLK or from
RTC8M_CLK.
Providing an integrated precision clock source can minimize system cost. To this end, ESP32 integrates an audio
PLL intended for I2S peripherals. More details on how to clock the I2S module, using an APLL clock, can be
found in Chapter I2S. The Audio PLL formula is as follows:
The operating frequency range of the numerator is 350 MHz ~ 500 MHz:
sdm1 sdm0
350M Hz < fxtal (sdm2 + + 16 + 4) < 500M Hz
28 2
Please note that sdm1 and sdm0 are not available on revision0 of ESP32. Please consult the silicon revision in
ECO and Workarounds for Bugs in ESP32 for further details.
Audio PLL can be manually enabled or disabled via registers RTC_CNTL_PLLA_FORCE_PU and
RTC_CNTL_PLLA_FORCE_PD, respectively. Disabling it takes priority over enabling it. When
RTC_CNTL_PLLA_FORCE_PU and RTC_CNTL_PLLA_FORCE_PD are 0, PLL will follow the state of the system,
i.e., when the system enters sleep mode, PLL will be disabled automatically; when the system wakes up, PLL will
be enabled automatically.
4.1 Overview
The ESP32 chip features 34 physical GPIO pads. Each pad can be used as a general-purpose I/O, or be
connected to an internal peripheral signal. The IO_MUX, RTC IO_MUX and the GPIO matrix are responsible for
routing signals from the peripherals to GPIO pads. Together these systems provide highly configurable I/O.
Note that the I/O GPIO pads are 0-19, 21-23, 25-27, 32-39, while the output GPIOs are 0-19, 21-23, 25-27,
32-33. GPIO pads 34-39 are input-only.
This chapter describes the signal selection and connection between the digital pads (FUN_SEL, IE, OE, WPU,
WDU, etc.), 162 peripheral input and 176 output signals (control signals: SIG_IN_SEL, SIG_OUT_SEL, IE, OE,
etc.), fast peripheral input/output signals (control signals: IE, OE, etc.), and RTC IO_MUX.
1. The IO_MUX contains one register per GPIO pad. Each pad can be configured to perform a ”GPIO” function
(when connected to the GPIO Matrix) or a direct function (bypassing the GPIO Matrix). Some high-speed
digital functions (Ethernet, SDIO, SPI, JTAG, UART) can bypass the GPIO Matrix for better high-frequency
digital performance. In this case, the IO_MUX is used to connect these pads directly to the peripheral.)
See Section 4.10 for a list of IO_MUX functions for each I/O pad.
2. The GPIO Matrix is a full-switching matrix between the peripheral input/output signals and the pads.
• For input to the chip: Each of the 162 internal peripheral inputs can select any GPIO pad as the input
source.
• For output from the chip: The output signal of each of the 34 GPIO pads can be from one of the 176
peripheral output signals.
3. RTC IO_MUX is used to connect GPIO pads to their low-power and analog functions. Only a subset of
GPIO pads have these optional ”RTC” functions.
The input signal is read from the GPIO pad through the IO_MUX. The IO_MUX must be configured to set the
chosen pad to ”GPIO” function. This causes the GPIO pad input signal to be routed into the GPIO Matrix, which
in turn routes it to the selected peripheral input.
MCU_SEL
GPIO0_in
0
GPIO1_in GPIO_SIGxx_IN_SEL
1
GPIO2_in
2
GPIO3_in 0 (FUNC)
3
0 1 (FUNC) I/O Pad X
GPIOX_in GPIO X in 2 (GPIO)
Peripheral Signal Y X 1 (GPIO)
GPIO39_in
39
FUN_IE = 1
Constant 0 input
(0x30)48
Constant 1 input
(0x38)56
To read GPIO pad X into peripheral signal Y, follow the steps below:
1. Configure the GPIO_FUNCy_IN_SEL_CFG register corresponding to peripheral signal Y in the GPIO Matrix:
• Set the GPIO_FUNCx_IN_SEL field in this register, corresponding to the GPIO pad X to read from.
Clear all other fields corresponding to other GPIO pads.
• Set the GPIO_FUNCx_OEN_SEL bit in the GPIO_FUNCx_OUT_SEL_CFG register to force the pin’s
output state to be determined always by the GPIO_ENABLE_DATA[x] field.
3. Configure the IO_MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO
pad X as follows:
• Set the function field (MCU_SEL) to the IO_MUX function corresponding to GPIO X (this is Function
#3—numeric value 2—for all pins).
• Set or clear the FUN_WPU and FUN_WPD bits, as desired, to enable/disable internal
pull-up/pull-down resistors.
Notes:
• It is possible to have a peripheral read a constantly low or constantly high input value without connecting
this input to a pad. This can be done by selecting a special GPIO_FUNCy_IN_SEL input, instead of a GPIO
number:
For example, to connect RMT peripheral channel 0 input signal (RMT_SIG_IN0_IDX, signal index 83) to GPIO 15,
please follow the steps below. Note that GPIO 15 is also named the MTDO pin:
4. Set the IO_MUX_GPIO15 register MCU_SEL field to 2 (GPIO function) and also set the FUN_IE bit (input
mode).
The input value of any GPIO pin can be read at any time without configuring the GPIO Matrix for a particular
peripheral signal. However, it is necessary to enable the input in the IO_MUX by setting the FUN_IE bit in the
IO_MUX_x_REG register corresponding to pad X, as mentioned in Section 4.2.2.
The output signal is routed from the peripheral into the GPIO Matrix. It is then routed into the IO_MUX, which is
configured to set the chosen pad to ”GPIO” function. This causes the output GPIO signal to be connected to the
pad.
Note:
The peripheral output signals 224 to 228 can be configured to be routed in from one GPIO and output directly from another
GPIO.
signal0_out 0 MCU_SEL
signal1_out 1
signal2_out 2
signal3_out 3
0 (FUNC)
1 (FUNC)
GPIO X out I/O Pad x
2 (GPIO)
GPIOx_out
signal228_out 228
FUN_OE = 1
GPIO_OUT_DATA bit x 256 (0x100)
256sdfsdfasdfgas
• If the signal should always be enabled as an output, set the GPIO_FUNCx_OEN_SEL bit in the
GPIO_FUNCx_OUT_SEL_CFG register and the GPIO_ENABLE_DATA[x] field in the
GPIO_ENABLE_REG register corresponding to GPIO pad X. To have the output enable signal decided
by internal logic, clear the GPIO_FUNCx_OEN_SEL bit instead.
2. For an open drain output, set the GPIO_PINx_PAD_DRIVER bit in the GPIO_PINx register corresponding to
GPIO pad X. For push/pull mode (default), clear this bit.
3. Configure the IO_MUX to select the GPIO Matrix. Set the IO_MUX_x_REG register corresponding to GPIO
pad X as follows:
• Set the function field (MCU_SEL) to the IO_MUX function corresponding to GPIO X (this is Function
#3—numeric value 2—for all pins).
• Set the FUN_DRV field to the desired value for output strength (0-3). The higher the drive strength, the
more current can be sourced/sunk from the pin.
• If using open drain mode, set/clear the FUN_WPU and FUN_WPD bits to enable/disable the internal
pull-up/down resistors.
Notes:
• The output signal from a single peripheral can be sent to multiple pads simultaneously.
To configure a pad as simple GPIO output, the GPIO Matrix GPIO_FUNCx_OUT_SEL register is configured with a
special peripheral index value (0x100).
Selecting this option is less flexible than using the GPIO Matrix, as the IO_MUX register for each GPIO pad can
only select from a limited number of functions. However, better high-frequency digital performance will be
maintained.
1. IO_MUX for the GPIO pad must be set to the required pad function. (Please refer to section 4.10 for a list of
pad functions.)
2. For inputs, the SIG_IN_SEL register must be set to route the input directly to the peripheral.
When configured as RTC GPIOs, the output pads can still retain the output level value when the chip is in
Deep-sleep mode, and the input pads can wake up the chip from Deep-sleep.
If the RTC_IO_TOUCH_PADx_TO_GPIO bit is cleared, then I/O to and from that pad is routed to the RTC
subsystem. In this mode, the RTC_GPIO_PINx register is used for digital I/O and the analog features of the pad
are also available. See Section 4.11 for a list of RTC pin functions.
See 4.11 for a table mapping GPIO pads to their RTC equivalent pins and analog functions. Note that the
RTC_IO_PINx registers use the RTC GPIO pin numbering, not the GPIO pad numbering.
If SLP_SEL is set to 0, the pin functions remain the same in both normal execution and Light-sleep mode.
to retain the pad state through a core reset and system reset triggered by watchdog time-out or Deep-sleep
events.
Note:
• For digital pads, to maintain the pad’s input/output status in Deep-sleep mode, you can set
REG_DG_PAD_FORCE_UNHOLD to 0 before powering down.
For RTC pads, the input and output values are controlled by the corresponding bits of register
RTC_CNTL_HOLD_FORCE_REG, and you can set it to 1 to hold the value or set it to 0 to unhold the value.
• For digital pads, to disable the hold function after the chip is woken up, you can set REG_DG_PAD_FORCE_UNHOLD
to 1. To maintain the hold function of the pad, you can change the corresponding bit in the register by setting
RTC_CNTL_HOLD_FORCE_REG to 1.
GPIO22
GPIO19
XTAL_N
XTAL_P
U0RXD
U0TXD
VDDA
VDDA
CAP1
CAP2
48
47
46
45
44
43
42
41
40
39
38
37
VDDA 1 36 GPIO23
LNA_IN 2 35 GPIO18
VDD3P3 3 34 GPIO5
VDD3P3 4 33 SD_DATA_1
SENSOR_VP 5 32 SD_DATA_0
SENSOR_VN 8 29 SD_DATA_3
CHIP_PU 9 28 SD_DATA_2
VDET_1 10 27 GPIO17
VDET_2 11 26 VDD_SDIO
32K_XP 12 25 GPIO16
13
14
15
16
17
18
19
20
21
22
23
24
Analog pads
32K_XN
GPIO25
GPIO26
GPIO27
MTMS
MTDI
VDD3P3_RTC
MTCK
MTDO
GPIO2
GPIO0
GPIO4
Figure 10: ESP32 I/O Pad Power Sources (QFN 6*6, Top View)
• Pads marked blue are RTC pads that have their individual analog function and can also act as normal
digital IO pads. For details, please see Section 4.11.
• Pads marked green can be powered externally or internally via VDD_SDIO (see below).
GPIO21
GPIO22
XTAL_N
XTAL_P
U0RXD
U0TXD
VDDA
VDDA
CAP1
CAP2
48
47
46
45
44
43
42
41
40
39
VDDA 1 38 GPIO19
LNA_IN 2 37 VDD3P3_CPU
VDD3P3 3 36 GPIO23
VDD3P3 4 35 GPIO18
SENSOR_VP 5 34 GPIO5
SENSOR_CAPP 6 33 SD_DATA_1
SENSOR_CAPN 7 32 SD_DATA_0
ESP32
49 GND
SENSOR_VN 8 31 SD_CLK
CHIP_PU 9 30 SD_CMD
VDET_1 10 29 SD_DATA_3
VDET_2 11 28 SD_DATA_2
32K_XP 12 27 GPIO17
32K_XN 13 26 VDD_SDIO
GPIO25 14 25 GPIO16
15
16
17
18
19
20
21
22
23
24
Analog pads
GPIO26
GPIO27
MTMS
MTDI
VDD3P3_RTC
MTCK
MTDO
GPIO2
GPIO0
Figure 11: ESP32 I/O Pad Power Sources (QFN 5*5, Top View)
Without an external power supply, the internal regulator will supply VDD_SDIO. The VDD_SDIO voltage can be
configured to be either 1.8V or the same as VDD3P3_RTC, depending on the state of the MTDI pad at reset – a
high level configures 1.8V and a low level configures the voltage to be the same as VDD3P3_RTC. Setting the
efuse bit determines the default voltage of the VDD_SDIO. In addition, software can change the voltage of the
VDD_SDIO by configuring register bits.
Direct I/O in IO_MUX ”YES” means that this signal is also available directly via IO_MUX. To apply the GPIO
Matrix to these signals, their corresponding SIG_IN_SEL register must be cleared.
GPIO Pad Name Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Reset Notes
0 GPIO0 GPIO0 CLK_OUT1 GPIO0 - - EMAC_TX_CLK 3 R
1 U0TXD U0TXD CLK_OUT3 GPIO1 - - EMAC_RXD2 3 -
2 GPIO2 GPIO2 HSPIWP GPIO2 HS2_DATA0 SD_DATA0 - 2 R
3 U0RXD U0RXD CLK_OUT2 GPIO3 - - - 3 -
4 GPIO4 GPIO4 HSPIHD GPIO4 HS2_DATA1 SD_DATA1 EMAC_TX_ER 2 R
5 GPIO5 GPIO5 VSPICS0 GPIO5 HS1_DATA6 - EMAC_RX_CLK 3 -
6 SD_CLK SD_CLK SPICLK GPIO6 HS1_CLK U1CTS - 3 -
7 SD_DATA_0 SD_DATA0 SPIQ GPIO7 HS1_DATA0 U2RTS - 3 -
8 SD_DATA_1 SD_DATA1 SPID GPIO8 HS1_DATA1 U2CTS - 3 -
9 SD_DATA_2 SD_DATA2 SPIHD GPIO9 HS1_DATA2 U1RXD - 3 -
10 SD_DATA_3 SD_DATA3 SPIWP GPIO10 HS1_DATA3 U1TXD - 3 -
11 SD_CMD SD_CMD SPICS0 GPIO11 HS1_CMD U1RTS - 3 -
12 MTDI MTDI HSPIQ GPIO12 HS2_DATA2 SD_DATA2 EMAC_TXD3 2 R
13 MTCK MTCK HSPID GPIO13 HS2_DATA3 SD_DATA3 EMAC_RX_ER 1 R
14 MTMS MTMS HSPICLK GPIO14 HS2_CLK SD_CLK EMAC_TXD2 1 R
GPIO Pad Name Function 1 Function 2 Function 3 Function 4 Function 5 Function 6 Reset Notes
15 MTDO MTDO HSPICS0 GPIO15 HS2_CMD SD_CMD EMAC_RXD3 3 R
16 GPIO16 GPIO16 - GPIO16 HS1_DATA4 U2RXD EMAC_CLK_OUT 1 -
17 GPIO17 GPIO17 - GPIO17 HS1_DATA5 U2TXD EMAC_CLK_180 1 -
18 GPIO18 GPIO18 VSPICLK GPIO18 HS1_DATA7 - - 1 -
19 GPIO19 GPIO19 VSPIQ GPIO19 U0CTS - EMAC_TXD0 1 -
21 GPIO21 GPIO21 VSPIHD GPIO21 - - EMAC_TX_EN 1 -
22 GPIO22 GPIO22 VSPIWP GPIO22 U0RTS - EMAC_TXD1 1 -
23 GPIO23 GPIO23 VSPID GPIO23 HS1_STROBE - - 1 -
25 GPIO25 GPIO25 - GPIO25 - - EMAC_RXD0 0 R
26 GPIO26 GPIO26 - GPIO26 - - EMAC_RXD1 0 R
27 GPIO27 GPIO27 - GPIO27 - - EMAC_RX_DV 1 R
32 32K_XP GPIO32 - GPIO32 - - - 0 R
33 32K_XN GPIO33 - GPIO33 - - - 0 R
34 VDET_1 GPIO34 - GPIO34 - - - 0 R, I
35 VDET_2 GPIO35 - GPIO35 - - - 0 R, I
36 SENSOR_VP GPIO36 - GPIO36 - - - 0 R, I
37 SENSOR_CAPP GPIO37 - GPIO37 - - - 0 R, I
38 SENSOR_CAPN GPIO38 - GPIO38 - - - 0 R, I
39 SENSOR_VN GPIO39 - GPIO39 - - - 0 R, I
Reset Configurations
Notes
Please refer to the ESP32 Pin Lists in ESP32 Datasheet for more details.
4.13 Registers
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
GPIO_OUT_W1TS_REG GPIO0-31 output set register. For every bit that is 1 in the value written here,
the corresponding bit in GPIO_OUT_REG will be set. (WO)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
GPIO_OUT_W1TC_REG GPIO0-31 output clear register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT_REG will be cleared. (WO)
_O
ve
r
O
se
PI
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
TA
_ DA
UT
d)
_O
ve
r
O
se
PI
(re
G
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
GPIO_OUT_DATA GPIO32-39 output value set register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT1_DATA will be set. (WO)
A
AT
_D
UT
)
ed
_O
rv
O
se
PI
(re
G
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
GPIO_OUT_DATA GPIO32-39 output value clear register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_OUT1_DATA will be cleared. (WO)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
GPIO_ENABLE_W1TS_REG GPIO0-31 output enable set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE will be set. (WO)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
GPIO_ENABLE_W1TC_REG GPIO0-31 output enable clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_ENABLE will be cleared. (WO)
A
AT
_D
B LE
NA
d )
_E
ve
r
O
se
PI
(re
G
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
TA
DA
E_
BL
NA
d )
_E
ve
r
O
se
PI
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
GPIO_ENABLE_DATA GPIO32-39 output enable set register. For every bit that is 1 in the value written
here, the corresponding bit in GPIO_ENABLE1 will be set. (WO)
_E
rv
O
se
PI
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
GPIO_ENABLE_DATA GPIO32-39 output enable clear register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_ENABLE1 will be cleared. (WO)
NG
PI
AP
TR
)
ed
_S
v
er
O
s
PI
(re
G
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x x x Reset
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
GPIO_IN_REG GPIO0-31 input value. Each bit represents a pad input value, 1 for high level and 0
for low level. (RO)
XT
NE
_
TA
DA
N_
)
ed
_I
rv
O
se
PI
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
GPIO_IN_DATA_NEXT GPIO32-39 input value. Each bit represents a pad input value. (RO)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
GPIO_STATUS_REG GPIO0-31 interrupt status register. Each bit can be either of the two interrupt
sources for the two CPUs. The enable bits in GPIO_STATUS_INTERRUPT, corresponding to the
0-4 bits in GPIO_PINn_REG should be set to 1. (R/W)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
GPIO_STATUS_W1TS_REG GPIO0-31 interrupt status set register. For every bit that is 1 in the value
written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be set. (WO)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
GPIO_STATUS_W1TC_REG GPIO0-31 interrupt status clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS_INTERRUPT will be cleared. (WO)
PT
RU
T ER
IN
S_
TU
TA
d )
_S
ve
r
O
se
PI
(re
31 8 7 G 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
_S
rv
O
se
PI
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status set register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be set. (WO)
P T
RU
TER
IN
S_
TU
TA
d)
_S
ve
r
O
se
PI
(re
G
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
GPIO_STATUS_INTERRUPT GPIO32-39 interrupt status clear register. For every bit that is 1 in the
value written here, the corresponding bit in GPIO_STATUS_INTERRUPT1 will be cleared. (WO)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
T
IN
U_
CP
PP
d)
_A
ve
r
O
se
PI
(re
G
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
T
IN
I_
NM
U_
CP
PP
)
ed
_A
rv
O
se
PI
(re
G
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
T
IN
U_
CP
RO
)
ed
_P
rv
O
se
PI
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
_P
e
rv
O
se
PI
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
LE
AB
EN
ER
P_
IV
PE
A
DR
EU
EN
TY
D_
AK
T_
_
NT
rv _PA
IN
_I
n_
n_
n
IN
IN
IN
(re PIN
d)
)
ed
ed
ed
_P
_P
_P
ve
rv
rv
_
er
O
se
se
se
s
PI
PI
PI
PI
(re
(re
(re
G
G
31 18 17 13 12 11 10 9 7 6 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x 0 0 x x x x 0 0 0 0 x 0 0 Reset
GPIO_PINn_WAKEUP_ENABLE GPIO wake-up enable will only wake up the CPU from Light-sleep.
(R/W)
L
SE
IN
_I L
E
N_
N_
C m _S
_I
UN IN
Cm
_F _
O m
UN
PI IG
d)
G O_S
ve
_F
r
O
se
PI
PI
(re
31 8 7 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x Reset
GPIO_SIGm_IN_SEL Bypass the GPIO Matrix. 1: route through GPIO Matrix, 0: connect signal
directly to peripheral configured in the IO_MUX. (R/W)
GPIO_FUNCm_IN_SEL Selection control for peripheral input m. A value of 0-39 selects which of the
40 GPIO Matrix input pins this signal is connected to, or 0x38 for a constantly high input or 0x30
for a constantly low input. (R/W)
UT SE EL
EL
_O N_ _S
_S
_I L
EL
Cn OE INV
NV
_S
UN n_ N_
UT
_F C E
O N O
_O
PI U n _
Cn
G O_F NC
UN
)
PI U
ed
G O_F
_F
rv
O
se
PI
PI
(re
G
31 12 11 10 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x Reset
GPIO_FUNCn_OEN_INV_SEL 1: Invert the output enable signal; 0: do not invert the output enable
signal. (R/W)
GPIO_FUNCn_OUT_INV_SEL 1: Invert the output value; 0: do not invert the output value. (R/W)
1
LK
LK
LK
_C
_C
_C
RL
RL
RL
)
ed
CT
CT
CT
rv
se
N_
N_
N_
(re
PI
PI
PI
31 12 11 8 7 4 3 0
Note:
Only the above mentioned combinations of clock source and clock output pins are possible.
The CLK_OUT1-3 can be found in the IO_MUX Pad Summary.
SL _W U
M _SE D
CU V
N_ PU
CU D
L
FU RV
CU P
P P
)
CU L
E
ed
P
SE
M _W
M _IE
_O
_D
FU _W
W
FU IE
D
rv
N_
N_
CU
CU
se
N
FU
(re
M
31 15 14 12 11 10 9 8 7 6 5 4 3 2 1 0
MCU_SEL Select the IO_MUX function for this signal. 0 selects Function 1, 1 selects Function 2, etc.
(R/W)
FUN_DRV Select the drive strength of the pad. A higher value corresponds with a higher strength.
For GPIO34-39, FUN_DRV is always 0. (R/W)
FUN_IE Input enable of the pad. 1: input enabled; 0: input disabled. (R/W)
FUN_WPU Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled. For
GPIO34-39, FUN_WPU is always 0. (R/W)
FUN_WPD Pull-down enable of the pad. 1: internal pull-down enabled, 0: internal pull-down dis-
abled. For GPIO34-39, FUN_WPD is always 0. (R/W)
MCU_DRV Select the drive strength of the pad during sleep mode. A higher value corresponds with
a higher strength. (R/W)
MCU_IE Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled. (R/W)
MCU_WPU Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal
pull-up disabled. (R/W)
MCU_WPD Pull-down enable of the pad during sleep mode. 1: internal pull-down enabled; 0: internal
pull-down disabled. (R/W)
SLP_SEL Sleep mode selection of this pad. Set to 1 to put the pad in sleep mode. (R/W)
MCU_OE Output enable of the pad in sleep mode. 1: enable output; 0: disable output. (R/W)
)
_R
ed
rv
O
CI
se
RT
(re
31 14 13 0
x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
S
1T
A _W
AT
_D
UT
_O
O
PI
_G
TC
)
_R
ed
rv
O
CI
se
RT
(re
31 14 13 0
x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_RTC_GPIO_OUT_DATA_W1TS GPIO0-17 output set register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be set. (WO)
)
_R
ed
rv
O
CI
se
RT
(re
31 14 13 0
x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_RTC_GPIO_OUT_DATA_W1TC GPIO0-17 output clear register. For every bit that is 1 in the
value written here, the corresponding bit in RTCIO_RTC_GPIO_OUT will be cleared. (WO)
)
_R
ed
rv
O
CI
se
RT
(re
31 14 13 0
x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
S
1T
_W
B LE
NA
_E
O
PI
_ G
TC
)
_R
ed
rv
O
CI
se
RT
(re
31 14 13 0
x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_RTC_GPIO_ENABLE_W1TS GPIO0-17 output enable set register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be set. (WO)
)
_R
ed
rv
O
CI
se
RT
(re
31 14 13 0
x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_RTC_GPIO_ENABLE_W1TC GPIO0-17 output enable clear register. For every bit that is 1 in
the value written here, the corresponding bit in RTCIO_RTC_GPIO_ENABLE will be cleared. (WO)
)
_R
ed
rv
O
CI
se
RT
(re
31 14 13 0
x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
S
1T
_W
NT
S _I
TU
TA
_S
O
PI
_G
TC
)
_R
ed
rv
O
CI
se
RT
(re
31 14 13 0
x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
)
_R
ed
rv
O
CI
se
RT
(re
31 14 13 0
x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
)
_R
ed
rv
O
CI
se
RT
(re
31 14 13 0
x x x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_RTC_GPIO_IN_NEXT GPIO0-17 input value. Bit14 is GPIO[0], bit15 is GPIO[1], etc. Each
bit represents a pad input value, 1 for high level, and 0 for low level. (RO)
LE
AB
EN
ER
P_
IV
E
YP
DR
EU
D_
AK
T_
PA
IN
W
n_
n_
n_
IN
IN
IN
_P
_P
_P
O
IO
PI
PI
ed GP
_G
_G
C_
TC
TC
(re _RT
)
)
_R
_R
ed
ed
rv
rv
rv
O
O
CI
CI
CI
se
se
se
RT
RT
RT
(re
(re
31 11 10 9 7 6 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x 0 0 0 0 x 0 0 Reset
31 0
0 Reset
RTCIO_DIG_PAD_HOLD_REG Selects the digital pads which should be put on hold. While 0 allows
normal operation, 1 puts the pad on hold. (R/W)
Name Description
Bit[0] Set to 1 to enable the Hold function of pad U0RTD
Bit[1] Set to 1 to enable the Hold function of pad U0TXD
Bit[2] Set to 1 to enable the Hold function of pad
SD_CLK
Bit[3] Set to 1 to enable the Hold function of pad
SD_DATA0
Bit[4] Set to 1 to enable the Hold function of pad
SD_DATA1
Bit[5] Set to 1 to enable the Hold function of pad
SD_DATA2
Bit[6] Set to 1 to enable the Hold function of pad
SD_DATA3
Bit[7] Set to 1 to enable the Hold function of pad
SD_CMD
Bit[8] Set to 1 to enable the Hold function of pad GPIO5
Bit[9] Set to 1 to enable the Hold function of pad GPIO16
Bit[10] Set to 1 to enable the Hold function of pad GPIO17
Bit[11] Set to 1 to enable the Hold function of pad GPIO18
Bit[12] Set to 1 to enable the Hold function of pad GPIO19
Bit[13] Set to 1 to enable the Hold function of pad GPIO20
Bit[14] Set to 1 to enable the Hold function of pad GPIO21
Bit[15] Set to 1 to enable the Hold function of pad GPIO22
Bit[16] Set to 1 to enable the Hold function of pad GPIO23
AS ALL
E
PH H
L_ D_
AL XP
_H L_
O L
CI HA
d)
ve
RT IO_
er
C
s
RT
(re
31 30 29 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CI ENS R_ NS FUN L
NS SE E2 LP L
NS SE E3 LP L
L
RT IO_ EN _SE 1_F P_I L
4_ P_ L
NS SE E3 U SE
CI SE R_ SE4 MU SE
RT _SE R_ NS 1_S SE
SE
E L E
E L E
E L E
SE SL SE
E
_S S S E4_ _IE
IE
_S
U E
UN E
UN E
FU IE
RT IO_ SO ENS 1_S P_S
NS _S _S
NS _S _S
RT IO_ EN R_ ENS 2_H LD
RT IO_ EN R_ ENS 3_H LD
O N R N _ LD
NS R_ NS _M LD
E2 N_I
_I
RT _SE R_ ENS 2_M X_
N_
N_
4_ P_
CI ENS R_ NS FUN
CI ENS R_ NS FUN
O S E U
C S SO S E O
C S SO S E O
CI SE SO SE E4 O
RT _SE SO _SE SE1 HO
FU
S E L
SE E L
RT IO_ EN R_ ENS 1_H
S
_
R_ N 4_
1
3
C S SO S E
O N R_ SE
SE E
SO _S SE
RT IO_ EN R_ ENS
NS
NS
NS
S
N
EN OR EN
N
SE
S O SE
S O SE
S SO SE
E
C S SO S
S
RT IO_ EN R_
O N R_
O N R_
O N R_
R
R
C S SO
CI SE SO
CI SE SO
CI SE SO
CI SE SO
S
S
RT IO_ EN
R T O_ N
)
C S
C S
C S
ed
RT IO_
RT O_
RT O_
R T O_
rv
O
O
CI
CI
CI
CI
se
C
C
C
RT
RT
RT
RT
(re
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_SENSOR_SENSEn_HOLD Set to 1 to hold the output value on sensen; 0 is for normal op-
eration. (R/W)
RTCIO_SENSOR_SENSEn_FUN_SEL Select the RTC IO_MUX function for this pad. 0: select Func-
tion 0; 1: select Function 1. (R/W)
RTCIO_SENSOR_SENSEn_SLP_SEL Selection of sleep mode for the pad: set to 1 to put the pad
in sleep mode. (R/W)
C1 X_ L
L
DC AD _S SEL
1 P L
2_ LP_ EL
AD MU _SE
_F SE
RT _AD _A 1_ _SE
AD DC _SL _SE
_F IE
IE
RT IO_ _A _FU _IE
FU IE
DC _S _S
RT _AD _A 2_ OLD
AD 1_ LD
C2 N_
N_
_ X
O C DC UN
O C DC UN
A 1 P
_A 2 P
C2 MU
C_ DC HO
C_ DC SL
L
O C DC H
CI AD _A 1_
_A _ 2
RT IO_ DC DC
C
D
C A _A
CI AD _A
CI AD A
_
_
RT IO_ DC
CI DC
RT IO_ DC
RT IO_ DC
)
C A
C A
ed
RT IO_
RT O_
rv
O
O
CI
CI
se
C
C
RT
RT
RT
(re
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_ADC_ADCn_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)
RTCIO_ADC_ADCn_FUN_SEL Select the RTC function for this pad. 0: select Function 0; 1: select
Function 1. (R/W)
RTCIO_ADC_ADCn_SLP_SEL Signal selection of pad’s sleep mode. Set this bit to 1 to put the pad
to sleep. (R/W)
RTCIO_ADC_ADCn_SLP_IE Input enable of the pad in sleep mode. 1 enabled; 0 disabled. (R/W)
E
RC
O
_F
RT IO_ AD_ C1 X_S C
PD
UN L
AD D 1_ P_ L
E
U A
SE
C1 FUN OE
_P _P C L E
AC E
_P AC SL IE
_X
RT IO_ _PD _M _D
O D A _S _S
DA 1_ LD
_ D _I
_
DA 1_ P_
AC
RV
_R E
UE
C1 PD
CI PA PD C1 LP
_P AC HO
C1 RD
CI PA PD _D
_D
RT IO_ AD_ DA _S
RT _PA DA _X
CI PA PD _F
AD D 1_
RT IO_ AD_ C1
C1
P C1
1
_P _P C
C
A
O D A
DA
D_ A
RT O_ D_ A
RT O_ _PD
RT _PA _PD
_P
P
D
AD
O D
D
RT _PA
CI PA
)
P
_P
C P
ed
RT IO_
rv
O
O
CI
CI
CI
CI
se
C
C
RT
RT
RT
(re
31 30 29 28 27 26 19 18 17 16 15 14 13 12 11 10 9 0
2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_PAD_PDAC1_HOLD Set to 1 to hold the output value on the pad; set to 0 for normal oper-
ation. (R/W)
RTCIO_PAD_PDAC1_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the
pad to sleep. (R/W)
RTCIO_PAD_PDAC1_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)
E
RC
O
_F
RT IO_ AD_ C2 X_S C
PD
UN L
AD D 2_ P_ L
E
U A
SE
C2 FUN OE
_P _P C L E
AC E
_P AC SL IE
_X
RT IO_ _PD _M _D
O D A _S _S
DA 2_ LD
_ D _I
_
DA 2_ P_
AC
RV
_R E
UE
C2 PD
CI PA PD C2 LP
_P AC HO
C2 RD
CI PA PD _D
_D
RT IO_ AD_ DA _S
RT _PA DA _X
CI PA PD _F
AD D 2_
RT IO_ AD_ C2
C2
P C2
2
_P _P C
C
A
O D A
DA
D_ A
RT O_ D_ A
RT O_ _PD
RT _PA _PD
_P
P
D
AD
O D
D
RT _PA
CI PA
)
P
_P
C P
ed
RT IO_
rv
O
O
CI
CI
CI
CI
se
C
C
RT
RT
RT
(re
31 30 29 28 27 26 19 18 17 16 15 14 13 12 11 10 9 0
2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_PAD_PDAC2_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)
RTCIO_PAD_PDAC2_FUN_SEL Select the RTC function for this pad. 0: select Function 0; 1: select
Function 1. (R/W)
RTCIO_PAD_PDAC2_SLP_SEL Sleep mode selection signal of the pad. Set this bit to 1 to put the
pad to sleep. (R/W)
RTCIO_PAD_PDAC2_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)
2K
2K
32 UX EL
L
EL
K
L
_X N_ P_ L
P_ UX K
_X P_ P_ L
_F SE
_3
_X _FU _OE
CI XT _X P_ _SE
RE N_ E
AL 32 SL SE
RT _XT L_X D_X _32
_3
AL 2 L E
32 M 32
P_ _IE
M _S
IE
32 SL IE
S
32 SL IE
FU O
S
AL
32 RD D
_X P_ LD
_
N_
AL
RT _XT L_X N_ LP_
_X N_ L_
RT _XT L_X P_ P_
P_ P_
_X N_ L
O AL 32 RV
N E
2P E
N
O AL 32 RV
P_ E
E
UN
N P
XT
CI TAL 32 HO
CI TAL 32 HO
_X _RU
TA
XT
32 RD
RU
U
AL 32 TA
O A 32 SL
D
O A 32 S
_D
S
F
S_
RT IO_ TAL C_X
S_
N_
X _X N_
CI T X _
X _X P_
IA
32
RT O_ AL 32
32
RT IO_ TAL 32
DB
A
O A P
3
3
RT IO_ L_D
D
_X
CI XT _X
CI XT _X
CI XT _X
RT IO_ L_X
CI XT _X
X
_
L_
_
CI TAL
RT IO_ TAL
RT IO_ TAL
RT _ L
CI TAL
RT O_ AL
AL
A
A
RT _XT
RT _XT
RT _XT
CI XT
CI XT
(re _XT
)
ed
_X
C X
C X
C X
C X
_X
RT O_
R T O_
RT O_
rv
O
O
CI
CI
CI
CI
CI
CI
se
C
C
RT
RT
RT
RT
RT
RT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset
RTCIO_XTAL_X32N_HOLD Set to 1 to hold the output value on the pad; 0 is for normal operation.
(R/W)
RTCIO_XTAL_X32P_HOLD Set to 1 to hold the output value on the pad, 0 is for normal operation.
(R/W)
RTCIO_XTAL_X32N_MUX_SEL 0: route X32N pad to the digital IO_MUX; 1: route to RTC block.
(R/W)
RTCIO_XTAL_X32P_MUX_SEL 0: route X32P pad to the digital IO_MUX; 1: route to RTC block.
(R/W)
RTCIO_XTAL_X32N_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W)
RTCIO_XTAL_X32N_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)
RTCIO_XTAL_X32P_SLP_SEL Sleep mode selection. Set this bit to 1 to put the pad to sleep. (R/W)
RTCIO_XTAL_X32P_SLP_IE Input enable of the pad in sleep mode. 1: enabled; 0: disabled. (R/W)
E
IA
G
FH
H_ _B
UR
AN
EF
D
DC
DR
DR
O _XP
H_
H_
H_
H
UC
UC
UC
UC
UC
RT _TO
)
ed
_T
_T
_T
_T
rv
O
O
CI
CI
CI
CI
CI
se
RT
RT
RT
RT
(re
31 30 29 28 27 26 25 24 23 22 0
0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_TOUCH_XPD_BIAS Touch sensor bias power on bit. 1: power on; 0: disabled. (R/W)
RTCIO_TOUCH_DCUR Touch sensor bias current. When BIAS_SLEEP is enabled, this setting is
available. (R/W)
EL
_F PIO
H_ n_T D T
D P P
_S
H AD TIE T
O _PA n_X _O
Dn _G
UC _P n_ AR
AC
UN
O
RT _TO CH AD _ST
_D
Dn
O U _P n
CI TO CH AD
PA
PA
RT O_ U _P
H_
CI TO CH
UC
UC
RT O_ U
O
CI TO
)
)
ed
ed
_T
_T
R T O_
rv
rv
O
O
CI
CI
CI
se
se
RT
RT
(re
(re
31 26 25 23 22 21 20 19 18 17 16 0
0 0 0 0 0 0 0x4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_TOUCH_PADn_DAC Touch sensor slope control. 3-bit for each touch pad, defaults to 100.
(R/W)
RTCIO_TOUCH_PADn_TIE_OPT Default touch sensor tie option. 0: tie low; 1: tie high. (R/W)
RTCIO_TOUCH_PADn_TO_GPIO Connect the RTC pad input to digital pad input; 0 is available.
(R/W)
d)
_E
e
rv
O
CI
se
RT
(re
31 27 26 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_EXT_WAKEUP0_SEL GPIO[0-17] can be used to wake up the chip when the chip is in the
sleep mode. This register prompts the pad source to wake up the chip when the latter is in
deep/light sleep mode. 0: select GPIO0; 1: select GPIO2, etc. (R/W)
L
SE
R_
CT
X T_
_E
TL
d)
_X
ve
O
er
CI
s
RT
(re
31 27 26 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_XTL_EXT_CTR_SEL Select the external crystal power down enable source to get into
sleep mode. 0: select GPIO0; 1: select GPIO2, etc. The input value on this pin XOR RT-
CIO_RTC_EXT_XTAL_CONF_REG[30] is the crystal power down enable signal. (R/W)
EL
_S
_S
DA
CL
_S
_S
2C
2C
_I
_I
AR
AR
d)
_S
_S
e
rv
O
O
CI
CI
se
RT
RT
(re
31 30 29 28 27 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTCIO_SAR_I2C_SDA_SEL Selects the other pad as the RTC I2C SDA signal. 0: pad
TOUCH_PAD[1]; 1: pad TOUCH_PAD[3]. Default value is 0. (R/W)
RTCIO_SAR_I2C_SCL_SEL Selects the other pad as the RTC I2C SCL signal. 0: pad
TOUCH_PAD[0]; 1: pad TOUCH_PAD[2]. Default value is 0. (R/W)
5. DPort Register
5.1 Introduction
The ESP32 integrates a large number of peripherals, and enables the control of individual peripherals to achieve
optimal characteristics in performance-vs-power-consumption scenarios. The DPort registers control clock
management (clock gating), power management, and the configuration of peripherals and core-system modules.
The system arranges each module with configuration registers contained in the DPort Register.
5.2 Features
DPort registers correspond to different peripheral blocks and core modules:
• Interrupt matrix
• DMA
• PID/MPU/MMU
• APP_CPU
• DPORT_PRO_BOOT_REMAP_CTRL_REG
• DPORT_APP_BOOT_REMAP_CTRL_REG
• DPORT_CACHE_MUX_MODE_REG
• DPORT_CPU_PER_CONF_REG
• DPORT_CPU_INTR_FROM_CPU_0_REG
• DPORT_CPU_INTR_FROM_CPU_1_REG
• DPORT_CPU_INTR_FROM_CPU_2_REG
• DPORT_CPU_INTR_FROM_CPU_3_REG
• DPORT_PRO_INTR_STATUS_0_REG
• DPORT_PRO_INTR_STATUS_1_REG
• DPORT_PRO_INTR_STATUS_2_REG
• DPORT_APP_INTR_STATUS_0_REG
• DPORT_APP_INTR_STATUS_1_REG
• DPORT_APP_INTR_STATUS_2_REG
• DPORT_PRO_MAC_INTR_MAP_REG
• DPORT_PRO_MAC_NMI_MAP_REG
• DPORT_PRO_BB_INT_MAP_REG
• DPORT_PRO_BT_MAC_INT_MAP_REG
• DPORT_PRO_BT_BB_INT_MAP_REG
• DPORT_PRO_BT_BB_NMI_MAP_REG
• DPORT_PRO_RWBT_IRQ_MAP_REG
• DPORT_PRO_RWBLE_IRQ_MAP_REG
• DPORT_PRO_RWBT_NMI_MAP_REG
• DPORT_PRO_RWBLE_NMI_MAP_REG
• DPORT_PRO_SLC0_INTR_MAP_REG
• DPORT_PRO_SLC1_INTR_MAP_REG
• DPORT_PRO_UHCI0_INTR_MAP_REG
• DPORT_PRO_UHCI1_INTR_MAP_REG
• DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG
• DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG
• DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG
• DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG
• DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG
• DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG
• DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG
• DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG
• DPORT_PRO_GPIO_INTERRUPT_MAP_REG
• DPORT_PRO_GPIO_INTERRUPT_NMI_MAP_REG
• DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG
• DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG
• DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG
• DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG
• DPORT_PRO_SPI_INTR_0_MAP_REG
• DPORT_PRO_SPI_INTR_1_MAP_REG
• DPORT_PRO_SPI_INTR_2_MAP_REG
• DPORT_PRO_SPI_INTR_3_MAP_REG
• DPORT_PRO_I2S0_INT_MAP_REG
• DPORT_PRO_I2S1_INT_MAP_REG
• DPORT_PRO_UART_INTR_MAP_REG
• DPORT_PRO_UART1_INTR_MAP_REG
• DPORT_PRO_UART2_INTR_MAP_REG
• DPORT_PRO_SDIO_HOST_INTERRUPT_MAP_REG
• DPORT_PRO_EMAC_INT_MAP_REG
• DPORT_PRO_PWM0_INTR_MAP_REG
• DPORT_PRO_PWM1_INTR_MAP_REG
• DPORT_PRO_PWM2_INTR_MAP_REG
• DPORT_PRO_PWM3_INTR_MAP_REG
• DPORT_PRO_LEDC_INT_MAP_REG
• DPORT_PRO_EFUSE_INT_MAP_REG
• DPORT_PRO_CAN_INT_MAP_REG
• DPORT_PRO_RTC_CORE_INTR_MAP_REG
• DPORT_PRO_RMT_INTR_MAP_REG
• DPORT_PRO_PCNT_INTR_MAP_REG
• DPORT_PRO_I2C_EXT0_INTR_MAP_REG
• DPORT_PRO_I2C_EXT1_INTR_MAP_REG
• DPORT_PRO_RSA_INTR_MAP_REG
• DPORT_PRO_SPI1_DMA_INT_MAP_REG
• DPORT_PRO_SPI2_DMA_INT_MAP_REG
• DPORT_PRO_SPI3_DMA_INT_MAP_REG
• DPORT_PRO_WDG_INT_MAP_REG
• DPORT_PRO_TIMER_INT1_MAP_REG
• DPORT_PRO_TIMER_INT2_MAP_REG
• DPORT_PRO_TG_T0_EDGE_INT_MAP_REG
• DPORT_PRO_TG_T1_EDGE_INT_MAP_REG
• DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG
• DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG
• DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG
• DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG
• DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG
• DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG
• DPORT_PRO_MMU_IA_INT_MAP_REG
• DPORT_PRO_MPU_IA_INT_MAP_REG
• DPORT_PRO_CACHE_IA_INT_MAP_REG
• DPORT_APP_MAC_INTR_MAP_REG
• DPORT_APP_MAC_NMI_MAP_REG
• DPORT_APP_BB_INT_MAP_REG
• DPORT_APP_BT_MAC_INT_MAP_REG
• DPORT_APP_BT_BB_INT_MAP_REG
• DPORT_APP_BT_BB_NMI_MAP_REG
• DPORT_APP_RWBT_IRQ_MAP_REG
• DPORT_APP_RWBLE_IRQ_MAP_REG
• DPORT_APP_RWBT_NMI_MAP_REG
• DPORT_APP_RWBLE_NMI_MAP_REG
• DPORT_APP_SLC0_INTR_MAP_REG
• DPORT_APP_SLC1_INTR_MAP_REG
• DPORT_APP_UHCI0_INTR_MAP_REG
• DPORT_APP_UHCI1_INTR_MAP_REG
• DPORT_APP_TG_T0_LEVEL_INT_MAP_REG
• DPORT_APP_TG_T1_LEVEL_INT_MAP_REG
• DPORT_APP_TG_WDT_LEVEL_INT_MAP_REG
• DPORT_APP_TG_LACT_LEVEL_INT_MAP_REG
• DPORT_APP_TG1_T0_LEVEL_INT_MAP_REG
• DPORT_APP_TG1_T1_LEVEL_INT_MAP_REG
• DPORT_APP_TG1_WDT_LEVEL_INT_MAP_REG
• DPORT_APP_TG1_LACT_LEVEL_INT_MAP_REG
• DPORT_APP_GPIO_INTERRUPT_MAP_REG
• DPORT_APP_GPIO_INTERRUPT_NMI_MAP_REG
• DPORT_APP_CPU_INTR_FROM_CPU_0_MAP_REG
• DPORT_APP_CPU_INTR_FROM_CPU_1_MAP_REG
• DPORT_APP_CPU_INTR_FROM_CPU_2_MAP_REG
• DPORT_APP_CPU_INTR_FROM_CPU_3_MAP_REG
• DPORT_APP_SPI_INTR_0_MAP_REG
• DPORT_APP_SPI_INTR_1_MAP_REG
• DPORT_APP_SPI_INTR_2_MAP_REG
• DPORT_APP_SPI_INTR_3_MAP_REG
• DPORT_APP_I2S0_INT_MAP_REG
• DPORT_APP_I2S1_INT_MAP_REG
• DPORT_APP_UART_INTR_MAP_REG
• DPORT_APP_UART1_INTR_MAP_REG
• DPORT_APP_UART2_INTR_MAP_REG
• DPORT_APP_SDIO_HOST_INTERRUPT_MAP_REG
• DPORT_APP_EMAC_INT_MAP_REG
• DPORT_APP_PWM0_INTR_MAP_REG
• DPORT_APP_PWM1_INTR_MAP_REG
• DPORT_APP_PWM2_INTR_MAP_REG
• DPORT_APP_PWM3_INTR_MAP_REG
• DPORT_APP_LEDC_INT_MAP_REG
• DPORT_APP_EFUSE_INT_MAP_REG
• DPORT_APP_CAN_INT_MAP_REG
• DPORT_APP_RTC_CORE_INTR_MAP_REG
• DPORT_APP_RMT_INTR_MAP_REG
• DPORT_APP_PCNT_INTR_MAP_REG
• DPORT_APP_I2C_EXT0_INTR_MAP_REG
• DPORT_APP_I2C_EXT1_INTR_MAP_REG
• DPORT_APP_RSA_INTR_MAP_REG
• DPORT_APP_SPI1_DMA_INT_MAP_REG
• DPORT_APP_SPI2_DMA_INT_MAP_REG
• DPORT_APP_SPI3_DMA_INT_MAP_REG
• DPORT_APP_WDG_INT_MAP_REG
• DPORT_APP_TIMER_INT1_MAP_REG
• DPORT_APP_TIMER_INT2_MAP_REG
• DPORT_APP_TG_T0_EDGE_INT_MAP_REG
• DPORT_APP_TG_T1_EDGE_INT_MAP_REG
• DPORT_APP_TG_WDT_EDGE_INT_MAP_REG
• DPORT_APP_TG_LACT_EDGE_INT_MAP_REG
• DPORT_APP_TG1_T0_EDGE_INT_MAP_REG
• DPORT_APP_TG1_T1_EDGE_INT_MAP_REG
• DPORT_APP_TG1_WDT_EDGE_INT_MAP_REG
• DPORT_APP_TG1_LACT_EDGE_INT_MAP_REG
• DPORT_APP_MMU_IA_INT_MAP_REG
• DPORT_APP_MPU_IA_INT_MAP_REG
• DPORT_APP_CACHE_IA_INT_MAP_REG
• DPORT_SPI_DMA_CHAN_SEL_REG
• DPORT_PRO_CACHE_CTRL_REG
• DPORT_APP_CACHE_CTRL_REG
• DPORT_IMMU_PAGE_MODE_REG
• DPORT_DMMU_PAGE_MODE_REG
• DPORT_AHB_MPU_TABLE_0_REG
• DPORT_AHB_MPU_TABLE_1_REG
• DPORT_AHBLITE_MPU_TABLE_UART_REG
• DPORT_AHBLITE_MPU_TABLE_SPI1_REG
• DPORT_AHBLITE_MPU_TABLE_SPI0_REG
• DPORT_AHBLITE_MPU_TABLE_GPIO_REG
• DPORT_AHBLITE_MPU_TABLE_FE2_REG
• DPORT_AHBLITE_MPU_TABLE_FE_REG
• DPORT_AHBLITE_MPU_TABLE_TIMER_REG
• DPORT_AHBLITE_MPU_TABLE_RTC_REG
• DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG
• DPORT_AHBLITE_MPU_TABLE_WDG_REG
• DPORT_AHBLITE_MPU_TABLE_HINF_REG
• DPORT_AHBLITE_MPU_TABLE_UHCI1_REG
• DPORT_AHBLITE_MPU_TABLE_I2S0_REG
• DPORT_AHBLITE_MPU_TABLE_UART1_REG
• DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG
• DPORT_AHBLITE_MPU_TABLE_UHCI0_REG
• DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG
• DPORT_AHBLITE_MPU_TABLE_RMT_REG
• DPORT_AHBLITE_MPU_TABLE_PCNT_REG
• DPORT_AHBLITE_MPU_TABLE_SLC_REG
• DPORT_AHBLITE_MPU_TABLE_LEDC_REG
• DPORT_AHBLITE_MPU_TABLE_EFUSE_REG
• DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG
• DPORT_AHBLITE_MPU_TABLE_PWM0_REG
• DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG
• DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG
• DPORT_AHBLITE_MPU_TABLE_SPI2_REG
• DPORT_AHBLITE_MPU_TABLE_SPI3_REG
• DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG
• DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG
• DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG
• DPORT_AHBLITE_MPU_TABLE_EMAC_REG
• DPORT_AHBLITE_MPU_TABLE_PWM1_REG
• DPORT_AHBLITE_MPU_TABLE_I2S1_REG
• DPORT_AHBLITE_MPU_TABLE_UART2_REG
• DPORT_AHBLITE_MPU_TABLE_PWM2_REG
• DPORT_AHBLITE_MPU_TABLE_PWM3_REG
• DPORT_AHBLITE_MPU_TABLE_PWR_REG
• DPORT_IMMU_TABLE0_REG
• DPORT_IMMU_TABLE1_REG
• DPORT_IMMU_TABLE2_REG
• DPORT_IMMU_TABLE3_REG
• DPORT_IMMU_TABLE4_REG
• DPORT_IMMU_TABLE5_REG
• DPORT_IMMU_TABLE6_REG
• DPORT_IMMU_TABLE7_REG
• DPORT_IMMU_TABLE8_REG
• DPORT_IMMU_TABLE9_REG
• DPORT_IMMU_TABLE10_REG
• DPORT_IMMU_TABLE11_REG
• DPORT_IMMU_TABLE12_REG
• DPORT_IMMU_TABLE13_REG
• DPORT_IMMU_TABLE14_REG
• DPORT_IMMU_TABLE15_REG
• DPORT_DMMU_TABLE0_REG
• DPORT_DMMU_TABLE1_REG
• DPORT_DMMU_TABLE2_REG
• DPORT_DMMU_TABLE3_REG
• DPORT_DMMU_TABLE4_REG
• DPORT_DMMU_TABLE5_REG
• DPORT_DMMU_TABLE6_REG
• DPORT_DMMU_TABLE7_REG
• DPORT_DMMU_TABLE8_REG
• DPORT_DMMU_TABLE9_REG
• DPORT_DMMU_TABLE10_REG
• DPORT_DMMU_TABLE11_REG
• DPORT_DMMU_TABLE12_REG
• DPORT_DMMU_TABLE13_REG
• DPORT_DMMU_TABLE14_REG
• DPORT_DMMU_TABLE15_REG
• When APP_CPU is booted up with a ROM code, it will jump to the address stored in the
DPORT_APPCPU_BOOT_ADDR register.
– BIT26, PWM3
– BIT25, PWM2
– BIT23, UART2
– BIT22, SPI_DMA
– BIT21, I2S1
– BIT20, PWM1
– BIT19, CAN
– BIT18, I2C1
– BIT17, PWM0
– BIT16, SPI3
– BIT14, eFuse
– BIT12, UHCI1
– BIT11, LED_PWM
– BIT10, PULSE_CNT
– BIT8, UHCI0
– BIT7, I2C0
– BIT6, SPI2
– BIT5, UART1
– BIT4, I2S0
– BIT3, WDG
– BIT2, UART
– BIT1, SPI
– BIT0, Timers
– BIT26, PWM3
– BIT25, PWM2
– BIT23, UART2
– BIT22, SPI_DMA
– BIT21, I2S1
– BIT20, PWM1
– BIT19, CAN
– BIT18, I2C1
– BIT17, PWM0
– BIT16, SPI3
– BIT14, eFuse
– BIT12, UHCI1
– BIT11, LED_PWM
– BIT10, PULSE_CNT
– BIT8, UHCI0
– BIT7, I2C0
– BIT6, SPI2
– BIT5, UART1
– BIT4, I2S0
– BIT3, WDG
– BIT2, UART
– BIT1, SPI
– BIT0, Timers
5.5 Registers
AP
M
RE
T_
O
d)
O
ve
_B
r
se
O
PR
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
AP
M
RE
T_
O
d)
BO
e
rv
P_
se
AP
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
NG
TI
ET
ES
_R
d)
PU
ve
PC
ser
AP
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
N
E_E
AT
G
LK
_C
d)
PU
e
rv
PC
se
AP
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
L
AL
ST
UN
_R
d)
PU
ve
PC
r
se
AP
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0x000000000 Reset
EL
S
D_
O
RI
E
UP
)
ed
CP
rv
U_
se
CP
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
NA _E NE
BL NA
_E SH DO
NA
E
HE FLU H_
_E
M
AC E_ US
_I T
RA
LE LI
_C H L
G P
L
O AC _F
_H
IN _S
PR _C HE
AM
_S M
O AC
O RA
)
)
ed
ed
ed
ed
R
PR _C
_D
PR _D
rv
rv
rv
rv
se
se
se
se
O
O
PR
PR
PR
(re
(re
(re
(re
31 17 16 15 12 11 10 9 6 5 4 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset
PRO_DRAM_HL Determines the virtual address mode of the external SRAM. (R/W)
PRO_DRAM_SPLIT Determines the virtual address mode of the external SRAM. (R/W)
PRO_SINGLE_IRAM_ENA Determines a special mode for PRO_CPU access to the external flash.
(R/W)
AB _EN E
EN H ON
LE A
NA
E_ LUS _D
_E
CH _F SH
M
_I T
CA HE LU
RA
LE PLI
L
P_ AC _F
_H
NG S
AP _C HE
SI M_
M
P AC
(re RA
P_ RA
d)
d)
)
ed
ed
ve
AP _C
D
AP D
rv
rv
rv
r
P_
P_
se
se
se
se
P
AP
AP
AP
(re
(re
(re
31 15 14 13 12 11 10 9 6 5 4 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Reset
APP_DRAM_HL Determines the virtual address mode of the External SRAM. (R/W)
APP_DRAM_SPLIT Determines the virtual address mode of the External SRAM. (R/W)
APP_SINGLE_IRAM_ENA Determines a special mode for APP_CPU access to the external flash.
(R/W)
DE
O
_M
UX
M
d)
E_
e
rv
CH
se
CA
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
CACHE_MUX_MODE The mode of the two caches sharing the memory. (R/W)
d)
e
e
U_
rv
rv
se
se
M
(re
(re
IM
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IMMU_PAGE_MODE Page size in the MMU for the internal SRAM 0. (R/W)
DE
O
ed _M
E
se AG
d)
)
P
U_
ve
rv
er
M
s
DM
(re
(re
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DMMU_PAGE_MODE Page size in the MMU for the internal SRAM 2. (R/W)
31 0
0x000000000 Reset
D_1
d)
_P
ve
AM
r
se
SR
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0x0FFFFFFFF Reset
1_
NT
RA
G
S S_
CE
)
ed
AC
rv
B_
se
AH
(re
31 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x1FF Reset
31 0
0x0F9C1E06F Reset
31 0
0x000000000 Reset
AB
AB
EN
EN
T_
T_
YP
YP
CR
CR
EN
DE
I_
I_
SP
SP
d)
)
ed
ed
E_
E_
e
rv
rv
rv
AV
AV
se
se
se
SL
SL
(re
(re
(re
31 13 12 11 9 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0x0FFFCE030 Reset
31 0
0x000000000 Reset
n
U_
P
_C
M
O
FR
R_
)
T
ed
IN
rv
U_
se
CP
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
_M
e
rv
_*
se
O
PR
(re
31 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 Reset
AP
)
M
ed
*_
rv
P_
se
AP
(re
31 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 Reset
IG
NF
CO
_
NT
RA
_G
SS
CE
AC
*_
E_
d )
ve
IT
BL
r
se
AH
(re
31 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
n
BLE
)
TA
ed
U_
rv
se
M
(re
IM
31 7 6 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 Reset
U_
rv
M
se
DM
(re
31 7 6 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 Reset
L
_SE
ER
AD
O
TL
O
O
_B
W
_S
d)
RE
ve
CU
r
se
SE
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EL
EL
E
_S
_S
_S
AN
AN
AN
CH
CH
CH
A_
A_
A_
DM
DM
M
_D
_
2_
d)
I3
I1
PI
e
SP
SP
rv
S
se
I_
I_
I_
SP
SP
SP
(re
31 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
6. DMA Controller
6.1 Overview
Direct Memory Access (DMA) is used for high-speed data transfer between peripherals and memory, as well as
from memory to memory. Data can be quickly moved with DMA without any CPU intervention, thus allowing for
more efficient use of the cores when processing data.
In the ESP32, 13 peripherals are capable of using DMA for data transfer, namely, UART0, UART1, UART2, SPI1,
SPI2, SPI3, I2S0, I2S1, SDIO slave, SD/MMC host, EMAC, BT, and Wi-Fi.
6.2 Features
The DMA controllers in the ESP32 feature:
Each DMA controller features different functions. However, the architecture of the DMA engine (DMA_ENGINE) is
the same in all DMA controllers.
The DMA Engine accesses SRAM over the AHB BUS. In Figure 12, the RAM represents the internal SRAM banks
available on ESP32. Further details on the SRAM addressing range can be found in Chapter System and
Memory. Software can use a DMA Engine by assigning a linked list to define the DMA operational
parameters.
The DMA Engine transmits the data from the RAM to a peripheral, according to the contents of the out_link
descriptor. Also, the DMA Engine stores the data received from a peripheral into a specified RAM location,
according to the contents of the in_link descriptor.
The DMA descriptor’s linked lists (out_link and in_link) have the same structure. As shown in Figure 13, a
linked-list descriptor consists of three words. The meaning of each field is as follows:
• owner (DW0) [31]: The allowed operator of the buffer corresponding to the current linked list.
1’b0: the allowed operator is the CPU;
1’b1: the allowed operator is the DMA controller.
• length (DW0) [23:12]: The number of valid bytes in the buffer corresponding to the current linked list. The
field value indicates the number of bytes to be transferred to/from the buffer denoted by word DW1.
• size (DW0) [11:0]: The size of the buffer corresponding to the current linked list.
NOTE: The size must be word-aligned.
• buffer address pointer (DW1): Buffer address pointer. This is the address of the data buffer.
NOTE: The buffer address must be word-aligned.
• next descriptor address (DW2): The address pointer of the next linked-list item. The value is 0, if the current
linked-list item is the last on the list (eof=1).
When receiving data, if the data transfer length is smaller than the specified buffer size, DMA will not use the
remaining space. This enables the DMA engine to be used for transferring an arbitrary number of data
bytes.
Figure 14 shows the data transfer in UDMA mode. Before the DMA Engine receives data, software must initialize
the receive-linked-list. UHCIx_INLINK_ADDR is used to point to the first in_link descriptor. The register must be
programmed with the lower 20 bits of the address of the initial linked-list item. After UHCIx_INLINK_START is set,
the Universal Host Controller Interface (UHCI) will transmit the data received by UART to the Decoder. After being
parsed, the data will be stored in the RAM as specified by the receive-linked-list descriptor.
Before DMA transmits data, software must initialize the transmit-linked-list and the data to be transferred.
UHCI_OUTLINK_ADDR is used to point to the first out_link descriptor. The register must be programmed with
the lower 20 bits of the address of the initial transmit-linked-list item. After UHCIx_OUTLINK_START is set, the
DMA Engine will read data from the RAM location specified by the linked-list descriptor and then transfer the data
through the Encoder. The DMA Engine will then shift the data out serially through the UART transmitter.
The UART DMA follows a format of (separator + data + separator). The Encoder is used for adding separators
before and after data, as well as using special-character sequences to replace data that are the same as
separators. The Decoder is used for removing separators before and after data, as well as replacing the
special-character sequences with separators. There can be multiple consecutive separators marking the
beginning or end of data. These separators can be configured through UHCIx_SEPER_CH, with the default
values being 0xC0. Data that are the same as separators can be replaced with UHCIx_ESC_SEQ0_CHAR0
(0xDB by default) and UHCIx_ESC_SEQ0_CHAR1 (0xDD by default). After the transmission process is complete,
a UHCIx_OUT_TOTAL_EOF_INT interrupt will be generated. After the reception procedure is complete, a
UHCIx_IN_SUC_EOF_INT interrupt will be generated.
ESP32 SPI modules can use DMA as well as the CPU for data exchange with peripherals. As can be seen from
Figure 15, two DMA channels are shared by SPI1, SPI2 and SPI3 controllers. Each DMA channel can be used by
any one SPI controller at any given time.
The ESP32 SPI DMA Engine also uses a linked list to receive/transmit data. Burst transmission is supported. The
minimum data length for a single transfer is one byte. Consecutive data transfer is also supported.
I2S_OUTLINK_START bit in I2S_OUT_LINK_REG and I2S_INLINK_START bit in I2S_IN_LINK_REG are used for
enabling the DMA Engine and are self-cleared by hardware. When I2S_OUTLINK_START is set to 1, the DMA
Engine starts processing the outbound linked-list descriptor and gets prepared to send data. When
I2S_INLINK_START is set to 1, the DMA Engine starts processing the inbound linked-list descriptor and gets
prepared to receive data.
4. In I2S master mode, set I2S_TX_START bit or I2S_RX_START bit to initiate an I2S operation;
In I2S slave mode, set I2S_TX_START bit or I2S_RX_START bit and wait for data transfer to be initiated by
the host device.
For more information on I2S DMA interrupts, please see Section DMA Interrupts, in Chapter I2S.
7. SPI
7.1 Overview
As Figure 16 shows, ESP32 integrates four SPI controllers which can be used to communicate with external
devices that use the SPI protocol. Controller SPI0 is used as a buffer for accessing external memory. Controller
SPI1 can be used as a master. Controllers SPI2 and SPI3 can be configured as either a master or a slave. When
used as a master, each SPI controller can drive multiple CS signals (CS0 ~ CS2) to activate multiple slaves.
Controllers SPI1 ~ SPI3 share two DMA channels.
The SPI signal buses consist of D, Q, CS0-CS2, CLK, WP, and HD signals, as Table 25 shows. Controllers SPI0
and SPI1 share one signal bus through an arbiter; the signals of the shared bus start with ”SPI”. Controllers SPI2
and SPI3 use signal buses starting with ”HSPI” and ”VSPI” respectively. The I/O lines included in the
above-mentioned signal buses can be mapped to pins via either the IO_MUX module or the GPIO matrix. (Please
refer to Chapter IO_MUX for details.)
The SPI controller supports four-line full-duplex/half-duplex communication (MOSI, MISO, CS, and CLK lines) and
three-line half-duplex-only communication (DATA, CS, and CLK lines) in GP-SPI mode. In QSPI mode, an SPI
controller accesses the flash or SRAM by using signal buses D, Q, CS0 ~ CS2, CLK, WP, and HD as a four-bit
parallel SPI bus. The mapping between SPI bus signals and pin function signals under different communication
modes is shown in Table 25.
Table 25: Mapping Between SPI Bus Signals and Pin Function Signals
• Programmable clock
Parallel QSPI
• SPI interrupts
7.3 GP-SPI
The SPI master mode supports four-line full-duplex/half-duplex communication and three-line half-duplex
communication. Figure 17 outlines the connections needed for four-line full-duplex/half-duplex
communications.
The SPI1 ~ SPI3 controllers can communicate with other slaves as a standard SPI master. SPI2 and SPI3 can
be configured as either a master or a slave. Every SPI master can be connected to three slaves at most by
default. When not using DMA, the maximum length of data received/sent in one burst is 64 bytes. The data
length is in multiples of one byte.
4. received and/or sent data: length of 0 ~ 512 bits (64 bytes); Master Out Slave In (MOSI) or Master In Slave
Out (MISO).
The address length is up to 32 bits in GP-SPI master mode and 64 bits in QSPI master mode. The command
phase, address phase, dummy phase and received/sent data phase are controlled by bits
SPI_USR_COMMAND, SPI_USR_ADDR, SPI_USR_DUMMY and SPI_USR_MISO/SPI_USR_MOSI respectively
in register SPI_USER_REG. A certain phase is enabled only when its corresponding control bit is set to 1. Details
can be found in register description. When SPI works as a master, the register can be configured by software as
required to determine whether or not to enable a certain phase.
When SPI works as a slave, the communication format must contain command, address, received and/or sent
data, among which the command has several options listed in Table 26. During data transmission or reception,
the CS signal should keep logic level low. If the CS signal is pulled up during transmission, the internal state of
the slave will be reset.
Command Description
0x1 Received by slave; writes data sent by the master into the slave status register via MOSI.
0x2 Received by slave; writes data sent by the master into the slave data buffer via MOSI.
0x3 Sent by slave; sends data in the slave buffer to master via MISO.
0x4 Sent by slave; sends data in the slave status register to master via MISO.
Writes master data on MOSI into data buffer and then sends the date in the slave data buffer
0x6
to MISO.
The master can write the slave status register SPI_SLV_WR_STATUS_REG, and decide whether to read data from
register SPI_SLV_WR_STATUS_REG or register SPI_RD_STATUS_REG via the SPI_SLV_STATUS_READBACK
bit in register SPI_SLAVE1_REG. The SPI master can maintain communication with the slave by reading and
writing slave status register, thus realizing complex communication with ease.
The length of received and sent data is controlled by SPI_MISO_DLEN_REG and SPI_MOSI_DLEN_REG in
master mode, as well as SPI_SLV_RDBUF_DLEN_REG and SPI_SLV_WRBUF_DLEN_REG in slave mode. A
reception or transmission of data is controlled by bit SPI_USR_MOSI or SPI_USR_MISO in SPI_USER_REG. The
SPI_USR bit in register SPI_CMD_REG needs to be configured to initialize a data transfer.
Note:
• In half-duplex communication, the order of command, address, received and/or sent data in the communication
format should be followed strictly.
• In half-duplex communication, communication formats ”command + address + received data + sent data” and
”received data + sent data” are not applicable to DMA.
• When ESP32 SPI acts as a slave, the master CS should be active at least one SPI clock period before a read/write
process is initiated, and should be inactive at least one SPI clock period after the read/write process is completed.
ESP32 SPI has 16 × 32 bits of data buffer to buffer data-send and data-receive operations. As is shown in Figure
18, received data is written from the low byte of SPI_W0_REG by default and the writing ends with
SPI_W15_REG. If the data length is over 64 bytes, the extra part will be written from SPI_W0_REG.
Data buffer blocks SPI_W0_REG ~ SPI_W7_REG and SPI_W8_REG ~ SPI_W15_REG data correspond to the
lower part and the higher part respectively. They can be used separately, and are controlled by the
SPI_USR_MOSI_HIGHPART bit and the SPI_USR_MISO_HIGHPART bit in register SPI_USER_REG. For
example, if SPI is configured as a master, when SPI_USR_MOSI_HIGHPART = 1,
SPI_W8_REG ~ SPI_W15_REG are used as buffer for sending data; when SPI_USR_MISO_HIGHPART = 1,
SPI_W8_REG ~ SPI_W15_REG are used as buffer for receiving data. If SPI acts as a slave, when
SPI_USR_MOSI_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for receiving data; when
SPI_USR_MISO_HIGHPART = 1, SPI_W8_REG ~ SPI_W15_REG are used as buffer for sending data.
fapb
fspi =
(SPI_CLKCNT_N+1)(SPI_CLKDIV_PRE+1)
SPI_CLKCNT_N and SPI_CLKDIV_PRE are two bits of register SPI_CLOCK_REG (Please refer to 7.7 Register
Description for details). SPI_CLKCNT_H = ⌊ SPI_CLKCNT_N+1
2 –1⌋, SPI_CLKCNT_N=SPI_CLKCNT_L. When the
SPI_CLK_EQU_SYSCLK bit in register SPI_CLOCK_REG is set to 1, and the other bits are set to 0, SPI output
clock frequency is fapb . For other clock frequencies, SPI_CLK_EQU_SYSCLK needs to be 0. In slave mode,
SPI_CLKCNT_N, SPI_CLKCNT_L, SPI_CLKCNT_H and SPI_CLKDIV_PRE should all be 0.
Table 27: Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Master
Table 28: Clock Polarity and Phase, and Corresponding SPI Register Values for SPI Slave
SPI_MOSI_DELAY_MODE 2 0 0 1 0 0
SPI_MOSI_DELAY_NUM 2 3 0 2 3 0
1. mode0 means CPOL=0, CPHA=0. When SPI is idle, the clock output is logic low; data changes on the
falling edge of the SPI clock and is sampled on the rising edge;
2. mode1 means CPOL=0, CPHA=1. When SPI is idle, the clock output is logic low; data changes on the
rising edge of the SPI clock and is sampled on the falling edge;
3. mode2 means when CPOL=1, CPHA=0. When SPI is idle, the clock output is logic high; data changes on
the rising edge of the SPI clock and is sampled on the falling edge;
4. mode3 means when CPOL=1, CPHA=1. When SPI is idle, the clock output is logic high; data changes on
the falling edge of the SPI clock and is sampled on the rising edge.
When GP-SPI is used as master and the data signals are not received by the SPI controller via GPIO matrix, if
GP-SPI output clock frequency is clkapb /2, register SPI_MISO_DELAY_MODE should be set to 0 when
configuring the clock polarity. If GP-SPI output clock frequency is not higher than clkapb /4, register
SPI_MISO_DELAY_MODE can be set to the corresponding value in Table 27 when configuring the clock
polarity.
When GP-SPI is used in master mode and the data signals enter the SPI controller via the GPIO matrix:
1. If GP-SPI output clock frequency is clkapb /2, register SPI_MISO_DELAY_MODE should be set to 0 and the
dummy phase should be enabled (SPI_USR_DUMMY = 1) for one clkspi clock cycle
(SPI_USR_DUMMY_CYCLELEN = 0) when configuring the clock polarity;
2. If GP-SPI output clock frequency is clkapb /4, register SPI_MISO_DELAY_MODE should be set to 0 when
configuring the clock polarity;
3. If GP-SPI output clock frequency is not higher than clkapb /8, register SPI_MISO_DELAY_MODE can be set
to the corresponding value in Table 27 when configuring the clock polarity.
When GP-SPI is used in slave mode, the clock signal and the data signals should be routed to the SPI controller
via the same path, i.e., neither the clock signal nor the data signals passes through GPIO matrix, or both of them
pass through GPIO matrix. This is important in ensuring that the signals are not delayed by different time periods
before they reach the SPI hardware.
Assume that tspi , tpre and tv in Figure 19 denote SPI clock period, how far ahead data output is, and data output
delay time, respectively. Assume the SPI slave’s main clock period is tapb . For non-DMA mode0, SPI slave data
output is delayed by tv :
• tv < 3.5 ∗ tapb , if CLK does not pass through GPIO matrix;
In DMA mode1 and mode3, SPI slave data output is delayed by the same period of time as in non-DMA mode.
However, for mode0 and mode2, SPI slave data is output earlier by tpre :
• tpre < (tspi /2 − 5.5 ∗ tapb ), if CLK does not pass through GPIO matrix;
• tpre < (tspi /2 − 7.5 ∗ tapb ), if CLK passes through GPIO matrix.
To conclude, if signals do not pass through GPIO matrix, the SPI slave clock frequency is up to fapb /8; if signals
pass through GPIO matrix, the SPI slave clock frequency is up to fapb /12. Note that (tspi /2–tpre ) represents data
output hold time for SPI slave in mode0 and mode2.
SPI1, SPI2 and SPI3 controllers can also be configured as QSPI master to connect to external memory. The
maximum output clock frequency of the SPI memory interface is fapb , with the same clock configuration as that
of the GP-SPI master.
ESP32 QSPI supports flash-read operation in one-line, two-line, and four-line modes. When working as a QSPI
master, the command phase, address phase, dummy phase and data phase can be configured as needed, as
flexible as in GP-SPI mode.
Note that GPI-SPI full-duplex mode does not support dummy phase.
ESP32 SPI reckons the completion of send- and/or receive-operations as the completion of one operation from
the controller and generates one interrupt. When ESP32 SPI is configured to slave mode, the slave will generate
read/write status registers and read/write buffer data interrupts according to different operations.
• SPI_OUT_DONE_INT: Triggered when the last linked list item has zero length.
• SPI_IN_DONE_INT: Triggered when the last received linked list had a length of 0.
7.8 Registers
d)
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ed
R
ve
US
rv
er
se
I_
s
SP
(re
(re
31 19 18 17 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_USR An SPI operation will be triggered when this bit is set. The bit will be cleared once the
operation is done. (R/W)
31 0
0x000000000 Reset
SPI_ADDR_REG It stores the transmitting address when master is in half-duplex mode or QSPI mode.
If the address length is bigger than 32 bits, SPI_SLV_WR_STATUS_REG contains the lower 32 bits.
The register in valid only when SPI_USR_ADDR is set to 1. (R/W)
(re FR D_ RD R
se EA Q ER
DE
I_ EA O E
_M L
SP FR IT_ RD
O
UA
RD UA
SP rve D_ IO
SP WP ) IO
I_ _B _O
Q
I_ d D
ST _D
D_
SP RD IT
FA D
I_ _B
EA
I_ EA
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ed
ed
ed
SP WR
FR
SP FR
rv
rv
rv
se
se
se
I_
I_
I_
SP
SP
(re
(re
(re
31 27 26 25 24 23 22 21 20 19 15 14 13 12 0
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_WR_BIT_ORDER This bit determines the bit order for command, address and data in transmitted
signal. 1: sends LSB first; 0: sends MSB first. (R/W)
SPI_RD_BIT_ORDER This bit determines the bit order for received data in received signal. 1: receives
LSB first; 0: receives MSB first. (R/W)
SPI_FREAD_QIO This bit is used to enable four-line address writes and data reads in QSPI mode.
(R/W)
SPI_FREAD_DIO This bit is used to enable two-line address writes and data reads in QSPI mode.
(R/W)
SPI_WP This bit determines the write-protection signal output when SPI is idle in QSPI mode. 1:
output high; 0: output low. (R/W)
SPI_FREAD_QUAD This bit is used to enable four-line data reads in QSPI mode. (R/W)
SPI_FREAD_DUAL This bit is used to enable two-line data reads in QSPI mode. (R/W)
SPI_FASTRD_MODE Reserved.
ed)
CS
rv
se
I_
SP
(re
31 28 27 0
0x05 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_CS_HOLD_DELAY Reserved.
T
EX
S_
S
U
TU
AT
TA
ST
S
I_
I_
SP
SP
31 24 23 16 15 0
SPI_STATUS_EXT Reserved.
SPI_STATUS Reserved.
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rv
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I_
I_
I_
se
SP
SP
SP
SP
SP
SP
SP
SP
SP
re
31 28 27 26 25 23 22 21 20 18 17 16 15 12 11 8 7 4 3 0
0x00 0x0 0x0 0x0 0x0 0x0 0x00 0x00 0x01 0x01 Reset
SPI_CS_DELAY_NUM Reserved.
SPI_CS_DELAY_MODE Reserved.
SPI_MOSI_DELAY_NUM It is used to configure the number of system clock cycles by which the
MOSI signals are delayed. (R/W)
SPI_MOSI_DELAY_MODE This register field determines the way the MOSI signals are delayed by
SPI clock. (R/W)
After being delayed by SPI_MOSI_DELAY_NUM system clocks, the MOSI signals will then be de-
layed by the configuration of SPI_MOSI_DELAY_MODE, specifically:
0: no delay.
1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MOSI signals are delayed by half a cycle,
otherwise they are delayed by one cycle.
2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MOSI signals are delayed by one cycle,
otherwise they are delayed by half a cycle.
3: the MOSI signals are delayed one cycle.
SPI_MISO_DELAY_NUM It is used to configure the number of system clock cycles by which the
MISO signals are delayed. (R/W)
SPI_MISO_DELAY_MODE This register field determines the way MISO signals are delayed by SPI
clock. (R/W)
After being delayed by SPI_MISO_DELAY_NUM system clock, the MISO signals will then be de-
layed by the configuration of SPI_MISO_DELAY_MODE, specifically:
0: no delay.
1: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MISO signals are delayed by half a cycle,
otherwise they are delayed by one cycle.
2: if SPI_CK_OUT_EDGE or SPI_CK_I_EDGE is set, the MISO signals are delayed by one cycle,
otherwise they are delayed by half a cycle.
3: the MISO signals are delayed by one cycle.
SPI_HOLD_TIME The number of SPI clock cycles by which CS pin signals are delayed. It is only valid
when SPI_CS_HOLD is set to 1. (R/W)
SPI_SETUP_TIME It is to configure the time between the CS signal active edge and the first SPI
clock edge. It is only valid in half-duplex mode or QSPI mode and when SPI_CS_SETUP is set to
1. (R/W)
LK
SC
SY
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NT
Q
IV
CN
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KC
KC
D
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LK
LK
CL
CL
CL
C
C
I_
I_
I_
I_
I_
SP
SP
SP
SP
SP
31 30 18 17 12 11 6 5 0
SPI_CLK_EQU_SYSCLK In master mode, when this bit is set to 1, SPI output clock is equal to system
clock; when set to 0, SPI output clock is divided from system clock. In slave mode, it should be
set to 0. (R/W)
SPI_CLKDIV_PRE In master mode, it is used to configure the pre-divider value for SPI output clock.
It is only valid when SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)
SPI_CLKCNT_N In master mode, it is used to configure the divider for SPI output clock. It is only
valid when SPI_CLK_EQU_SYSCLK is 0. In slave mode, it should be set to 0. (R/W)
HP T
T
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AR
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SP US _DU R D
DE
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R_ OS Y_
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SP US AD MA
SP US _MI MY
SP WR ITE UA
se BYT _O
SP FW TE IO
SP FW ITE IO
SP CS _ED ED
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RD Y U
CS E E
_H TUP
I_ R_ SO
SP US _DU I
I_ R_ M
I_ RI _Q
I_ R _Q
I_ R M
I_ R S
I_ R_ M
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SP US _CO
SP CK UT
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SP SIO
SP FW
DO
SP CK
SP US
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rv
rv
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se
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I_
I_
I_
SP
SP
SP
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(re
(re
31 30 29 28 27 26 25 24 23 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 1 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Reset
SPI_USR_COMMAND This bit enables the command phase of an SPI operation in SPI half-duplex
mode and QSPI mode. (R/W)
SPI_USR_ADDR This bit enables the address phase of an SPI operation in SPI half-duplex mode and
QSPI mode. (R/W)
SPI_USR_DUMMY This bit enables the dummy phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)
SPI_USR_MISO This bit enables the read-data phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)
SPI_USR_MOSI This bit enables the write-data phase of an SPI operation in SPI half-duplex mode
and QSPI mode. (R/W)
SPI_USR_DUMMY_IDLE The SPI clock signal is disabled in the dummy phase when the bit is set in
SPI half-duplex mode and QSPI mode. (R/W)
SPI_USR_MOSI_HIGHPART If set, MOSI data is stored in SPI_W8 ~ SPI_W15 of the SPI buffer.
(R/W)
SPI_USR_MISO_HIGHPART If set, MISO data is stored in SPI_W8 ~ SPI_W15 of the SPI buffer.
(R/W)
SPI_FWRITE_QIO Reserved.
SPI_FWRITE_DIO Reserved.
SPI_FWRITE_QUAD Reserved.
SPI_FWRITE_DUAL Reserved.
SPI_WR_BYTE_ORDER This bit determines the byte order of the command, address and data in
transmitted signal. 1: big-endian; 0: little-endian. (R/W)
SPI_RD_BYTE_ORDER This bit determines the byte order of received data in transmitted signal. 1:
big-endian; 0: little_endian. (R/W)
SPI_CK_OUT_EDGE This bit, combined with SPI_MOSI_DELAY_MODE, sets the MOSI signal delay
mode. It is only valid in master mode. (R/W)
SPI_CK_I_EDGE In slave mode, the bit is the same as SPI_CK_OUT_EDGE in master mode. It is
combined with SPI_MISO_DELAY_MODE. It is only valid in slave mode. (R/W)
SPI_CS_SETUP Setting this bit enables a delay between CS active edge and the first clock edge,
in multiples of one SPI clock cycle. In full-duplex mode and QSPI mode, setting this bit results in
(SPI_SETUP_TIME + 1.5) SPI clock cycles delay. In full-duplex mode, there will be 1.5 SPI clock
cycles delay for mode0 and mode2, and 1 SPI clock cycle delay for mode1 and mode3. (R/W)
SPI_CS_HOLD Setting this bit enables a delay between the end of a transmission and CS being
inactive, as specified in SPI_HOLD_TIME. (R/W)
EN
EL
CL
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LE
CY
IT
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ed
SR
US
rv
U
se
I_
I_
SP
SP
(re
31 26 25 8 7 0
23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 Reset
SPI_USR_ADDR_BITLEN It indicates the bit length of the transmitted address minus one in half-
duplex mode and QSPI mode, in multiples of one bit. It is only valid when SPI_USR_ADDR is set
to 1. (RO)
SPI_USR_DUMMY_CYCLELEN It indicates the number of SPI clock cycles for the dummy phase
minus one in SPI half-duplex mode and QSPI mode. It is only valid when SPI_USR_DUMMY is set
to 1. (R/W)
UE
E
TL
L
VA
BI
D_
D_
AN
AN
M
M
M
M
CO
O
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ed
R
US
US
rv
se
I_
I_
SP
SP
(re
31 28 27 16 15 0
7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_USR_COMMAND_BITLEN It indicates the bit length of the command phase minus one in SPI
half-duplex mode and QSPI mode. It is only valid when SPI_USR_COMMAND is set to 1. (R/W)
EN
TL
BI
_D
SI
O
M
R_
d)
ve
US
r
se
I_
SP
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0000000 Reset
SPI_USR_MOSI_DBITLEN It indicates the length of MOSI data minus one, in multiples of one bit. It
is only valid when SPI_USR_MOSI is set to 1 in master mode. (R/W)
SR
rv
_U
se
I
SP
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0000000 Reset
SPI_USR_MISO_DBITLEN It indicates the length of MISO data minus one, in multiples of one bit. It
is only valid when SPI_USR_MISO is set to 1 in master mode. (R/W)
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_SLV_WR_STATUS_REG In the slave mode this register is the status register for the master to
write the slave. In the master mode, if the address length is bigger than 32 bits, this register
contains the lower 32 bits. (R/W)
L
G E
EL
O
ED IV
E
_S
_P
E_ CT
CK
CS
DL A
_I EP_
R_
R_
SP CS DIS
0_ IS
S
se DIS
DI
TE
TE
CK E
CS D
I_ _K
I_ 2_
I_ 1_
SP CS )
SP ed)
AS
AS
I_ d
ed
ed
K_
SP rve
SP CS
rv
rv
rv
M
C
se
se
se
I_
I_
I_
I_
SP
SP
SP
(re
(re
(re
(re
31 30 29 28 14 13 11 10 9 8 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 Reset
SPI_CS_KEEP_ACTIVE This bit is only used in master mode where when it is set, the CS signal will
keep active. (R/W)
SPI_CK_IDLE_EDGE This bit is only used in master mode to configure the logicl level of SPI output
clock in idle state. (R/W)
1: the spi_clk line keeps high when idle;
0: the spi_clk line keeps low when idle.
SPI_MASTER_CK_SEL Reserved.
SPI_MASTER_CS_POL Reserved.
SPI_CK_DIS Reserved.
SPI_CS2_DIS This bit enables the SPI CS2 signal. 1: disables CS2; 0: enables CS2. (R/W)
SPI_CS1_DIS This bit enables the SPI CS1 signal. 1: disables CS1; 0: enables CS1. (R/W)
SPI_CS0_DIS This bit enables the SPI CS0 signal. 1: disables CS0; 0: enables CS0. (R/W)
D
DE TA_ N
FI EN
AN
I_ V_ D _I EN
_D NE
I_ V_ _ _IN EN
V_ R_ A_D NE
I_ V_ _ E N
NE
D_ _S _E
I_ AN _B _ N
_B F_ NE
SP SL WR ON NTE
SP TR RD BUF TE
NE
SP SL S_ UF INT
UF DO
CM RD UF
SP SL WR TA NT
T O
TE
O
RD BU O
M
I_ V_W _S _D
TA
V_ R_ _B
I_ V_ _S _I
O
I_ V_ _ N
I_ V_W _R E
I_ V_ M T
SP SL RD STA
SP SL RD STA
SP SL WR TE
_C
SP SL WR OD
_S
SP SL E_ E
DE
CN
I_ AV ES
I_ V_ IN
ST
ST
I_ _MO
SP SL C_R
S_
SP SL S_
LA
LA
AN
I_ AN
)
V_
V_
_I
ed
I_ N
CS
SP SY
TR
SP R
SL
SL
SL
SL
rv
T
se
I_
I_
I_
I_
I_
SP
SP
SP
SP
SP
SP
(re
31 30 29 28 27 26 23 22 20 19 17 16 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_SYNC_RESET When set, it resets the latched values of the SPI clock line, CS line and data line.
(R/W)
SPI_SLAVE_MODE This bit is used to set the mode of the SPI device. (R/W)
1: slave mode;
0: master mode.
SPI_SLV_WR_RD_BUF_EN This bit is only used in slave half-duplex mode, where when it is set, the
write and read data commands are enabled. (R/W)
SPI_SLV_WR_RD_STA_EN This bit is only used in slave half-duplex mode, where when it is set, the
write and read status commands are enabled. (R/W)
SPI_SLV_CMD_DEFINE Reserved.
SPI_TRANS_CNT The counter for operations in both the master mode and the slave mode. (RO)
SPI_SLV_LAST_STATE In slave mode, this contains the state of the SPI state machine. (RO)
SPI_SLV_LAST_COMMAND Reserved.
SPI_CS_I_MODE Reserved.
SPI_TRANS_INTEN The interrupt enable bit for the SPI_TRANS_DONE_INT interrupt. (R/W)
SPI_SLV_WR_STA_INTEN The interrupt enable bit for the SPI_SLV_WR_STA_INT interrupt. (R/W)
SPI_SLV_RD_STA_INTEN The interrupt enable bit for the SPI_SLV_RD_STA_INT interrupt. (R/W)
SPI_SLV_WR_BUF_INTEN The interrupt enable bit for the SPI_SLV_WR_BUF_INT interrupt. (R/W)
SPI_SLV_RD_BUF_INTEN The interrupt enable bit for the SPI_SLV_RD_BUF_INT interrupt. (R/W)
SPI_TRANS_DONE The raw interrupt status bit for the SPI_TRANS_DONE_INT interrupt. It is set by
hardware and cleared by software. (R/W)
SPI_SLV_WR_STA_DONE The raw interrupt status bit for the SPI_SLV_WR_STA_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)
SPI_SLV_RD_STA_DONE The raw interrupt status bit for the SPI_SLV_RD_STA_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)
SPI_SLV_WR_BUF_DONE The raw interrupt status bit for the SPI_SLV_WR_BUF_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)
SPI_SLV_RD_BUF_DONE The raw interrupt status bit for the SPI_SLV_RD_BUF_INT interrupt. It is
set by hardware and cleared by software, and only applicable to slave half-duplex mode. (R/W)
M N
K
BU _D MY EN
EN
DU M N
M Y_E
AC
F_ UM _E
EN
EA EN
RD UF UM Y_
Y_
LE
EN
DB
TL
V_ RB _D MM
_R T_
IT
TL
_B
US AS
_B
I_ V_W ST DU
BI
DR
AT _F
DR
S_
SP SL D A_
ST US
AD
D
A
U
I_ _R ST
_A
AT
V_ AT
R_
SP SL WR
RD
ST
SL T
_W
I_ V_S
)
V_
I_ _
ed
LV
LV
V
V
SL
SP SL
SP L
SL
rv
S
se
I_
I_
I_
I_
I_
SP
SP
SP
SP
SP
(re
31 27 26 25 24 16 15 10 9 4 3 2 1 0
SPI_SLV_STATUS_BITLEN It is only used in slave half-duplex mode to configure the length of the
master writing into the status register. (R/W)
SPI_SLV_STATUS_FAST_EN Reserved.
SPI_SLV_STATUS_READBACK Reserved.
SPI_SLV_RD_ADDR_BITLEN It indicates the address length in bits minus one for a slave-read oper-
ation. It is only valid in slave half-duplex mode. (R/W)
SPI_SLV_WR_ADDR_BITLEN It indicates the address length in bits minus one for a slave-write op-
eration. It is only valid in slave half-duplex mode. (R/W)
SPI_SLV_WRSTA_DUMMY_EN In slave mode, this bit enables the dummy phase for write-status
operations. It is only valid in slave half-duplex mode.(R/W)
SPI_SLV_RDSTA_DUMMY_EN In slave mode, this bit enables the dummy phase for read-status
operations. It is only valid in slave half-duplex mode. (R/W)
SPI_SLV_WRBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for write-buffer
operations. It is only valid in slave half-duplex mode. (R/W)
SPI_SLV_RDBUF_DUMMY_EN In slave mode, this bit enables the dummy phase for read-buffer
operations. It is only valid in slave half-duplex mode. (R/W)
EN
EN
N
E
LE
EL
EL
EL
E
CL
CL
CL
CL
CY
CY
CY
CY
Y_
Y_
Y_
Y_
M
M
M
M
UM
M
M
M
DU
DU
DU
_D
_
F_
A_
UF
TA
BU
ST
RB
RS
RD
RD
W
W
V_
V_
V_
LV
SL
SL
SL
S
I_
I_
I_
I_
SP
SP
SP
SP
31 24 23 16 15 8 7 0
SPI_SLV_WRBUF_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one for
the dummy phase for write-data operations. It is only valid when SPI_SLV_WRBUF_DUMMY_EN
is set to 1 in slave half-duplex mode. (R/W)
SPI_SLV_RDBUF_DUMMY_CYCLELEN It indicates the number of SPI clock cycles minus one for
the dummy phase for read-data operations. It is only valid when SPI_SLV_RDBUF_DUMMY_EN is
set to 1 in slave half-duplex mode. (R/W)
UE
UE
LU
L
L
L
VA
VA
VA
VA
D_
D_
D_
D_
M
CM
CM
CM
_C
_
F_
_
UF
TA
TA
BU
RB
RS
S
RD
RD
W
W
V_
V_
V_
V_
SL
SL
SL
SL
I_
I_
I_
I_
SP
SP
SP
SP
31 24 23 16 15 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_SLV_WRSTA_CMD_VALUE Reserved.
SPI_SLV_RDSTA_CMD_VALUE Reserved.
SPI_SLV_WRBUF_CMD_VALUE Reserved.
SPI_SLV_RDBUF_CMD_VALUE Reserved.
N
LE
IT
DB
U F_
RB
W
)
V_
ed
SL
rv
se
I_
SP
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0000000 Reset
SPI_SLV_WRBUF_DBITLEN It indicates the length of written data minus one, in multiples of one bit.
It is only valid in slave half-duplex mode. (R/W)
EN
TL
DBI
F_
BU
RD
d)
V_
ve
SL
r
se
I_
SP
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0000000 Reset
SPI_SLV_RDBUF_DBITLEN It indicates the length of read data minus one, in multiples of one bit. It
is only valid in slave half-duplex mode. (R/W)
_
d
LV
ve
_S
r
se
I
SP
(re
31 24 23 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_SLV_RDATA_BIT It indicates the bit length of data the master reads from the slave, minus one.
It is only valid in slave half-duplex mode. (R/W)
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_TX_CRC_REG Reserved.
d)
ve
ST
er
I_
s
SP
(re
31 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
O BU _E N
N
_E R_ ST _E
DE E
F_ R N
O _
UT C R T
M ST
O S U S
T
SP rve _RX STO E
I_ TD _B UR
P
I_ d _S P
TO
(re DM _TX TIN
SP OU R _B
IN R O
SP OU M_ T
I_ SC TA
I_ A ON
I_ B RS
I_ T_ FIF
SP IND _DA
SP DM _C
SP AH M_
T
d)
S P OU )
)
I_ A
ed
ed
I_ B
I_ T
SP DM
ve
SP AH
rv
rv
er
se
se
I_
I_
s
SP
SP
(re
(re
31 17 16 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Reset
SPI_DMA_CONTINUE This bit enables SPI DMA continuous data TX/RX mode. (R/W)
SPI_DMA_TX_STOP When in continuous TX/RX mode, setting this bit stops sending data. (R/W)
SPI_DMA_RX_STOP When in continuous TX/RX mode, setting this bit stops receiving data. (R/W)
SPI_OUT_DATA_BURST_EN SPI DMA reads data from memory in burst mode. (R/W)
SPI_AHBM_FIFO_RST This bit is used to reset SPI DMA AHB master FIFO pointer. (R/W)
SPI_OUT_RST The bit is used to reset DMA out-FSM and out-data FIFO pointer. (R/W)
SPI_IN_RST The bit is used to reset DMA in-DSM and in-data FIFO pointer. (R/W)
DR
P
TO
UT K S
D
O IN RE
_A
I_ TL K_
NK
SP OU IN
LI
I_ TL
SP OU )
)
I_ d
ed
UT
SP rve
rv
O
se
se
I_
SP
(re
(re
31 30 29 28 27 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset
E T
_S RT T
_R
NK TA R
LI _S TA
DR
TO
P
TO
IN K S
D
I_ IN RE
_A
_A
SP INL K_
NK
I_ IN
IN
SP INL )
)
I_ d
ed
LI
L
SP rve
IN
IN
rv
se
se
I_
I_
SP
SP
(re
(re
31 30 29 28 27 21 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset
SPI_INLINK_AUTO_RET when the bit is set, inlink descriptor jumps to the next descriptor when a
packet is invalid. (R/W)
N
RX N
_E
A_ X_E
DM T
I_ A_
d)
SP DM
e
rv
se
I_
SP
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EN A
T_ EN
Y_ IN A
A
PT R_ _EN
I N T_
A
EM RO T
I_ E _E IN A EN
R_ _ER _IN
SP IN_ UC E_ EN T_
SP OU K_ INT T_ NA
IN IN C N A
SC R OR
SP INL ON OF NT_ A
I_ TL DS _E EN
I_ S N T_ IN
I_ D _E _I N
I_ IN E_ _IN E
_D SC RR
LI K R_ A
SP IN_ DO IN F_
SP IN_ RR OF T_E
NK _D E
I_ T_ F_ EO
SP OU _EO AL_
I_ T T
SP OU _TO
)
ed
I_ T
SP OU
rv
se
I_
SP
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_OUT_EOF_INT_ENA The interrupt enable bit for the SPI_OUT_EOF_INT interrupt. (R/W)
SPI_OUT_DONE_INT_ENA The interrupt enable bit for the SPI_OUT_DONE_INT interrupt. (R/W)
SPI_IN_SUC_EOF_INT_ENA The interrupt enable bit for the SPI_IN_SUC_EOF_INT interrupt. (R/W)
SPI_IN_ERR_EOF_INT_ENA The interrupt enable bit for the SPI_IN_ERR_EOF_INT interrupt. (R/W)
SPI_IN_DONE_INT_ENA The interrupt enable bit for the SPI_IN_DONE_INT interrupt. (R/W)
RA W
T_ RA
Y_ IN W
W
PT R_ _RA
IN T_
W
EM RO T
I_ E _E IN W RA
R_ _ER _IN
SP OU K_ INT T_ AW
IN IN C A W
SP IN_ UC E_ RA T_
SC R OR
SP INL ON OF NT_ W
I_ TL DS _R RA
I_ S N T_ IN
I_ D _E _I A
I_ IN E_ _IN R
LI K R_ W
_D SC RR
SP IN_ RR OF T_R
SP IN_ DO IN F_
NK _D E
I_ T_ F_ EO
SP OU _EO AL_
I_ T T
SP OU _TO
d)
I_ T
ve
SP OU
r
se
I_
SP
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_OUT_TOTAL_EOF_INT_RAW The raw interrupt status bit for the SPI_OUT_TOTAL_EOF_INT in-
terrupt. (RO)
SPI_OUT_EOF_INT_RAW The raw interrupt status bit for the SPI_OUT_EOF_INT interrupt. (RO)
SPI_OUT_DONE_INT_RAW The raw interrupt status bit for the SPI_OUT_DONE_INT interrupt. (RO)
SPI_IN_SUC_EOF_INT_RAW The raw interrupt status bit for the SPI_IN_SUC_EOF_INT interrupt.
(RO)
SPI_IN_ERR_EOF_INT_RAW The raw interrupt status bit for the SPI_IN_ERR_EOF_INT interrupt.
(RO)
SPI_IN_DONE_INT_RAW The raw interrupt status bit for the SPI_IN_DONE_INT interrupt. (RO)
T_ ST
PT R_ _ST
ST
IN T_
Y_ IN
EM RO T
R_ _ER _IN
ST
SP IN_ UC E_ ST T_
SC R OR
I_ IN E_ _IN ST
I_ TL DS _S ST
I_ S N T_ IN
I_ D E I T
_D SC RR
SP IN_ RR OF T_S
SP IN_ DO IN F_
SP INL ON OF NT_
SP OU K_ INT T_
IN IN C T
NK _D E
I_ T_ F_ EO
LI K R_
I_ E _E IN
_
SP OU _EO AL_
I_ T T
_
SP OU _TO
)
ed
I_ T
SP OU
rv
se
I_
SP
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_OUT_EOF_INT_ST The masked interrupt status bit for the SPI_OUT_EOF_INT interrupt. (RO)
SPI_OUT_DONE_INT_ST The masked interrupt status bit for the SPI_OUT_DONE_INT interrupt.
(RO)
SPI_IN_SUC_EOF_INT_ST The masked interrupt status bit for the SPI_IN_SUC_EOF_INT interrupt.
(RO)
SPI_IN_ERR_EOF_INT_ST The masked interrupt status bit for the SPI_IN_ERR_EOF_INT interrupt.
(RO)
SPI_IN_DONE_INT_ST The masked interrupt status bit for the SPI_IN_DONE_INT interrupt. (RO)
CL R
T_ CL
Y_ IN R
R
PT R_ _CL
IN T_
R
EM RO T
I_ E _E IN R CL
R_ _ER _IN
SP IN_ C E_ L T_
SP OU K_ INT T_ LR
IN IN C L R
SC R OR
SP INL ON OF NT_ R
I_ TL DS _C CL
I_ SU N T_C IN
I_ IN E_ _IN C
I_ D _E _I L
_D SC RR
LI K R_ R
SP IN_ RR OF T_C
SP IN_ _DO _IN OF_
NK _D E
I_ T F E
SP OU _EO AL_
I_ T T
SP OU _TO
)
ed
I_ T
SP OU
rv
se
I_
SP
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_IN_SUC_EOF_DES_ADDR_REG The last inlink descriptor address when SPI DMA encountered
EOF. (RO)
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SPI_OUT_EOF_DES_ADDR_REG The last outlink descriptor address when SPI DMA encountered
EOF. (RO)
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DR
L
O P
IF EM
AD
)
_F _
S_
ed
TX FIFO
E
rv
_D
se
_
TX
TX
(re
31 30 29 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TX_DES_ADDRESS The LSB of the SPI DMA outlink descriptor address. (RO)
S
ES
UL Y
_F T
DR
L
O P
IF EM
AD
_F O_
d)
S_
ve
RX FIF
E
r
_D
se
_
RX
RX
(re
31 30 29 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RX_DES_ADDRESS The LSB of the SPI DMA inlink descriptor address. (RO)
8. SDIO Slave
8.1 Overview
The ESP32 features hardware support for the industry-standard Secure Digital (SD) device interface that
conforms to the SD Input/Output (SDIO) Specification Version 2.0. This allows a host controller to access the
ESP32 via an SDIO bus protocol, enabling high-speed data transfer.
The SDIO interface may be used to read ESP32 SDIO registers directly and access shared memory via Direct
Memory Access (DMA), thus reducing processing overhead while maintaining high performance.
8.2 Features
• Meets SDIO V2.0 specification
The Host System represents any SDIO specification V2.0-compatible host device. The Host System interacts
with the ESP32 (configured as the SDIO slave) via the standard SDIO bus implementation.
The SDIO Device Interface block enables effective communication with the external Host by directly providing
SDIO interface registers and enabling DMA operation for high-speed data transfer over the Advanced
High-performance Bus (AHB) without engaging the CPU.
ESP32 segregates data into packets sent to/from the Host. To achieve high bus utilization and data transfer
rates, we recommend the single block transmission mode. For detailed information on this mode, please refer to
the SDIO V2.0 protocol specification. When Host and Slave exchange data as blocks on the SDIO bus, the Slave
automatically pads data-when sending data out-and automatically strips padding data from the incoming data
block.
Whether the Slave pads or discards the data depends on the data address on the SDIO bus. When the data
address is equal to, or greater than, 0x1F800, the Slave will start padding or discarding data. Therefore, the
starting data address should be 0x1F800 - Packet_length, where Packet_length is measured in bytes. Data flow
on the SDIO bus is shown in Figure 23.
The standard IO_RW_EXTENDED (CMD53) command is used to initiate a packet transfer of an arbitrary length.
The content of the CMD53 command used in data transmission is as illustrated in Figure 24 below. For detailed
information on CMD53, please refer to the SDIO protocol specifications.
There are 54 bytes of field between SLCHOST_CONF_W0_REG and SLCHOST_CONF_W15_REG. Host and
Slave can access and change these fields, thus facilitating the information interaction between Host and
Slave.
8.3.4 DMA
The SDIO Slave module uses dedicated DMA to access data residing in the RAM. As shown in Figure 22, the
RAM is accessed over the AHB. DMA accesses RAM through a linked-list descriptor. Every linked list is
composed of three words, as shown in Figure 25.
• Owner: The allowed operator of the buffer that corresponds to the current linked list. 0: CPU is the allowed
operator; 1: DMA is the allowed operator.
• Eof: End-of-file marker, indicating that this linked-list element is the last element of the data packet.
• Length: The number of valid bytes in the buffer, i.e., the number of bytes that should be accessed from the
buffer for reading/writing.
• Buffer Address Pointer: The address of the data buffer as seen by the CPU (according to the RAM address
space).
• Next Descriptor Address: The address of the next linked-list element in the CPU RAM address space. If the
current linked list is the last one, the Eof bit should be 1, and the last descriptor address should be 0.
The transmission of packets from Slave to Host is initiated by the Slave. The Host will be notified with an interrupt
(for detailed information on interrupts, please refer to SDIO protocol). After the Host reads the relevant
information from the Slave, it will initiate an SDIO bus transaction accordingly. The whole procedure is illustrated
in Figure 27.
When the Host is interrupted, it reads relevant information from the Slave by visiting registers SLC0HOST_INT
and SLCHOST_PKT_LEN.
• SLCHOST_PKT_LEN: Packet length accumulator register. The current value minus the value of last time
equals the packet length sent this time.
In order to start DMA, the CPU needs to write the low 20 bits of the address of the first linked-list element to the
SLC0_RXLINK_ADDR bit of SLC0RX_LINK, then set the SLC0_RXLINK_START bit of SLC0RX_LINK. The DMA
will automatically complete the data transfer. Upon completion of the operation, DMA will interrupt the CPU so
that the buffer space can be freed or reused.
Transmission of packets from Host to Slave is initiated by the Host. The Slave receives data via DMA and stores it
in RAM. After transmission is completed, the CPU will be interrupted to process the data. The whole procedure is
demonstrated in Figure 28.
The Host obtains the number of available receiving buffers from the Slave by accessing register
SLC0HOST_TOKEN_RDATA. The Slave CPU should update this value after the receiving DMA linked list is
prepared.
The Host can figure out the available buffer space, using HOSTREG_SLC0_TOKEN1 minus the number of
buffers already used.
If the buffers are not enough, the Host needs to constantly poll the register until there are enough buffers
available.
To ensure sufficient receiving buffers, the Slave CPU must constantly load buffers on the receiving linked list. The
process is shown in Figure 29.
The CPU first needs to append new buffer segments at the end of the linked list that is being used by DMA and is
available for receiving data.
The CPU then needs to notify the DMA that the linked list has been modified. This can be done by setting bit
SLC0_TXLINK_RESTART of the SLC0TX_LINK register. Please note that when the CPU initiates DMA to receive
packets for the first time, SLC0_TXLINK_RESTART should be set to 1.
Lastly, the CPU refreshes any available buffer information by writing to the SLC0TOKEN1 register.
When the incoming data changes near the rising edge of the clock, the Slave will perform sampling on the falling
edge of the clock, or vice versa, as Figure 30 shows.
Sampling edges are configured via the FRC_POS_SAMP and FRC_NEG_SAMP bitfields in the SLCHOST_CONF
register. Each field is five bits wide, with bits corresponding to the CMD line and four DATA lines (0-3). Setting a
bit in FRC_POS_SAMP causes the corresponding line to be sampled for input at the rising clock edge, whereas
setting a bit in FRC_NEG_SAMP causes the corresponding line to be sampled for input at the falling clock
edge.
The Slave can also select the edge at which data output lines are driven to accommodate for any latency caused
by the physical signal path, as shown in Figure 31.
Driving edges are configured via the FRC_SDIO20 and FRC_SDIO11 bitfields in the SLCHOST_CONF register.
Each field is five bits wide, with bits corresponding to the CMD line and four DATA lines (0-3). Setting a bit in
FRC_SDIO20 causes the corresponding line to output at the rising clock edge, whereas setting a bit in
FRC_SDIO11 causes the corresponding line to output at the falling clock edge.
8.3.7 Interrupt
Host and Slave can interrupt each other via the interrupt vector. Both Host and Slave have eight interrupt
vectors. The interrupt is enabled by configuring the interrupt vector register (setting the enable bit to 1). The
interrupt vector registers can clear themselves automatically, which means one interrupt at a time and no other
configuration is required.
P_ S K
LR
O TE AC
_C
TE T
ST
LO P_ B
X_ O WR
TO
AU
_T LO _
SL ed) LC0 RX_ UTO
N_
X_ T
T
_T RS
RS
KE
S _ A
se F0_ LC0 RX_
C0 X_
TO
SL _R
0_
N S _
O 0_ C0
0_ C0
LC
CC NF SL
NF SL
_S
SL CO F0_
O 0_
0
NF
CC NF
d)
C N
ed
ve
SL CO
SL CO
rv
rv
CC
er
se
C
s
SL
SL
(re
(re
(re
31 15 14 13 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 Reset
SLCCONF0_SLC0_RX_LOOP_TEST Loop around when the slave buffer finishes sending packets.
When set to 1, hardware will not change the owner bit in the linked list. (R/W)
SLCCONF0_SLC0_TX_LOOP_TEST Loop around when the slave buffer finishes receiving packets.
When set to 1, hardware will not change the owner bit in the linked list. (R/W)
_R W
AW
AW W
NT A
C0 T_ C_ HO T_ 5_ T_R W
IN SL FR S BIT INT AW
C_ H T_ T3_ T_ W
HO T_ 2_ T_ W
ST BIT INT AW
IT NT AW
T_ W
W
_I _R
_R RA
SL FR OS BI IN RA
FR OS BIT IN RA
IN RA
RA
SL 0IN _SL _FR OS BIT _IN W
SL 0IN _SL _FR OS BIT T_ W
NE OF_ RAW
R
_ B 1_I _R
RR INT
NT T_
C T C H T_ 7 RA
C T C H T_ IN A
C T C H A IN W
X_ C IN W
C T C H T_ 6 T_
T_ C_ H T_ 4_ _
0_ _
C T C X AR T_ W
C T C X_ F T_
T
se _SL 0_T _DO _IN
DS R_
SL IN SL _T UD IN
E
C0 T_ C0 X_ F_
N
X_ C
T C X F
IN L R O
SL 0IN ) 0_T _DS
SL IN SL _R V O
E
C0 T_ C0 X_
C0 T_ C0 X_
C d C X
X
SL rve _SL 0_R
SL IN SL _R
SL IN L T
_
_
C0 _ 0
C0 T_ C0
se T C
C
(re 0IN _SL
SL IN SL
SL IN SL
S
S
C0 T_
C0 T_
)
C0 )
ed
ed
d
C T
e
SL 0IN
SL IN
rv
rv
er
se
C
s
SL
SL
(re
(re
(re
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SLC0INT_SLC0_RX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave sending descriptor error
(RO)
SLC0INT_SLC0_TX_DSCR_ERR_INT_RAW The raw interrupt bit for Slave receiving descriptor error.
(RO)
SLC0INT_SLC0_RX_EOF_INT_RAW The interrupt mark bit when Slave sending operation is finished.
(RO)
SLC0INT_SLC0_RX_DONE_INT_RAW The raw interrupt bit to mark single buffer as sent by Slave.
(RO)
SLC0INT_SLC0_TX_DONE_INT_RAW The raw interrupt bit to mark a single buffer as finished during
Slave receiving operation. (RO)
SLC0INT_SLC0_TX_OVF_INT_RAW The raw interrupt bit to mark Slave receiving buffer overflow.
(RO)
SLC0INT_SLC0_RX_UDF_INT_RAW The raw interrupt bit for Slave sending buffer underflow. (RO)
SLC0INT_SLC0_TX_START_INT_RAW The raw interrupt bit for registering Slave receiving initializa-
tion interrupt. (RO)
SLC0INT_SLC0_RX_START_INT_RAW The raw interrupt bit to mark Slave sending initialization in-
terrupt. (RO)
SLC0INT_SLC_FRHOST_BIT7_INT_RAW The interrupt mark bit 7 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT6_INT_RAW The interrupt mark bit 6 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT5_INT_RAW The interrupt mark bit 5 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT4_INT_RAW The interrupt mark bit 4 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT3_INT_RAW The interrupt mark bit 3 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT2_INT_RAW The interrupt mark bit 2 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT1_INT_RAW The interrupt mark bit 1 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT0_INT_RAW The interrupt mark bit 0 for Host to interrupt Slave. (RO)
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8. SDIO Slave
NT T
T
_I _S
_S
_S ST
S
_B 1_I _S
RR INT
NT T_
C T C H T_ 7 ST
C T C H T_ IN T
C T C H T_ 6 T_
T_ C_ H T_ 4_ _
C_ H T_ T3_ T_
HO T_ 2_ T_
0_ _
T_
NE OF_ ST
SL IN SL FR S T_ T_S
_I IN
_E R_
C T C X AR T_
_
C0 T_ C_ HO AR IN
C T C X_ F T_
X_ C IN
T
se _SL 0_T _DO _IN
DS R_
SL IN SL _T UD IN
C0 T_ C0 X_ F_
N
X_ C
T C X F
IN L R O
SL 0IN ) 0_T _DS
SL IN SL _R V O
E
C0 T_ C0 X_
C0 T_ C0 X_
C d C X
X
SL rve _SL 0_R
SL IN SL _R
SL IN L T
_
_
C0 _ 0
C0 T_ C0
se T C
C
(re 0IN _SL
SL IN SL
SL IN SL
S
S
C0 T_
C0 T_
)
d)
ed
C T
T
ve
SL 0IN
SL IN
rv
rv
er
C0
se
C
s
SL
(re
(re
(re
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SLC0INT_SLC0_RX_DSCR_ERR_INT_ST The interrupt status bit for Slave sending descriptor error.
(RO)
SLC0INT_SLC0_TX_DSCR_ERR_INT_ST The interrupt status bit for Slave receiving descriptor error.
(RO)
SLC0INT_SLC0_RX_EOF_INT_ST The interrupt status bit for finished Slave sending operation. (RO)
SLC0INT_SLC0_RX_DONE_INT_ST The interrupt status bit for finished Slave sending operation.
(RO)
SLC0INT_SLC0_TX_SUC_EOF_INT_ST The interrupt status bit for marking Slave receiving opera-
tion as finished. (RO)
SLC0INT_SLC0_TX_DONE_INT_ST The interrupt status bit for marking a single buffer as finished
during the receiving operation. (RO)
SLC0INT_SLC0_TX_OVF_INT_ST The interrupt status bit for Slave receiving overflow interrupt. (RO)
SLC0INT_SLC0_RX_UDF_INT_ST The interrupt status bit for Slave sending buffer underflow. (RO)
SLC0INT_SLC0_TX_START_INT_ST The interrupt status bit for Slave receiving interrupt initialization.
(RO)
SLC0INT_SLC0_RX_START_INT_ST The interrupt status bit for Slave sending interrupt initialization.
(RO)
SLC0INT_SLC_FRHOST_BIT7_INT_ST The interrupt status bit 7 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT6_INT_ST The interrupt status bit 6 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT5_INT_ST The interrupt status bit 5 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT4_INT_ST The interrupt status bit 4 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT3_INT_ST The interrupt status bit 3 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT2_INT_ST The interrupt status bit 2 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT1_INT_ST The interrupt status bit 1 for Host to interrupt Slave. (RO)
SLC0INT_SLC_FRHOST_BIT0_INT_ST The interrupt status bit 0 for Host to interrupt Slave. (RO)
_E A
NA
NT N
NA A
C0 T_ C_ HO T_ 5_ T_E A
IN SL FR S BIT INT NA
C_ H T_ T3_ T_ A
HO T_ 2_ T_ A
ST BIT INT NA
IT NT NA
T_ A
A
_I _E
_E EN
SL FR OS BI IN EN
FR OS BIT IN EN
IN EN
EN
SL 0IN _SL _FR OS BIT _IN A
SL 0IN _SL _FR OS BIT T_ A
NE OF_ ENA
E
_ B 1_I _E
RR INT
NT T_
C T C H T_ 7 EN
C T C H T_ IN N
C T C H T_ 6 T_
T_ C_ H T_ 4_ _
0_ _
C T C H A IN A
X_ C IN A
C T C X AR T_ A
C T C X_ F T_
T
se _SL 0_T _DO _IN
DS R_
SL IN SL _T UD IN
E
C0 T_ C0 X_ F_
N
X_ C
T C X F
IN L R O
SL 0IN ) 0_T _DS
SL IN SL _R V O
E
C0 T_ C0 X_
C0 T_ C0 X_
C d C X
X
SL rve _SL 0_R
SL IN SL _R
SL IN L T
_
_
C0 _ 0
C0 T_ C0
se T C
C
(re 0IN _SL
SL IN SL
SL IN SL
S
S
C0 T_
C0 T_
)
d)
C0 )
ed
d
C T
T
ve
e
SL 0IN
SL IN
rv
rv
er
se
C
s
SL
SL
(re
(re
(re
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SLC0INT_SLC0_RX_DSCR_ERR_INT_ENA The interrupt enable bit for Slave sending linked list de-
scriptor error. (R/W)
SLC0INT_SLC0_TX_DSCR_ERR_INT_ENA The interrupt enable bit for Slave receiving linked list de-
scriptor error. (R/W)
SLC0INT_SLC0_RX_EOF_INT_ENA The interrupt enable bit for Slave sending operation completion.
(R/W)
SLC0INT_SLC0_RX_DONE_INT_ENA The interrupt enable bit for single buffer’s sent interrupt, in
Slave sending mode. (R/W)
SLC0INT_SLC0_TX_SUC_EOF_INT_ENA The interrupt enable bit for Slave receiving operation com-
pletion. (R/W)
SLC0INT_SLC0_TX_DONE_INT_ENA The interrupt enable bit for single buffer’s full event, in Slave
receiving mode. (R/W)
SLC0INT_SLC0_TX_OVF_INT_ENA The interrupt enable bit for Slave receiving buffer overflow. (R/W)
SLC0INT_SLC0_RX_UDF_INT_ENA The interrupt enable bit for Slave sending buffer underflow.
(R/W)
SLC0INT_SLC0_TX_START_INT_ENA The interrupt enable bit for Slave receiving operation initial-
ization. (R/W)
SLC0INT_SLC0_RX_START_INT_ENA The interrupt enable bit for Slave sending operation initializa-
tion. (R/W)
SLC0INT_SLC_FRHOST_BIT7_INT_ENA The interrupt enable bit 7 for Host to interrupt Slave. (R/W)
SLC0INT_SLC_FRHOST_BIT6_INT_ENA The interrupt enable bit 6 for Host to interrupt Slave. (R/W)
SLC0INT_SLC_FRHOST_BIT5_INT_ENA The interrupt enable bit 5 for Host to interrupt Slave. (R/W)
SLC0INT_SLC_FRHOST_BIT4_INT_ENA The interrupt enable bit 4 for Host to interrupt Slave. (R/W)
SLC0INT_SLC_FRHOST_BIT3_INT_ENA The interrupt enable bit 3 for Host to interrupt Slave. (R/W)
SLC0INT_SLC_FRHOST_BIT2_INT_ENA The interrupt enable bit 2 for Host to interrupt Slave. (R/W)
SLC0INT_SLC_FRHOST_BIT1_INT_ENA The interrupt enable bit 1 for Host to interrupt Slave. (R/W)
SLC0INT_SLC_FRHOST_BIT0_INT_ENA The interrupt enable bit 0 for Host to interrupt Slave. (R/W)
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8. SDIO Slave
_C R
LR
NT L
LR R
C0 T_ C_ HO T_ 5_ T_C R
IN SL FR S BIT INT LR
C_ H T_ T3_ T_ R
HO T_ 2_ T_ R
ST BIT INT LR
IT NT LR
T_ R
R
_I _C
_C CL
SL FR OS BI IN CL
FR OS BIT IN CL
IN CL
CL
SL 0IN _SL _FR OS BIT _IN R
SL IN SL FR S BIT T_ R
C
_ B 1_I _C
NE OF_ CLR
RR INT
NT T_
C T C H T_ 7 CL
C0 T_ C_ HO T_ IN L
C T C H T_ 6 T_
T_ C_ H T_ 4_ _
0_ _
C T C H A IN R
X_ C IN R
C T C X AR T_ R
_T SU _ L
C T C X_ F T_
T
se _SL 0_T _DO _IN
DS R_
SL IN SL _T UD IN
E
C0 T_ C0 X_ F_
N
X_ C
T C X F
IN L R O
SL 0IN ) 0_T _DS
SL IN SL _R V O
E
C0 T_ C0 X_
C0 T_ C0 X_
C d C X
X
SL rve _SL 0_R
SL IN SL _R
SL IN L T
_
_
C0 _ 0
C0 T_ C0
se T C
C
(re 0IN _SL
SL IN SL
SL IN SL
S
S
C0 T_
C0 T_
d)
C0 )
ed
d
C T
T
ve
e
SL 0IN
SL IN
rv
rv
er
se
C
s
SL
SL
(re
(re
(re
31 27 26 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SLC0INT_SLC0_RX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave sending linked list descriptor
error. (WO)
SLC0INT_SLC0_TX_DSCR_ERR_INT_CLR Interrupt clear bit for Slave receiving linked list descriptor
error. (WO)
SLC0INT_SLC0_RX_EOF_INT_CLR Interrupt clear bit for Slave sending operation completion. (WO)
SLC0INT_SLC0_RX_DONE_INT_CLR Interrupt clear bit for single buffer’s sent interrupt, in Slave
sending mode. (WO)
SLC0INT_SLC0_TX_DONE_INT_CLR Interrupt clear bit for single buffer’s full event, in Slave receiving
mode. (WO)
SLC0INT_SLC0_TX_OVF_INT_CLR Set this bit to clear the Slave receiving overflow interrupt. (WO)
SLC0INT_SLC0_RX_UDF_INT_CLR Set this bit to clear the Slave sending underflow interrupt. (WO)
SLC0INT_SLC0_TX_START_INT_CLR Set this bit to clear the interrupt for Slave receiving operation
initialization. (WO)
SLC0INT_SLC0_RX_START_INT_CLR Set this bit to clear the interrupt for Slave sending operation
initialization. (WO)
R
P
DD
TO
RX NK ES
0_ LI _R
_A
LC RX NK
NK
_S 0_ XLI
LI
RX
RX LC _R
0_
C0 X_S C0
LC
SL 0R SL
_S
SL 0R )
)
C X_
C d
ed
RX
SL rve
rv
C0
se
se
SL
(re
(re
31 30 29 28 27 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset
SLC0RX_SLC0_RXLINK_RESTART Set this bit to restart and continue the linked list operation for
sending packets. (R/W)
SLC0RX_SLC0_RXLINK_START Set this bit to start the linked list operation for sending packets.
Sending will start from the address indicated by SLC0_RXLINK_ADDR. (R/W)
SLC0RX_SLC0_RXLINK_STOP Set this bit to stop the linked list operation. (R/W)
SLC0RX_SLC0_RXLINK_ADDR The lowest 20 bits in the initial address of Slave’s sending linked list.
(R/W)
_S RT T
NK TA R
LI _S TA
R
P
DD
TO
TX K ES
0_ LIN _R
_A
LC TX NK
NK
_S 0_ LI
LI
TX LC _TX
TX
0_
C0 _S 0
SL 0TX SLC
SLC
SL 0TX )
)
C _
X_
C d
ed
SL rve
T
rv
C0
se
se
SL
(re
(re
31 30 29 28 27 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset
SLC0TX_SLC0_TXLINK_RESTART Set this bit to restart and continue the linked list operation for
receiving packets. (R/W)
SLC0TX_SLC0_TXLINK_START Set this bit to start the linked list operation for receiving packets.
Receiving will start from the address indicated by SLC0_TXLINK_ADDR. (R/W)
SLC0TX_SLC0_TXLINK_STOP Set this bit to stop the linked list operation for receiving packets.
(R/W)
SLC0TX_SLC0_TXLINK_ADDR The lowest 20 bits in the initial address of Slave’s receiving linked
list. (R/W)
EC
TV
N
_I
ST
HO
O
_T
C0
SL
C_
VE
)
d)
ed
ed
NT
rv
rv
rv
se
se
se
CI
SL
(re
(re
(re
31 24 23 16 15 8 7 0
RE
O
TA
M
DA
C_
IN
W
_
_
N1
N1
N1
KE
KE
KE
TO
TO
TO
0_
0_
0_
LC
LC
LC
_S
_S
_S
N1
rv N1
N1
KE
KE
(re OK
)
C0 d)
)
ed
ed
TO
TO
SL rve
T
rv
C0
C0
se
se
se
SL
SL
(re
(re
31 28 27 16 15 14 13 12 11 0
LR
_A CH N
O N
EN IT _E
_C
UT _E
_L ST CH
C0 X_ TIT
SL _T S
1_ C0 X_
NF SL _R
O 1_ C0
CC NF SL
SL O 1_
CC NF
)
)
ed
ed
ve
SL CO
rv
rv
er
se
se
C
s
SL
(re
(re
(re
31 23 22 16 15 7 6 5 4
0x000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 Reset
E
AC
L
EP
_R
NO
N_
KE
TO
0_
LC
)
ed
S
rv
C_
se
SL
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TA
_M
DA
NC
W
_I
N_
EN
d)
d)
E
ed
_L
_L
ve
e
rv
rv
r
C0
C0
se
se
se
SL
SL
(re
(re
(re
31 29 28 23 22 21 20 19 0
SLC0_LEN_INC_MORE Set this bit to add the value of SLC0_LEN to that of SLC0_LEN_WDATA.
(WO)
_L
rv
C0
se
SL
(re
31 20 19 0
N1
KE
O
_T
C0
L
_S
G
d)
)
ed
RE
ve
rv
ST
er
se
s
HO
(re
(re
31 28 27 16 15 0
W
RA
C0 S LC TO ST IT5 T_ W
ST LC TO ST IT4 T_ W
LC TO ST IT3 T_ W
T W
ST IT1 T_ W
0_ T_R W
IN AW
W
T_
RA
IN
T_
T_
S LC TO S IT6 T
W
T_ W
N
KE
RA
_IN RA
S LC TO S IT7
AC
DF T_
TO S IT
IT
SL HO T_S 0_ HO _B
_P
_U _IN
W
C0 S LC TO ST
RX VF
E
SL 0HO T_S 0_ HO
_N
0_ _O
S LC TO
X
LC TX
_R
_S 0_
SL HO T_S 0_
0
LC
ST LC
C0 S LC
_S
HO _S
SL 0HO T_S
ST
T
C0 S
S
)
d)
)
ed
ed
ed
HO
SL 0HO
SL 0HO
ve
rv
rv
rv
r
C0
se
se
se
se
C
C
C
C
C
SL
SL
SL
(re
(re
(re
(re
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0
0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ST
T_
HO T_ C0 OH ST IT5 T_ T
ST SLC _TO OS _BI _IN ST
LC TO OS BI IN ST
TO OS BI IN ST
ST BIT INT T
IT NT T
IN ST
ST
IN
C0 OS SL _T O _B _IN _S
S
_B 1_I _S
_S 0_ H T_ T4_ T_
0_ H T_ T3_ T_
HO T_ T2_ T_
0_ _
T_
T_
T
_I _ST
C OS S _ O _B _
_S
NT
DF T
C OS S _ O _B
_P
_U _IN
W
SL 0H T_ LC0 TOH ST
RX VF
NE
C OS S _ O
0 _ _O
SL 0H T_ LC0 TOH
X_
LC TX
R
0_
_S 0_
C OS S _
SL 0H T_ LC0
LC
ST LC
_S
C OS S
HO T_
SL 0H T_
ST
C0 OS
C OS
)
SL ed)
)
ed
ed
ed
HO
SL H
SL 0H
rv
rv
rv
rv
C0
C0
se
se
se
se
C
SL
SL
(re
(re
(re
(re
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0
0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
K
H EC
N_C
N
LE
LE
0_
_
C0
LC
L
_S
_S
G
G
RE
RE
ST
ST
O
O
_H
_H
ST
ST
O
O
CH
CH
SL
SL
31 20 19 0
SLCHOST_HOSTREG_SLC0_LEN The accumulated value of the data length sent by the Slave. The
value gets updated only when the Host reads it.
0
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF3 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)
SLCHOST_CONF2 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)
SLCHOST_CONF1 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)
SLCHOST_CONF0 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)
4
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF7 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)
SLCHOST_CONF6 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)
SLCHOST_CONF5 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)
SLCHOST_CONF4 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)
10
8
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF11 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF10 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF9 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)
SLCHOST_CONF8 The information interaction register between Host and Slave. Both Host and Slave
can access it. (R/W)
15
4
1
NF
NF
O
O
_C
_C
ST
ST
O
O
CH
CH
SL
SL
31 24 23 16
SLCHOST_CONF15 The information interaction register between Host and Slave. Both Host and
Slave can be read from and written to this. (R/W)
SLCHOST_CONF14 The information interaction register between Host and Slave. Both Host and
Slave can be read from and written to this. (R/W)
18
NF
NF
O
O
_C
_C
ST
ST
O
O
CH
CH
SL
SL
31 24 23 16
SLCHOST_CONF19 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF18 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
27
26
24
2
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF27 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF26 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF25 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF24 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
29
NF
NF
O
O
_C
_C
ST
ST
)
)
ed
ed
O
O
rv
rv
CH
CH
se
se
SL
SL
(re
(re
31 24 23 16 15 8 7 0
SLCHOST_CONF31 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared
automatically. (WO)
SLCHOST_CONF29 The interrupt vector used by Host to interrupt Slave. This bit will not be cleared
automatically. (WO)
35
34
32
3
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF35 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF34 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF33 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF32 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
38
37
36
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF39 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF38 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF37 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF36 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
43
42
40
4
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF43 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF42 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF41 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF40 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
46
45
44
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF47 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF46 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF45 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF44 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
51
50
48
4
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF51 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF50 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF49 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF48 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
54
53
52
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF55 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF54 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF53 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF52 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
59
58
56
5
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF59 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF58 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF57 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF56 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
62
61
60
NF
NF
NF
NF
O
O
_C
_C
_C
_C
ST
ST
ST
ST
O
O
CH
CH
CH
CH
SL
SL
SL
SL
31 24 23 16 15 8 7 0
SLCHOST_CONF63 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF62 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF61 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
SLCHOST_CONF60 The information interaction register between Host and Slave. Both Host and
Slave can access it. (R/W)
R
CL
HO T_ C0 OH T_ T5_ T_C R
ST SLC _TO OS BIT INT LR
LC TO S IT INT LR
TO S IT INT LR
ST BIT INT LR
IT NT LR
T_ R
R
T_
C0 OS SL _T OS BI IN CL
IN L
CL
_S 0_ HO T_B 4_ _C
0_ HO T_B 3_ _C
HO T_ 2_ _C
_B 1_I _C
0_ _C
IN
SL 0H T_ C0 OH ST_ IT6_ T_
T_
R
T_ R
C OS SL _T O B IN
KE
CL
_IN CL
SL 0H T_ C0 OH ST_ IT7_
AC
DF T_
C OS SL _T O B
_P
_U _IN
SL H T_ C0 OH T_
W
RX VF
C0 OS SL _T OS
NE
0_ _O
SL 0H T_ C0 OH
X_
LC TX
_R
C OS SL _T
_S 0_
0
SL 0H T_ C0
LC
ST SLC
C OS SL
_S
HO T_
SL 0H T_
ST
C0 OS
C OS
)
)
ed
ed
ed
ed
O
0H
SL 0H
SL 0H
rv
rv
rv
rv
se
se
se
se
C
C
SL
SL
SL
(re
(re
(re
(re
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0
0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
A
EN
HO _F SL _TO S IT5 T_ A
T A
_S 0_T OS BIT NT A
0_ HO _BI _INT ENA
HO _B _IN ENA
I T 0 T_ A
T_ A
A
T_
C0 ST 1_ C0 HO _B _IN N
ST N1_ C0 HO T_B _IN EN
N1 C OH ST_ T4_I _EN
_B _IN N
_IN EN
EN
IN
ST IT1 T_E
_
_
T_
A
T_ A
C0 ST 1_ C0 HO _B _IN
KE
EN
_IN EN
3
TO ST T2
AC
DF T_
I
_B
_P
_U IN
RX F_
W
SL HO _FN SL _TO ST
T
NE
0 _ OV
C0 ST 1_ C0 HO
ST 1 C0 H
X_
LC X_
LC O
_R
_S 0_T
_F SL _T
0
ST 1 C0
LC
N1 C
_F SL
SL HO _FN SL
_S
ST N1_
C0 ST 1_
N1
SL 0HO _FN
_F
HO _F
ST
C0 OST
ST
d)
d)
d)
d)
HO
SL 0HO
rve
rve
rve
rve
H
C0
C0
se
se
se
se
C
C
C
SL
SL
SL
SL
(re
(re
(re
(re
31 26 25 24 23 22 18 17 16 15 8 7 6 5 4 3 2 1 0
0x00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
P
P
M
M
A
SA
20
11
_S
S_
IO
O
G
DI
O
SD
NE
_P
_S
_
_
RC
RC
RC
RC
_F
_F
_F
_F
ST
ST
ST
ST
d)
)
ed
ve
O
rv
CH
CH
CH
CH
er
se
s
SL
SL
SL
SL
(re
(re
31 28 27 20 19 15 14 10 9 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SLCHOST_FRC_POS_SAMP Set this bit to sample the corresponding signal at the rising clock edge.
(R/W)
SLCHOST_FRC_NEG_SAMP Set this bit to sample the corresponding signal at the falling clock edge.
(R/W)
SLCHOST_FRC_SDIO20 Set this bit to output the corresponding signal at the rising clock edge.
(R/W)
SLCHOST_FRC_SDIO11 Set this bit to output the corresponding signal at the falling clock edge.
(R/W)
Y1 LE
AD AB
RE N
O _E
_I D
O E
DI PE
_S HS
NF IG
d )
ve
HI F_H
r
se
N
(re
HI
31 3 2 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
9.1 Overview
The ESP32 memory card interface controller provides a hardware interface between the Advanced Peripheral
Bus (APB) and an external memory device. The memory card interface allows the ESP32 to be connected to
SDIO memory cards, MMC cards and devices with a CE-ATA interface. It supports two external cards (Card0
and Card1).
9.2 Features
This module has the following features:
The SD/MMC controller topology is shown in Figure 32. The controller supports two peripherals which cannot be
functional at the same time.
• Bus Interface Unit (BIU): It provides APB interfaces for registers, data read and write operation by FIFO and
DMA.
• Card Interface Unit (CIU): It handles external memory card interface protocols. It also provides clock control.
9.4.1.1 BIU
The BIU provides the access to registers and FIFO data through the Host Interface Unit (HIU). Additionally, it
provides FIFO access to independent data through a DMA interface. The host interface can be configured as an
APB interface. Figure 34 illustrates the internal components of the BIU. The BIU provides the following
functions:
• Host interface
• DMA interface
• Interrupt control
• Register access
• FIFO access
9.4.1.2 CIU
The CIU module implements the card-specific protocols. Within the CIU, the command path control unit and
data path control unit prompt the controller to interface with the command and data ports, respectively, of the
SD/MMC/CE-ATA cards. The CIU also provides clock control. Figure 34 illustrates the internal structure of the
CIU, which consists of the following primary functional blocks:
• Command path
• Data path
• Clock control
• Mux/demux unit
If the data_expected bit is set in the Command register, the new command is a data-transfer command and the
data path starts one of the following operations:
The data transmit state machine is illustrated in Figure 36. The module starts data transmission two clock cycles
after a response for the data-write command is received. This occurs even if the command path detects a
response error or a cyclic redundancy check (CRC) error in a response. If no response is received from the card
until the response timeout, no data are transmitted. Depending on the value of the transfer_mode bit in the
Command register, the data-transmit state machine adds data to the card’s data bus in a stream or in block(s).
The data transmit state machine is shown in Figure 36.
The data-receive state machine is illustrated in Figure 37. The module receives data two clock cycles after the
end bit of a data-read command, even if the command path detects a response error or a CRC error. If no
response is received from the card and a response timeout occurs, the BIU does not receive a signal about the
completion of the data transfer. If the command sent by the CIU is an illegal operation for the card, it would
prevent the card from starting a read-data transfer, and the BIU will not receive a signal about the completion of
the data transfer.
If no data are received by the data timeout, the data path signals a data timeout to the BIU, which marks an end
to the data transfer. Based on the value of the transfer_mode bit in the Command register, the data-receive state
machine gets data from the card’s data bus in a stream or block(s). The data receive state machine is shown in
Figure 37.
• During an open-ended card-write operation, if the card clock is stopped due to FIFO being empty, the
software must fill FIFO with data first, and then start the card clock. Only then can it issue a stop/abort
command to the card.
• During an SDIO/COMBO card transfer, if the card function is suspended and the software wants to resume
the suspended transfer, it must first reset FIFO, and then issue the resume command as if it were a new
data-transfer command.
• When issuing card reset commands (CMD0, CMD15 or CMD52_reset), while a card data transfer is in
progress, the software must set the stop_abort_cmd bit in the Command register, so that the CIU can stop
the data transfer after issuing the card reset command.
• When the data’s end bit error is set in the RINTSTS register, the CIU does not guarantee SDIO interrupts. In
such a case, the software ignores SDIO interrupts and issues a stop/abort command to the card, so that
the card stops sending read-data.
• If the card clock is stopped due to FIFO being full during a card read, the software will read at least two
FIFO locations to restart the card clock.
• Only one CE-ATA device at a time can be selected for a command or data transfer. For example, when
data are transferred from a CE-ATA device, a new command should not be sent to another CE-ATA device.
• If a CE-ATA device’s interrupts are enabled (nIEN=0), a new RW_BLK command should not be sent to the
same device if the execution of a RW_BLK command is already in progress (the RW_BLK command used
in this databook is the RW_MULTIPLE_BLOCK MMC command defined by the CE-ATA specifications).
Only the CCSD can be sent while waiting for the CCS.
• If, however, a CE-ATA device’s interrupts are disabled (nIEN=1), a new command can be issued to the
same device, allowing it to read status information.
• The send_auto_stop signal is not supported (software should not set the send_auto_stop bit) in CE-ATA
transfers.
After configuring the command start bit to 1, the values of the following registers cannot be changed before a
command has been issued:
• CMD - command
• TMOUT - timeout
If SDIO-sending is enabled, data can be written to the transferred RAM module by APB interface or DMA. Data
will be written from register EMAC_FIFO to the CPU, directly, by an APB interface.
When a subunit of the data path receives data, the subdata will be written onto the receive-RAM. Then, these
subdata can be read either with the APB or the DMA method at the reading end. Register EMAC_FIFO can be
read by the APB directly.
The DES2 element contains the address pointer to the data buffer.
Table 36: DES2
The DES3 element contains the address pointer to the next descriptor if the present descriptor is not the last one
in a chained descriptor structure.
9.9 Initialization
9.9.1 DMAC Initialization
The DMAC initialization should proceed as follows:
• Write to the DMAC Bus Mode Register (BMOD_REG) will set the Host bus’s access parameters.
• Write to the DMAC Interrupt Enable Register (IDINTEN) will mask any unnecessary interrupt causes.
• The software driver creates either the transmit or the receive descriptor list. Then, it writes to the DMAC
Descriptor List Base Address Register (DBADDR), providing the DMAC with the starting address of the list.
1. The Host sets up the elements (DES0-DES3) for transmission, and sets the OWN bit (DES0[31]). The Host
also prepares the data buffer.
2. The Host programs the write-data command in the CMD register in BIU.
3. The Host also programs the required transmit threshold (TX_WMARK field in FIFOTH register).
4. The DMAC engine fetches the descriptor and checks the OWN bit. If the OWN bit is not set, it means that
the host owns the descriptor. In this case, the DMAC enters a suspend-state and asserts the Descriptor
Unable interrupt in the IDSTS register. In such a case, the host needs to release the DMAC by writing any
value to PLDMND_REG.
5. It then waits for the Command Done (CD) bit and no errors from BIU, which indicates that a transfer can be
done.
6. Subsequently, the DMAC engine waits for a DMA interface request (dw_dma_req) from BIU. This request
will be generated, based on the programmed transmit-threshold value. For the last bytes of data which
cannot be accessed using a burst, single transfers are performed on the AHB Master Interface.
7. The DMAC fetches the transmit data from the data buffer in the Host memory and transfers them to FIFO
for transmission to card.
8. When data span across multiple descriptors, the DMAC fetches the next descriptor and extends its
operation using the following descriptor. The last descriptor bit indicates whether the data span multiple
descriptors or not.
9. When data transmission is complete, the status information is updated in the IDSTS register by setting the
Transmit Interrupt, if it has already been enabled. Also, the OWN bit is cleared by the DMAC by performing
a write transaction to DES0.
1. The Host sets up the element (DES0-DES3) for reception, and sets the OWN bit (DES0[31]).
2. The Host programs the read-data command in the CMD register in BIU.
3. Then, the Host programs the required level of the receive-threshold (RX_WMARK field in FIFOTH register).
4. The DMAC engine fetches the descriptor and checks the OWN bit. If the OWN bit is not set, it means that
the host owns the descriptor. In this case, the DMA enters a suspend-state and asserts the Descriptor
Unable interrupt in the IDSTS register. In such a case, the host needs to release the DMAC by writing any
value to PLDMND_REG.
5. It then waits for the Command Done (CD) bit and no errors from BIU, which indicates that a transfer can be
done.
6. The DMAC engine then waits for a DMA interface request (dw_dma_req) from BIU. This request will be
generated, based on the programmed receive-threshold value. For the last bytes of the data which cannot
be accessed using a burst, single transfers are performed on the AHB.
7. The DMAC fetches the data from FIFO and transfers them to the Host memory.
8. When data span across multiple descriptors, the DMAC will fetch the next descriptor and extend its
operation using the following descriptor. The last descriptor bit indicates whether the data span multiple
descriptors or not.
9. When data reception is complete, the status information is updated in the IDSTS register by setting
Receive-Interrupt, if it has already been enabled. Also, the OWN bit is cleared by the DMAC by performing
a write-transaction to DES0.
Please find detailed information on the clock phase selection register CLK_EDGE_SEL in Section
Registers.
9.11 Interrupt
Interrupts can be generated as a result of various events. The IDSTS register contains all the bits that might
cause an interrupt. The IDINTEN register contains an enable bit for each of the events that can cause an
interrupt.
There are two groups of summary interrupts, ”Normal” ones (bit8 NIS) and ”Abnormal” ones (bit9 AIS), as
outlined in the IDSTS register. Interrupts are cleared by writing 1 to the position of the corresponding bit. When all
the enabled interrupts within a group are cleared, the corresponding summary bit is also cleared. When both
summary bits are cleared, the interrupt signal dmac_intr_o is de-asserted (stops signalling).
Interrupts are not queued up, and if a new interrupt-event occurs before the driver has responded to it, no
additional interrupts are generated. For example, the Receive Interrupt IDSTS[1] indicates that one or more data
were transferred to the Host buffer.
An interrupt is generated only once for concurrent events. The driver must scan the IDSTS register for the
interrupt cause.
9.13 Registers
SD/MMC controller registers can be accessed by the APB bus of the CPU.
S
TU
TA
SD _S
CC PT
P_ RU
SE
SE RT SD STO ER
ET
se WA E TA
N
O CC _ T
ES
O
AB D_ TO E_IN
_R
ER
D
N AU IC
DM rve BLE
CO _R SET
RE _ EA
RO T
SE _ V
LL
NT ESE
ND DE
ND _R
)
d)
T_ d)
FI _R )
R
ed
ed
A d
se A
FO E
SE TA_
ve
(re N
rv
rv
E
r
se
se
se
A
CE
(re
(re
(re
31 25 24 23 12 11 10 9 8 7 6 5 4 3 2 1 0
SEND_CCSD When set, SD/MMC sends CCSD to the CE-ATA device. Software sets this bit only
if the current command is expecting CCS (that is, RW_BLK), and if interrupts are enabled for the
CE-ATA device. Once the CCSD pattern is sent to the device, SD/MMC automatically clears the
send_ccsd bit. It also sets the Command Done (CD) bit in the RINTSTS register, and generates
an interrupt for the host, in case the Command Done interrupt is not masked. NOTE: Once the
send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this,
within the boundary conditions the CCSD may be sent to the CE-ATA device, even if the device
has signalled CCS. (R/W)
SEND_IRQ_RESPONSE Bit automatically clears once response is sent. To wait for MMC card inter-
rupts, host issues CMD40 and waits for interrupt response from MMC card(s). In the meantime, if
host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC
command state-machine sends CMD40 response on bus and returns to idle state. (R/W)
DMA_RESET To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two
AHB clocks. (R/W)
FIFO_RESET To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of
reset operation. Note: FIFO pointers will be out of reset after 2 cycles of system clocks in addition
to synchronization delay (2 cycles of card clock), after the fifo_reset is cleared. (R/W)
CONTROLLER_RESET To reset controller, firmware should set this bit. This bit is auto-cleared after
two AHB and two cclk_in clock cycles. (R/W)
R2
R1
R0
DE
DE
DE
DE
VI
VI
VI
VI
DI
DI
DI
DI
K_
K_
K_
K_
CL
CL
CL
CL
31 24 23 16 15 8 7 0
CLK_DIVIDER3 Clock divider-3 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)
CLK_DIVIDER2 Clock divider-2 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)
CLK_DIVIDER1 Clock divider-1 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)
CLK_DIVIDER0 Clock divider-0 value. Clock division factor is 2*n, where n=0 bypasses the divider
(division factor of 1). For example, a value of 1 means divide by 2*1 = 2, a value of 0xFF means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, these bits are not implemented
because only one clock divider is supported. (R/W)
EG
_R
d)
RC
ve
KS
r
se
CL
(re
31 4 3 0
CLKSRC_REG Clock divider source for two SD cards is supported. Each card has two bits assigned
to it. For example, bit[1:0] are assigned for card 0, bit[3:2] are assigned for card 1. Card 0 maps
and internally routes clock divider[0:3] outputs to cclk_out[1:0] pins, depending on bit value.
00 : Clock divider 0;
01 : Clock divider 1;
10 : Clock divider 2;
11 : Clock divider 3.
In MMC-Ver3.3-only controller, only one clock divider is supported. The cclk_out is always from
clock divider 0, and this register is not implemented. (R/W)
L
BE
NA
d)
_E
ve
LK
r
se
CC
(re
31 2 1 0
CCLK_ENABEL Clock-enable control for two SD card clocks and one MMC card clock is supported.
0: Clock disabled;
1: Clock enabled.
In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0] is used. (R/W)
UT
EO
IM
UT
_T
EO
E
NS
M
TI
O
_
SP
TA
DA
RE
31 8 7 0
DATA_TIMEOUT Value for card data read timeout. This value is also used for data starvation by host
timeout. The timeout counter is started only after the card clock is stopped. This value is specified
in number of card output clocks, i.e. cclk_out of the selected card.
NOTE: The software timer should be used if the timeout value is in the order of 100 ms. In this
case, read data timeout interrupt needs to be disabled. (R/W)
RESPONSE_TIMEOUT Response timeout value. Value is specified in terms of number of card output
clocks, i.e., cclk_out. (R/W)
4
TH
TH
ID
ID
)
)
_W
_W
ed
ed
rv
rv
RD
RD
se
se
CA
CA
(re
(re
31 18 17 16 15 2 1 0
CARD_WIDTH4 One bit per card indicates if card is 1-bit or 4-bit mode.
0: 1-bit mode;
1: 4-bit mode.
Bit[1:0] correspond to card[1:0] respectively. Only NUM_CARDS*2 number of bits are imple-
mented. (R/W)
CK
rv
se
O
BL
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00200 Reset
31 0
0x000000200 Reset
BYTCNT_REG Number of bytes to be transferred, should be an integral multiple of Block Size for
block transfers. For data transfers of undefined byte lengths, byte count should be set to 0. When
byte count is set to 0, it is the responsibility of host to explicitly send stop/abort command to
terminate data transfer. (R/W)
K
AS
_M
K
NT
d)
AS
ve
_I
_M
r
IO
se
T
SD
(re
IN
31 18 17 16 15 0
SDIO_INT_MASK SDIO interrupt mask, one bit for each card. Bit[17:16] correspond to card[15:0] re-
spectively. When masked, SDIO interrupt detection for that card is disabled. 0 masks an interrupt,
and 1 enables an interrupt. In MMC-Ver3.3-only mode, these bits are always 0. (R/W)
INT_MASK These bits used to mask unwanted interrupts. A value of 0 masks interrupt, and a value
of 1 enables the interrupt. (R/W)
Bit 15 (EBE): End-bit error, read/write (no CRC)
Bit 14 (ACD): Auto command done
Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt
Bit 12 (HLE): Hardware locked write error
Bit 11 (FRUN): FIFO underrun/overrun error
Bit 10 (HTO): Data starvation-by-host timeout/Volt_switch_int
Bit 9 (DRTO): Data read timeout
Bit 8 (RTO): Response timeout
Bit 7 (DCRC): Data CRC error
Bit 6 (RCRC): Response CRC error
Bit 5 (RXDR): Receive FIFO data request
Bit 4 (TXDR): Transmit FIFO data request
Bit 3 (DTO): Data transfer over
Bit 2 (CD): Command done
Bit 1 (RE): Response error
Bit 0 (CD): Card detect
31 0
0x000000000 Reset
Y
NL
_O
RS
TE
TE
EX T RC
T R M P LE
IS
DA D/W R_ STO MP
E_ NG _C
EG
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TR D_ VD _CM N
PE H
CK IC
CT
N R T IO
A AU AT D
NS LE SE
A FE _ O
LO EV
E
RE NS TO A_C
SE T_P OR IZAT
O E_ N
RE PO ES ED
CH A_E ITE OD
TE ATA D
R
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SP NS PO
DA CE TE
BE
S _R T
AI AB L
RE CK PEC
US rve MD
W P_ ITIA
UP _ EC
X
UM
(re rve E
DE
se OL
AD XP
(re _H )
(re rve )
(re rve )
se d)
CC rve )
RE _E )
se C
O N
E X
E d
se d
se d
se d
S d
_N
IN
(re RT_
(re rve
I
ST _
D_
RD
ND
A
CM
CA
SE
ST
31 30 29 28 27 26 25 24 23 22 21 20 16 15 14 13 12 11 10 9 8 7 6 5 0
START_CMD Start command. Once command is served by the CIU, this bit is automatically cleared.
When this bit is set, host should not attempt to write to any command registers. If a write is
attempted, hardware lock error is set in raw interrupt register. Once command is sent and a
response is received from SD_MMC_CEATA cards, Command Done bit is set in the raw interrupt
Register. (R/W)
USE_HOLE Use Hold Register. (R/W) 0: CMD and DATA sent to card bypassing HOLD Register; 1:
CMD and DATA sent to card through the HOLD Register.
UPDATE_CLOCK_REGISTERS_ONLY (R/W)
0: Normal command sequence.
1: Do not send commands, just update clock register value into card clock domain
Following register values are transferred into card clock domain: CLKDIV, CLRSRC, and CLKENA.
Changes card clocks (change frequency, truncate off or on, and set low-frequency mode). This
is provided in order to change clock frequency or stop clock without having to send command to
cards.
During normal command sequence, when update_clock_registers_only = 0, following control reg-
isters are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, and BYTCNT.
CIU uses new register values for new command sequence to card(s). When bit is set, there are no
Command Done interrupts because no command is sent to SD_MMC_CEATA cards.
CARD_NUMBER Card number in use. Represents physical slot number of card being accessed. In
MMC-Ver3.3-only mode, up to two cards are supported. In SD-only mode, up to two cards are
supported. (R/W)
SEND_INITIALIZATION (R/W)
0: Do not send initialization sequence (80 clocks of 1) before sending this command.
1: Send initialization sequence before sending this command.
After power on, 80 clocks must be sent to card for initialization before sending any commands to
card. Bit should be set while sending first command to card so that controller will initialize clocks
before sending command to card.
STOP_ABORT_CMD (R/W)
0: Neither stop nor abort command can stop current data transfer. If abort is sent to function-
number currently selected or not in data-transfer mode, then bit should be set to 0.
1: Stop or abort command intended to stop current data transfer in progress. When open-ended
or predefined data transfer is in progress, and host issues stop or abort command to stop data
transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle
state.
WAIT_PRVDATA_COMPLETE (R/W)
0: Send command at once, even if previous data transfer has not completed;
1: Wait for previous data transfer to complete before sending Command.
The wait_prvdata_complete = 0 option is typically used to query status of card during data transfer
or to stop current data transfer. card_number should be same as in previous command.
SEND_AUTO_STOP (R/W)
0: No stop command is sent at the end of data transfer;
1: Send stop command at the end of data transfer.
TRANSFER_MODE (R/W)
0: Block data transfer command;
1: Stream data transfer command. Don’t care if no data expected.
READ/WRITE (R/W)
0: Read from card;
1: Write to card.
Don’t care if no data is expected from card.
DATA_EXPECTED (R/W)
0: No data transfer expected.
1: Data transfer expected.
CHECK_RESPONSE_CRC (R/W)
0: Do not check;
1: Check response CRC.
Some of command responses do not return valid CRC bits. Software should disable CRC checks
for those commands in order to disable CRC checking by controller.
RESPONSE_LENGTH (R/W)
0: Short response expected from card;
1: Long response expected from card.
RESPONSE_EXPECT (R/W)
0: No response expected from card;
1: Response expected from card.
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
SK
PT
RU
M
S_
ER
TU
NT
d)
TA
ve
_I
_S
r
IO
se
T
SD
(re
IN
31 18 17 16 15 0
SDIO_INTERRUPT_MSK Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond
to card1 and card0, respectively. SDIO interrupt for card is enabled only if corresponding
sdio_int_mask bit is set in Interrupt mask register (Setting mask bit enables interrupt). (RO)
INT_STATUS_MSK Interrupt enabled only if corresponding bit in interrupt mask register is set. (RO)
Bit 15 (EBE): End-bit error, read/write (no CRC)
Bit 14 (ACD): Auto command done
Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt
Bit 12 (HLE): Hardware locked write error
Bit 11 (FRUN): FIFO underrun/overrun error
Bit 10 (HTO): Data starvation by host timeout (HTO)
Bit 9 (DTRO): Data read timeout
Bit 8 (RTO): Response timeout
Bit 7 (DCRC): Data CRC error
Bit 6 (RCRC): Response CRC error
Bit 5 (RXDR): Receive FIFO data request
Bit 4 (TXDR): Transmit FIFO data request
Bit 3 (DTO): Data transfer over
Bit 2 (CD): Command done
Bit 1 (RE): Response error
Bit 0 (CD): Card detect
AW
_R
W
PT
RA
RU
S_
ER
U
NT
d)
AT
ve
ST
_I
er
IO
T_
s
SD
(re
IN
31 18 17 16 15 0
SDIO_INTERRUPT_RAW Interrupt from SDIO card, one bit for each card. Bit[17:16] correspond to
card1 and card0, respectively. Setting a bit clears the corresponding interrupt bit and writing 0 has
no effect. (R/W)
0: No SDIO interrupt from card;
1: SDIO interrupt from card.
In MMC-Ver3.3-only mode, these bits are always 0. Bits are logged regardless of interrupt-mask
status. (R/W)
INT_STATUS_RAW Setting a bit clears the corresponding interrupt and writing 0 has no effect. Bits
are logged regardless of interrupt mask status. (R/W)
Bit 15 (EBE): End-bit error, read/write (no CRC)
Bit 14 (ACD): Auto command done
Bit 13 (SBE/BCI): Start Bit Error/Busy Clear Interrupt
Bit 12 (HLE): Hardware locked write error
Bit 11 (FRUN): FIFO underrun/overrun error
Bit 10 (HTO): Data starvation by host timeout (HTO)
Bit 9 (DTRO): Data read timeout
Bit 8 (RTO): Response timeout
Bit 7 (DCRC): Data CRC error
Bit 6 (RCRC): Response CRC error
Bit 5 (RXDR): Receive FIFO data request
Bit 4 (TXDR): Transmit FIFO data request
Bit 3 (DTO): Data transfer over
Bit 2 (CD): Command done
Bit 1 (RE): Response error
Bit 0 (CD): Card detect
S
TE
Y
K
US
M K
TA
AR
ER AR
_B
_S
X
AT M
DE
_3 Y C
M
US
W R
TA US _M
FS
X_ ATE
IN
T
T
FI _T PTY
DA A_B ATE
E_
TA
D_
UN
_R W
FI _E L
NS
_S
AN
FO UL
se d)
FO X_
T T
ed
FO M
DA A_S
(re rve
O
_C
FI _F
rv
SP
M
se
FO
FO
T
CO
DA
RE
(re
FI
FI
31 30 29 17 16 11 10 9 8 7 4 3 2 1 0
RESPONSE_INDEX Index of previous response, including any auto-stop sent by core. (RO)
FIFO_TX_WATERMARK FIFO reached Transmit watermark level, not qualified with data transfer. (RO)
FIFO_RX_WATERMARK FIFO reached Receive watermark level, not qualified with data transfer. (RO)
ZE
SI
N_
IO
ACT
ANS
TR
E_
PL
K
TI
K
AR
UL
AR
d)
)
ed
ed
M
M
ve
M
rv
rv
A_
_W
_W
er
se
se
s
DM
RX
TX
(re
(re
(re
31 30 28 27 26 16 15 12 11 0
RX_WMARK FIFO threshold watermark level when receiving data to card.When FIFO data count
reaches greater than this number (FIFO_RX_WATERMARK), DMA/FIFO request is raised. During
end of packet, request is generated regardless of threshold programming in order to complete any
remaining data.In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then
interrupt is generated instead of DMA request.During end of packet, interrupt is not generated if
threshold programming is larger than any remaining data. It is responsibility of host to read remain-
ing bytes on seeing Data Transfer Done interrupt.In DMA mode, at end of packet, even if remaining
bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes
before Data Transfer Done interrupt is set. (R/W)
TX_WMARK FIFO threshold watermark level when transmitting data to card. When FIFO data count
is less than or equal to this number (FIFO_TX_WATERMARK), DMA/FIFO request is raised. If In-
terrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated,
regardless of threshold programming.In non-DMA mode, when transmit FIFO threshold (TXDR) in-
terrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on
last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO
is full or after CIU completes data transfers, because FIFO may not be empty). In DMA mode, at
end of packet, if last transfer is less than burst size, DMA controller does single cycles until required
bytes are transferred. (R/W)
N
T_
EC
ET
d)
_D
ve
RD
r
se
CA
(re
31 2 1 0
CARD_DETECT_N Value on card_detect_n input ports (1 bit per card), read-only bits.0 represents
presence of card. Only NUM_CARDS number of bits are implemented. (RO)
CT
TE
OR
d)
_P
ve
TE
r
se
RI
(re
W
31 2 1 0
WRITE_PROTECT Value on card_write_prt input ports (1 bit per card).1 represents write protection.
Only NUM_CARDS number of bits are implemented. (RO)
31 0
0x000000000 Reset
31 0
0x000000000 Reset
TBBCNT_REG Number of bytes transferred between Host/DMA memory and BIU FIFO. (RO)
T
UN
CO
_
CE
)
UN
ed
rv
BO
se
DE
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0000000 Reset
DEBOUNCE_COUNT Number of host clocks (clk) used by debounce filter logic. The typical de-
bounce time is 5 ~ 25 ms to prevent the card instability when the card is inserted or removed.
(R/W)
31 0
0x000000000 Reset
USRID_REG User identification register, value set by user. Default reset value can be picked by user
while configuring core before synthesis. Can also be used as a scratchpad register by user. (R/W)
ET
ES
_R
RD
d)
CA
ver
T_
se
RS
(re
31 2 1 0
0 0x1 Reset
RST_CARD_RESET Hardware reset.1: Active mode; 0: Reset. These bits cause the cards to enter
pre-idle state, which requires them to be re-initialized. CARD_RESET[0] should be set to 1’b0 to
reset card0, CARD_RESET[1] should be set to 1’b0 to reset card1.The number of bits implemented
is restricted to NUM_CARDS. (R/W)
R
BL
SW
DE
O FB
)
)
P
ed
ed
D_
D_
BM D_
D_
rv
rv
O
O
se
se
BM
BM
BM
(re
(re
31 11 10 8 7 6 2 1 0
BMOD_PBL Programmable Burst Length. These bits indicate the maximum number of beats to be
performed in one IDMAC transaction. The IDMAC will always attempt to burst as specified in PBL
each time it starts a burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64,
128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value,
write the required value to FIFOTH register. This is an encode value as follows:
000: 1-byte transfer; 001: 4-byte transfer; 010: 8-byte transfer; 011: 16-byte transfer; 100: 32-
byte transfer; 101: 64-byte transfer; 110: 128-byte transfer; 111: 256-byte transfer.
PBL is a read-only value and is applicable only for data access, it does not apply to descriptor
access. (R/W)
BMOD_FB Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or
not. When set, the AHB will use only SINGLE, INCR4, INCR8 or INCR16 during start of normal
burst transfers. When reset, the AHB will use SINGLE and INCR burst transfer operations. (R/W)
BMOD_SWR Software Reset. When set, the DMA Controller resets all its internal registers. It is
automatically cleared after one clock cycle. (R/W)
31 0
0x000000000 Reset
PLDMND_REG Poll Demand. If the OWN bit of a descriptor is not set, the FSM goes to the Suspend
state. The host needs to write any value into this register for the IDMAC FSM to resume normal
descriptor fetch operation. This is a write only register, PD bit is write-only. (WO)
31 0
0x000000000 Reset
DBADDR_REG Start of Descriptor List. Contains the base address of the First Descriptor. The LSB
bits [1:0] are ignored and taken as all-zero by the IDMAC internally. Hence these LSB bits may be
treated as read-only. (R/W)
DE
CO
E_
SM
(re S_ ES
ID S_ E
(re NIS
S_ S
ID rve U
FB
ST FB
d)
ID ed)
ID S_ )
ST RI
ST AI
TI
ST d
ST C
se D
_F
ve
S_
ID _
ID S_
S_
rv
TS
S
er
se
ST
ST
ST
s
S
(re
ID
ID
ID
31 17 16 13 12 10 9 8 7 6 5 4 3 2 1 0
IDSTS_FBE_CODE Fatal Bus Error Code. Indicates the type of error that caused a Bus Error. Valid
only when the Fatal Bus Error bit IDSTS[2] is set. This field does not generate an interrupt. (RO)
3b001: Host Abort received during transmission;
3b010: Host Abort received during reception;
Others: Reserved.
IDSTS_AIS Abnormal Interrupt Summary. Logical OR of the following: IDSTS[2] : Fatal Bus Interrupt,
IDSTS[4] : DU bit Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be
cleared each time a corresponding bit that causes AIS to be set is cleared. Writing 1 clears this
bit. (R/W)
IDSTS_NIS Normal Interrupt Summary. Logical OR of the following: IDSTS[0] : Transmit Interrupt,
IDSTS[1] : Receive Interrupt. Only unmasked bits affect this bit. This is a sticky bit and must be
cleared each time a corresponding bit that causes NIS to be set is cleared. Writing 1 clears this
bit. (R/W)
IDSTS_CES Card Error Summary. Indicates the status of the transaction to/from the card, also
present in RINTSTS. Indicates the logical OR of the following bits: EBE : End Bit Error, RTO :
Response Timeout/Boot Ack Timeout, RCRC : Response CRC, SBE : Start Bit Error, DRTO : Data
Read Timeout/BDS timeout, DCRC : Data CRC for Receive, RE : Response Error.
Writing 1 clears this bit. The abort condition of the IDMAC depends on the setting of this CES bit.
If the CES bit is enabled, then the IDMAC aborts on a response error. (R/W)
IDSTS_DU Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to
OWN bit = 0 (DES0[31] =0). Writing 1 clears this bit. (R/W)
IDSTS_FBE Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]) . When this
bit is set, the DMA disables all its bus accesses. Writing 1 clears this bit. (R/W)
IDSTS_RI Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing 1
clears this bit. (R/W)
IDSTS_TI Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing 1
clears this bit. (R/W)
se _ S
IN _ E
ID rve DU
(re TEN CE
ID TEN FB
se NI
N_ I
TE AI
TI
TE R
d)
ID ed)
ID TE N )
IN _
(re N_
IN _
IN _
IN d
ID TEN
ID TEN
ve
rv
r
se
IN
IN
(re
ID
31 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IDINTEN_CES Card Error summary Interrupt Enable. When set, it enables the Card Interrupt sum-
mary. (R/W)
IDINTEN_DU Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary
Enable, the DU interrupt is enabled. (R/W)
IDINTEN_FBE Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal
Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. (R/W)
IDINTEN_RI Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive
Interrupt is enabled. When reset, Receive Interrupt is disabled. (R/W)
IDINTEN_TI Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit
Interrupt is enabled. When reset, Transmit Interrupt is disabled. (R/W)
31 0
0x000000000 Reset
DSCADDR_REG Host Descriptor Address Pointer, updated by IDMAC during operation and cleared
on reset. This register points to the start address of the current descriptor read by the IDMAC.
(RO)
31 0
0x000000000 Reset
BUFADDR_REG Host Buffer Address Pointer, updated by IDMAC during operation and cleared on
reset. This register points to the current Data Buffer Address being accessed by the IDMAC. (RO)
L
L
SE
SE
_S
V_
F_
DR
SA
SL
N
H
L
E_
E_
E_
E_
E_
E_
G
DG
DG
G
D
D
_E
_E
_E
_E
_E
_E
d)
IN
IN
IN
IN
IN
IN
ve
LK
LK
LK
LK
LK
LK
r
se
CC
CC
CC
CC
CC
CC
(re
31 21 20 17 16 13 12 9 8 6 5 3 2 0
CCLKIN_EDGE_L The low level of the divider clock. The value should be larger than
CCLKIN_EDGE_H. (R/W)
CCLKIN_EDGE_H The high level of the divider clock. The value should be smaller than
CCLKIN_EDGE_L. (R/W)
CCLKIN_EDGE_SLF_SEL It is used to select the clock phase of the internal signal from phase90,
phase180, or phase270. (R/W)
CCLKIN_EDGE_SAM_SEL It is used to select the clock phase of the input signal from phase90,
phase180, or phase270. (R/W)
CCLKIN_EDGE_DRV_SEL It is used to select the clock phase of the output signal from phase90,
phase180, or phase270. (R/W)
10.1 Overview
Features of Ethernet
By using the external Ethernet PHY (physical layer), ESP32 can send and receive data via Ethernet MAC (Media
Access Controller) according to the IEEE 802.3 standard, as Figure 41 shows. Ethernet is currently the most
commonly used network protocol that controls how data is transmitted over local- and wide-area networks,
abbreviated as LAN and WAN, respectively.
• IEEE 1588-2008 standard for specifying the accuracy of networked clock synchronization
• Two industry-standard interfaces conforming with IEEE 802.3-2002: Media-Independent Interface (MII) and
Reduced Media-Independent Interface (RMII).
• Support for a data transmission rate of 10 Mbit/s or 100 Mbit/s through an external PHY interface
• Communication with an external Fast Ethernet PHY through IEEE 802.3-compliant MII and RMII interfaces
• Support for:
– Carrier Sense Multiple Access / Collision Detection (CSMA/CD) protocol in half-duplex mode
– operations in full-duplex mode, forwarding the received pause-control frame to the user application
– If the flow control input signal disappears during a full-duplex operation, a pause frame with zero
pause time value is automatically transmitted.
• The Preamble and the Start Frame Delimiter (SFD) are inserted in the Transmit path, and deleted in the
Receive path.
• Cyclic Redundancy Check (CRC) and Pad can be controlled on a per-frame basis.
• The Pad is generated automatically, if data is below the minimum frame length.
– All frames in mixed mode can be transmitted without being filtered for network monitoring
– A status report is attached each time all incoming packets are transmitted and filtered
• Use of the Management Data Input/Output (MDIO) interface to configure and manage PHY devices
• Support for the offloading of received IPv4 and TCP packets encapsulated by an Ethernet frame in the
reception function
• Support for checking IPv4 header checksums, as well as TCP, UDP, or ICMP (Internet Control Message
Protocol) checksums encapsulated in IPv4/IPv6 packets in the enhanced reception function
• Support for Ethernet frame timestamps. (For details please refer to IEEE 1588-2008.) Each frame has a
64-bit timestamp when transmitted or received.
• Two sets of FIFOs: one 2 KB Tx FIFO with programmable threshold and one 2 KB Rx FIFO with
configurable threshold (64 bytes by default)
• When Rx FIFO stores multiple frames, the Receive Status Vector is inserted into the Rx FIFO after
transmitting an EOF (end of frame), so that the Rx FIFO does not need to store the Receive Status of these
frames.
• In store-and-forward mode, all error frames can be filtered during reception, but not forwarded to the
application.
• Support for data statistics by generating pulses for lost or corrupted frames in the Rx FIFO due to an
overflow
• Support for store-and-forward mechanism when transmitting data to the MAC core
• Automatic re-transmission of collided frames during transmission (subject to certain conditions, see section
10.2.1.2)
• Discarding frames in cases of late collisions, excessive collisions, excessive deferrals, and under-run
conditions
• Calculating the IPv4 header checksum, as well as the TCP, UDP, or ICMP checksum, and then inserting
them into frames transmitted in store-and-forward mode.
Ethernet MAC consists of the MAC-layer configuration register module and three layers: EMAC_CORE (MAC
Core Layer), EMAC_MTL (MAC Transition Layer), and EMAC_DMA (Direct Memory Access). Each of these three
layers has two directions: Tx and Rx. They are connected to the system through the Advanced
High-Performance Bus (AHB) and the Advanced Peripheral Bus (APB) on the chip. Off the chip, they
communicate with the external PHY through the MII and RMII interfaces to establish an Ethernet
connection.
10.2 EMAC_CORE
The MAC supports many interfaces with the PHY chip. The PHY interface can be selected only once after reset.
The MAC communicates with the application side (DMA side), using the MAC Transmit Interface (MTI), MAC
Receive Interface (MRI) and the MAC Control Interface (MCI).
After the EOF (end of frame) is transmitted to the MAC, the MAC completes the normal transmission and yields
the Transmit Status to the MTL. If a normal collision (in half-duplex mode) occurs during transmission, the MAC
makes valid the Transmit Status in the MTL. It then accepts and drops all further data until the next SOF is
received. The MTL block should retransmit the same frame from SOF upon observing a retry request (in the
Status) from the MAC.
The MAC issues an underflow status if the MTL is not able to provide the data continuously during transmission.
During the normal transmission of a frame from MTL, if the MAC receives an SOF without getting an EOF for the
previous frame, it ignores the SOF and considers the new frame as a continuation of the previous one.
In full-duplex mode, when the Transmit Flow Control Enable bit (TFE bit in the Flow Control Register) is set to 1,
the MAC will generate and send a pause frame, as needed. The pause frame is added and transmitted together
with the calculated CRC. The generation of pause frames can be initiated in two ways.
When the application sets the Flow Control Busy bit (FCB bit in the Flow Control Register) to 1, or when the Rx
FIFO is full, a pause frame is transmitted.
• If an application has requested flow control by setting the FCB bit in the Flow Control Register to 1, the MAC
will generate and send a single pause frame. The pause time value in the generated frame is the pause time
value programmed in the Flow Control Register. To extend or end the pause time before the time specified
in the previously transmitted pause frame, the application program must configure the pause time value in
the Flow Control Register to the appropriate value and, then, request another pause frame transmission.
• If the application has requested flow control when the Rx FIFO is full, the MAC will generate and transmit a
pause frame. The value of the pause time of the generated frame is the pause time value programmed in
the Flow Control Register. If the Rx FIFO remains full during the configurable interval, which is determined
by the Pause Low Threshold bit (PLT) in the Flow Control Register before the pause time expires, a second
pause frame will be transmitted. As long as the Rx FIFO remains full, the process repeats itself. If the FIFO
is no longer full before the sample time, the MAC will send a pause frame with zero pause time, indicating
to the remote end that the Rx buffer is ready to receive the new data frame.
In half-duplex mode, a collision may occur on the MAC line interface when frames are transmitted to the MAC.
The MAC may even give a status to indicate a retry before the end of the frame is received. The retransmission is
then enabled and the frame is popped out from the FIFO. When more than 96 bytes are transmitted to the MAC
core, the FIFO controller frees the space in the FIFO, allowing the DMA to push more data into FIFO. This means
that data cannot be retransmitted after the threshold is exceeded or when the MAC core indicates that a late
collision has occurred.
The MAC transmitter may abort the transmission of a frame because of collision, Tx FIFO underflow, loss of
carrier, jabber timeout, no carrier, excessive deferral, and late collision. When frame transmission is aborted
because of collision, the MAC requests retransmission of the frame.
The frame received by the MAC will be pushed into the Rx FIFO. Once the FIFO status exceeds the Receive
Threshold, configured by the Receive Threshold Control (RTC) bit in the Operation Mode register, the DMA can
initiate a preconfigured burst transmission to the AHB interface.
In the default pass-through mode, when the FIFO receives a complete packet or 64 bytes configured by the RTC
bit in the Operation Mode Register, the data pops up and its availability is notified to the DMA. After the DMA
initiates the transmission to the AHB interface, the data transmission continues from the FIFO until the complete
packet is transmitted. Upon completing transmitting the EOF, the status word will pop up and be transmitted to
the DMA controller.
In the Rx FIFO Store-and-Forward mode (configured through the RSF or Receive Store and Forward bit in the
Operation Mode Register), only the valid frames are read and forwarded to the application. In the passthrough
mode, error frames are not discarded because the error status is received at the end of the frame. The start of
frame will have been read from the FIFO at that point.
After the receive module receives the packets, the Preamble and SFD of the received frames are removed. When
the SFD is detected, the MAC starts sending Ethernet frame data to the Rx FIFO, starting at the first byte
(destination address) following the SFD. This timestamp is passed on to the application, unless the MAC filters
out and drops the frame.
If the received frame length/type is less than 0x600 and the automatic CRC/Pad removal option is programmed
for the MAC, the MAC will send frame data to the Rx FIFO (the amount of data does not exceed the number
specified in the length/type field). Then MAC begins discarding the remaining section, including the FCS field. If
the frame length/type is greater than, or equal to, 0x600, the MAC will send all received Ethernet frame data to
the Rx FIFO, regardless of the programmed value of the automatic CRC removal option. By default, the MAC
watchdog timer is enabled, meaning that frames, including DA, SA, LT, data, pad and FCS, which exceed 2048
bytes, are cut off. This function can be disabled by programming the Watchdog Disable (WD) bit in the MAC
Configuration Register. However, even if the watchdog timer is disabled, frames longer than 16 KB will be cut off
and the watchdog timeout status will be given.
If the RA (Receive All) bit in the MAC Frame Filter Register is reset, the MAC will filter frames based on the
destination and source addresses. If the application decides not to receive any bad frames, such as runt frames
and CRC error frames, another level of filtering is needed. When a frame fails the filtering, the frame is discarded
and is not transmitted to the application. When the filter parameters are changed dynamically, if a frame fails the
DA and SA filterings, the remaining part of the frame is discarded and the Receive Status word is updated
immediately and, therefore, the zero frame length bit, CRC error bit, and runt frame error bit are set to 1. This
indicates that the frame has failed the filtering.
The MAC will detect the received pause frame and pause transmission of frames for a specified delay within the
received pause frame (in full-duplex mode only). The Pause Frame Detect Function can be enabled or disabled
by the RFCE (Receive Flow Control Enable) bit in the Flow Control Register. When receive flow control is enabled,
it starts monitoring whether the destination address of the received frame matches the multicast address of the
control frame (0x0180 C200 0001). If a match is detected (i.e. the destination address of the received frame
matches the destination address of the reserved control frame), the MAC will determine whether to transmit the
received control frame to the application, according to the PCF (Pass Control Frames) bit in the Frame Filter
Register.
The MAC will also decode the type, the opcode, and the pause timer field of the Receive Control Frame. If the
value of the status byte counter is 64 bits and there are no CRC errors, the MAC transmitter will halt the
transmission of any data frame. The duration of the pause is the decoded pause time value multiplied by the
interval (which is 64 bytes for both 10 Mbit/s and 100 Mb/s modes). At the same time, if another pause frame of
zero pause time is detected, the MAC will reset the pause time to manage the new pause request.
If the type field (0x8808), the opcode (0x00001), and the byte length (64 bytes) of the received control frame are
not 0x8808, 0x00001, and 64 bytes, respectively, or if there is a CRC error, the MAC will not generate a
pause.
If a pause frame has a multicast destination address, the MAC filters the frame, according to the address
matching.
For pause frames with a unicast destination address, the MAC checks whether the DA matches the content of
the EMACADDR0 Register, and whether the Unicast Pause Frame Detect (UPFD) bit in the Flow Control Register
is set to 1. The Pass Control Frames (PCF) bits in the Frame Filter Register [7:6] control the filtering of frames and
addresses.
Since the status is available immediately after the data is received. Frames can be stored there, as long as the
FIFO is not full.
If the Rx FIFO is full before receiving the EOF data from the MAC, an overflow will be generated and the entire
frame will be discarded. In fact, status bit RDES0[11] will indicate that this frame is partial due to an overflow, and
that it should be discarded.
If the function that corresponds to the Flush Transmit FIFO (FTF) bit and the Forward Undersized Good Frames
(FUGF) bit in the Operation Mode Register is enabled, the Rx FIFO can filter error frames and runt frames. If the
receive FIFO is configured to operate in store-and-forward mode, all error frames will be filtered and
discarded.
In passthrough mode, if a frame’s status and length are available when reading a SOF from the Rx FIFO, the
entire error frame can be discarded. DMA can clear the error frame being read from the FIFO by enabling the
Receive Frame Clear bit. The data transmission to the application (DMA) will then stop, and the remaining frames
will be read internally and discarded. If FIFO is available, the transmission of the next frame will be initiated.
After receiving the Ethernet frames, the MAC outputs the receive status to the application. The detailed
description of the receive status is the same as that which is configured by bit [31:0] in RDES0.
The interrupt register bits only indicate various interrupt events. To clear the interrupts, the corresponding status
register and other registers must be read. An Interrupt Status Register describes the events that prompt the MAC
core to generate interrupts. Each interrupt event can be prevented by setting the corresponding mask bit in the
Interrupt Mask Register to 1. For example, if bit3 of the interrupt register is set high, it indicates that a magic
packet or Wake-on-LAN frame has been received in Power-down mode. The PMT Control and Status register
must be read to clear this interrupt event.
Physical (MAC) addresses are used for address checking during address filtering.
In perfect filtering mode, the multicast address is compared with the programmed MAC Destination Address
Registers (EMACADDR0 ~ EMACADDR7). Group address filtering is also supported.
When the SAF enable bit is set to 1, the result of the SA filtering and DA filtering is AND’ed to determine whether
or not to forward the frame. Any frame that fails to pass will be discarded. Frames need to pass both filterings in
order to be forwarded to the application.
The following two tables summarize the destination address and source address filtering, based on the type of
the frames received.
The filtering parameters in the MAC Frame Filter Register described in Table 39 are as follows.
Parameter name: Parameter setting:
PM: Pass All Multicast 1: Set
PF: Perfect Filter 0: Cleared
DAIF: Destination Address Inverse Filtering
PAM: Pass All Multicast
DB: Disable Broadcast Frames
The filtering parameters in the MAC Frame Filter Register described in Table 40 are as follows.
Parameter name: Parameter setting:
PM: Pass All Multicast 1: Set
SAF: Source Address Filtering 0: Cleared
SAIF: Source Address Inverse Filtering X: Don’t care
• Jabber timeout
• Late collision
• Frame underflow
• Excessive deferral
• Excessive collision
The received frames are considered ”good frames”, if there are not any of the following errors:
• CRC error
• Frame size over the maximum size (for non-type frames over the maximum frame size only)�
For details please refer to Register Summary and Linked List Descriptors.
Interface signals between MII and PHY are shown in Figure 43.
• MII_TX_CLK: TX clock signal. This signal provides the reference timing for TX data transmission. The
frequencies are divided into two types: 2.5 MHz at a data transmission rate of 10 Mbit/s, and 25 MHz at
100 Mbit/s.
• MII_TXD[3:0]: Transmit data signal in groups of four, syn-driven by the MAC sub-layer, and valid only when
the MII_TX_EN signal is valid. MII_TXD[0] is the lowest significant bit and MII_TXD[3] is the highest
significant bit. When the signal MII_TX_EN is pulled low, sending data does not have any effect on the PHY.
• MII_TX_EN: Transmit data enable signal. This signal indicates that the MAC is currently sending nibbles (4
bits) for the MII. This signal must be synchronized with the first nibble of the header (MII_TX_CLK) and must
be synchronized when all nibbles to be transmitted are sent to the MII.
• MII_RX_CLK: RX clock signal. This signal provides the reference timing for RX data transmission. The
frequencies are divided into two types: 2.5 MHz at the data transmission rate of 10 Mbit/s, and 25 MHz at
100 Mbit/s.
• MII_RXD[3:0]: Receive data signal in groups of four, syn-driven by the PHY, and valid only when MII_RX_DV
signal is valid. MII_RXD[0] is the lowest significant bit and MII_RXD[3] is the highest significant bit. When
MII_RX_DV is disabled and MII_RX_ER is enabled, the specific MII_RXD[3:0] value represents specific
information from the PHY.
• MII_RX_DV: Receive data valid signal. This signal indicates that the PHY is currently receiving the recovered
and decoded nibble that will be transmitted to the MII. This signal must be synchronized with the first nibble
of the recovered frame (MII_RX_CLK) and remain synchronized till the last nibble of the recovered frame.
This signal must be disabled before the first clock cycle following the last nibble. In order to receive the
frame correctly, the MII_RX_DV signal must cover the frame to be received over the time range, starting no
later than when the SFD field appears.
• MII_CRS: Carrier sense signal. When the transmitting or receiving medium is in the non-idle state, the
signal is enabled by the PHY. When the transmitting or receiving medium is in the idle state, the signal is
disabled by the PHY. The PHY must ensure that the MII_CRS signal remains valid under conflicting
conditions. This signal does not need to be synchronized with the TX and RX clocks. In full-duplex mode,
this signal is insignificant.
• MII_COL: Collision detection signal. After a collision is detected on the medium, the PHY must immediately
enable the collision detection signal, and the collision detection signal must remain active as long as a
condition for collision exists. This signal does not need to be synchronized with the TX and RX clocks. In
full-duplex mode, this signal is meaningless.
• MII_RX_ER: Receive error signal. The signal must remain for one or more cycles (MII_RX_CLK) to indicate
to the MAC sublayer that an error has been detected somewhere in the frame.
• MDIO and MDC: Management Data Input/Output and Management Data Clock. The two signals constitute
a serial bus defined for the Ethernet family of IEEE 802.3 standards, used to transfer control and data
information to the PHY, see section Station Management Agent (SMA) Interface.
In MII mode, there are two directions of clock, Tx and Rx clocks in the interface between MII and the PHY.
MII_TX_CLK is used to synchronize the TX data, and MII_RX_CLK is used to synchronize the RX data. The
MII_RX_CLK clock is provided by the PHY. The MII_TX_CLK is provided by the chip’s internal PLL or external
crystal oscillator. For details regarding Figure 44, please refer to the clock-related registers in Register
Summary.
The Reduced Media-Independent Interface (RMII) specification reduces the number of pins between the
microcontroller’s external peripherals and the external PHY at a data transmission rate of 10 Mbit/s or 100 Mbit/s.
According to the IEEE 802.3u standard, MII includes 16 pins that contain data and control signals. The RMII
specification reduces 62.5% of the pins to the number of seven.
• The same reference clock must be provided externally both to the MAC and the external Ethernet PHY. It
provides independent 2-bit-wide Tx and Rx data paths.
Please refer to Register Summary for details about the EMII Address Register and the EMII Data Register.
TTSS
OWN
TTSE
TDES0 Ctrl[30:26] Ctrl[24:18] Status[16:7]
[6:3] [2:0]
Ctrl
TDES1 Reserved Transmit Buffer Size[12:0]
[31:29]
TDES2 Buffer Address [31:0]
TDES3 Next Descriptor Address[31:0]
TDES4 Reserved
TDES5 Reserved
TDES6 Transmit Frame Timestamp Low[31:0]
TDES7 Transmit Frame Timestamp High[31:0]
Res
RDES1 Reserved[30:16] Receive Buffer 1 Size[12:0]
[15:14]
RDES2 Buffer1 Address [31:0]
RDES3 Next Descriptor Address[31:0]
RDES4 Extended Status[31:0]
RDES5 Reserved
RDES6 Receive Frame Timestamp Low[31:0]
RDES7 Receive Frame Timestamp High[31:0]
• Latched-low (LL)
• Latched-high (LH)
10.10 Registers
Note: The value of all reset registers must be set to the reset value.
EN
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31 27 26 25 24 23 22 17 16 15 14 13 8 7 6 2 1 0
DMAMIXEDBURST When this bit is set high and the FB(FIXES_BURST) bit is low, the AHB master
interface starts all bursts of a length more than 16 with INCR (undefined burst), whereas it reverts
to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. (R/W)
DMAADDRALIBEA When this bit is set high and the FB bit is 1, the AHB interface generates all bursts
aligned to the start address LS bits. If the FB bit is 0, the first burst (accessing the start address of
data buffer) is not aligned, but subsequent bursts are aligned to the address. (R/W)
PBLX8_MODE When set high, this bit multiplies the programmed PBL(PROG_BURST_LEN) value
(Bits[22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64,
128, and 256 beats depending on the PBL value. (R/W)
USE_SEP_PBL When set high, this bit configures the Rx DMA to use the value configured in
Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When
reset to low, the PBL value in Bits[13:8] is applicable for both DMA engines. (R/W)
RX_DMA_PBL This field indicates the maximum number of beats to be transferred in one Rx DMA
transaction. This is the maximum value that is used in a single block Read or Write.The Rx DMA
always attempts to burst as specified in the RPBL(RX_DMA_PBL) bit each time it starts a burst
transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other
value results in undefined behavior. This field is valid and applicable only when USP(USE_SEP_PBL)
is set high. (R/W)
FIXED_BURST This bit controls whether the AHB master interface performs fixed burst transfers or
not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of
the normal burst transfers. When reset, the AHB interface uses SINGLE and INCR burst transfer
operations. (R/W)
PRI_RATIO These bits control the priority ratio in the weighted round-robin arbitration between the
Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio Rx:Tx
represented by each bit: (R/W)
• 2’b00 — 1: 1
• 2’b01 — 2: 0
• 2’b10 — 3: 1
• 2’b11 — 4: 1
PROG_BURST_LEN These bits indicate the maximum number of beats to be transferred in one DMA
transaction. If the number of beats to be transferred is more than 32, then perform the following
steps: 1. Set the PBLx8 mode; 2. Set the PBL. (R/W)
ALT_DESC_SIZE When set, the size of the alternate descriptor increases to 32 bytes. (R/W)
DESC_SKIP_LEN This bit specifies the number of Word to skip between two unchained descriptors.
The address skipping starts from the end of current descriptor to the start of next descriptor. When
the DSL(DESC_SKIP_LEN) value is equal to zero, the descriptor table is taken as contiguous by
the DMA in Ring mode. (R/W)
DMA_ARB_SCH This bit specifies the arbitration scheme between the transmit and receive paths.
1’b0: weighted round-robin with RX: TX or TX: RX, priority specified in PR (bit[15:14]); 1’b1 Fixed
priority (Rx priority to Tx). (R/W)
SW_RST When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the
MAC. It is cleared automatically after the reset operation is complete in all of the ETH_MAC clock
domains. Before reprogramming any register of the ETH_MAC, you should read a zero (0) value in
this bit. (R/WS/SC)
31 0
0x000000000 Reset
TRANS_POLL_DEMAND When these bits are written with any value, the DMA reads the current
descriptor to which the Register (Current Host Transmit Descriptor Register) is pointing. If that
descriptor is not available (owned by the Host), the transmission returns to the suspend state and
Bit[2] (TU) of Status Register is asserted. If the descriptor is available, the transmission resumes.
(RO/WT)
31 0
0x000000000 Reset
RECV_POLL_DEMAND When these bits are written with any value, the DMA reads the current de-
scriptor to which the Current Host Receive Descriptor Register is pointing. If that descriptor is
not available (owned by the Host), the reception returns to the Suspended state and Bit[7] (RU) of
Status Register is asserted. If the descriptor is available, the Rx DMA returns to the active state.
(RO/WT)
31 0
0x000000000 Reset
START_RECV_LIST This field contains the base address of the first descriptor in the Receive De-
scriptor list. The LSB Bits[1:0] are ignored and internally taken as all-zero by the DMA. Therefore,
these LSB bits are read-only. (R/W)
31 0
0x000000000 Reset
START_TRANS_LIST This field contains the base address of the first descriptor in the Transmit De-
scriptor list. The LSB Bits[1:0] are ignored and are internally taken as all-zero by the DMA. Therefore,
these LSB bits are read-only. (R/W)
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31 30 29 28 27 26 25 23 22 20 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS_TRI_INT This bit indicates an interrupt event in the Timestamp Generator block of the ETH_MAC.
The software must read the corresponding registers in the ETH_MAC to get the exact cause of the
interrupt and clear its source to reset this bit to 1’b0. (RO)
EMAC_PMT_INT This bit indicates an interrupt event in the PMT module of the ETH_MAC. The soft-
ware must read the PMT Control and Status Register in the MAC to get the exact cause of interrupt
and clear its source to reset this bit to 1’b0. (RO)
ERROR_BITS This field indicates the type of error that caused a Bus Error, for example, error response
on the AHB interface. This field is valid only when Bit[13] (FBI) is set. This field does not generate
an interrupt. (RO)
TRANS_PROC_STATE This field indicates the Transmit DMA FSM state. This field does not generate
an interrupt. (RO)
• 3’b111: Running. Transferring the TX packets data from transmit buffer to host memory.
RECV_PROC_STATE This field indicates the Receive DMA FSM state. This field does not generate
an interrupt. (RO)
• 3’b111: Running. Transferring the TX packets data from receive buffer to host memory.
NORM_INT_SUMM Normal Interrupt Summary bit value is the logical OR of the following bits when
the corresponding interrupt bits are enabled in Interrupt Enable Register:(R/SS/WC)
• Bit[14]: Early Receive Interrupt. Only unmasked bits affect the Normal Interrupt Summary bit.
This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit,
which causes NIS to be set, is cleared.
ABN_INT_SUMM Abnormal Interrupt Summary bit value is the logical OR of the following when the
corresponding interrupt bits are enabled in Interrupt Enable Register: (R/SS/WC)
• Bit[13]: Fatal Bus Error. Only unmasked bits affect the Abnormal Interrupt Summary bit. This
is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit,
which causes AIS to be set, is cleared.
EARLY_RECV_INT This bit indicates that the DMA filled the first data buffer of the packet. This bit is
cleared when the software writes 1 to this bit or when Bit[6] (RI) of this register is set (whichever
occurs earlier). (R/SS/WC)
FATAL_BUS_ERR_INT This bit indicates that a bus error occurred, as described in Bits [25:23]. When
this bit is set, the corresponding DMA engine disables all of its bus accesses. (R/SS/WC)
EARLY_TRANS_INT This bit indicates that the frame to be transmitted is fully transferred to the MTL
Transmit FIFO. (R/SS/WC)
RECV_WDT_TO When set, this bit indicates that the Receive Watchdog Timer expired while receiving
the current frame and the current frame is truncated after the watchdog timeout. (R/SS/WC)
RECV_PROC_STOP This bit is asserted when the Receive Process enters the Stopped state.
(R/SS/WC)
RECV_BUF_UNAVAIL This bit indicates that the host owns the Next Descriptor in the Receive List and
the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive
descriptors, the host should change the ownership of the descriptor and issue a Receive Poll
Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when
the next recognized incoming frame is received. This bit is set only when the previous Receive
Descriptor is owned by the DMA. (R/SS/WC)
RECV_INT This bit indicates that the frame reception is complete. When reception is complete, the
Bit[31] of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific
frame status information is updated in the descriptor. The reception remains in the Running state.
(R/SS/WC)
TRANS_UNDFLOW This bit indicates that the Transmit Buffer had an Underflow during frame trans-
mission. Transmission is suspended and an Underflow Error TDES0[1] is set. (R/SS/WC)
RECV_OVFLOW This bit indicates that the Receive Buffer had an Overflow during frame recep-
tion. If the partial frame is transferred to the application, the overflow status is set in RDES0[11].
(R/SS/WC)
TRANS_JABBER_TO This bit indicates that the Transmit Jabber Timer expired, which happens when
the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber
Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes
the Transmit Jabber Timeout TDES0[14] flag to assert. (R/SS/WC)
TRANS_BUF_UNAVAIL This bit indicates that the host owns the Next Descriptor in the Transmit
List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit
Process state transitions. To resume processing Transmit descriptors, the host should change
the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand
command. (R/SS/WC)
TRANS_INT This bit indicates that the frame transmission is complete. When transmission is com-
plete, Bit[31] (OWN) of TDES0 is reset, and the specific frame status information is updated in the
descriptor. (R/SS/WC)
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DI
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31 27 26 25 24 23 22 21 20 19 17 16 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DIS_DROP_TCPIP_ERR_FRAM When this bit is set, the MAC does not drop the frames which only
have errors detected by the Receive Checksum engine.When this bit is reset, all error frames are
dropped if the Fwd_Err_Frame bit is reset. (R/W)
RX_STORE_FORWARD When this bit is set, the MTL reads a frame from the Rx FIFO only after the
complete frame has been written to it. (R/W)
DIS_FLUSH_RECV_FRAMES When this bit is set, the Rx DMA does not flush any frames because
of the unavailability of receive descriptors or buffers. (R/W)
TX_STR_FWD When this bit is set, transmission starts when a full frame resides in the MTL Trans-
mit FIFO. When this bit is set, the TX_THRESH_CTRL values specified in TX_THRESH_CTRL are
ignored. (R/W)
FLUSH_TX_FIFO When this bit is set, the transmit FIFO controller logic is reset to its default values
and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing
operation is complete. (R/WS/SC)
TX_THRESH_CTRL These bits control the threshold level of the MTL Transmit FIFO. Transmission
starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition,
full frames with a length less than the threshold are also transmitted. These bits are used only
when TX_STR_FWD is reset. 3’b000: 64, 3’b001: 128, 3’b010: 192, 3’b011: 256, 3’b100: 40,
3’b101: 32, 3’b110: 24, 3’b111: 16. (R/W)
FWD_ERR_FRAME When this bit is reset, the Rx FIFO drops frames with error status (CRC error,
collision error, giant frame, watchdog timeout, or overflow). (R/W)
FWD_UNDER_GF When set, the Rx FIFO forwards Undersized frames (that is, frames with no Error
and length less than 64 bytes) including pad-bytes and CRC.
DROP_GFRM When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that
are larger than the computed giant frame limit. (R/W)
RX_THRESH_CTRL These two bits control the threshold level of the MTL Receive FIFO. Transfer (re-
quest) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold.
2’b00: 64; 2’b01: 32; 2’b10: 96; 2’b11: 128. (R/W)
OPT_SECOND_FRAME When this bit is set, it instructs the DMA to process the second frame of the
Transmit data even before the status for the first frame is obtained. (R/W)
START_STOP_RX When this bit is set, the Receive process is placed in the Running state. The DMA
attempts to acquire the descriptor from the Receive list and processes the incoming frames.When
this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. (R/W)
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DM IN IE
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DM
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31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
DMAIN_NISE When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal
interrupt summary is disabled. This bit enables the following interrupts in Status Register: (R/W)
DMAIN_AISE When this bit is set, abnormal interrupt summary is enabled. When this bit is reset,
the abnormal interrupt summary is disabled. This bit enables the following interrupts in Status
Register:(R/W)
DMAIN_ERIE When this bit is set with Normal Interrupt Summary Enable (Bit[16]), the Early Receive
Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled. (R/W)
DMAIN_FBEE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Fatal Bus
Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled.
(R/W)
DMAIN_ETIE When this bit is set with an Abnormal Interrupt Summary Enable (Bit[15]), the Early
Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled. (R/W)
DMAIN_RWTE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Receive
Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout
Interrupt is disabled. (R/W)
DMAIN_RSE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Receive
Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled.
(R/W)
DMAIN_RBUE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Receive
Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Inter-
rupt is disabled. (R/W)
DMAIN_RIE When this bit is set with Normal Interrupt Summary Enable (Bit[16]), the Receive Interrupt
is enabled. When this bit is reset, the Receive Interrupt is disabled. (R/W)
DMAIN_UIE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Transmit Un-
derflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled. (R/W)
DMAIN_OIE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Receive Over-
flow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled. (R/W)
DMAIN_TJTE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Transmit
Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt
is disabled. (R/W)
DMAIN_TBUE When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer
Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is
disabled. (R/W)
DMAIN_TSE When this bit is set with Abnormal Interrupt Summary Enable (Bit[15]), the Transmission
Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled.
(R/W)
DMAIN_TIE When this bit is set with Normal Interrupt Summary Enable (Bit[16]), the Transmit Interrupt
is enabled. When this bit is reset, the Transmit Interrupt is disabled. (R/W)
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30 29 28 27 17 16 10 0
Overflow_BFOC This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that
is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario,
the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened.
(R/SS/RC)
Overflow_FC This field indicates the number of frames missed by the application. This counter is
incremented each time the MTL FIFO overflows. The counter is cleared when this register is read.
(R/SS/RC)
Overflow_BMFC This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the
DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the
missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to
all-zeros and this bit indicates that the rollover happened. (R/SS/RC)
Missed_FC This field indicates the number of frames missed by the controller because of the Host
Receive Buffer being unavailable. This counter is incremented each time the DMA discards an
incoming frame. The counter is cleared when this register is read. (R/SS/RC)
TC
r
se
W
(re
RI
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000 Reset
RIWTC This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog
timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA
completes the transfer of a frame for which the RI (RECV_INT) status bit is not set because of the
setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit
is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of
automatic setting of RI as per RDES1[31] of any received frame. (R/W)
31 0
0x000000000 Reset
TRANS_DSCR_ADDR_PTR The address of the current receive descriptor list. Cleared on Reset.
Pointer updated by the DMA during operation. (RO)
31 0
0x000000000 Reset
RECV_DSCR_ADDR_PTR The address of the current receive descriptor list. Cleared on Reset.
Pointer updated by the DMA during operation. (RO)
31 0
0x000000000 Reset
TRANS_BUFF_ADDR_PTR The address of the current receive descriptor list. Cleared on Reset.
Pointer updated by the DMA during operation. (RO)
31 0
0x000000000 Reset
RECV_BUFF_ADDR_PTR The address of the current receive descriptor list. Cleared on Reset.
Pointer updated by the DMA during operation. (RO)
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31 30 28 27 26 24 23 22 21 20 19 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAIRC This field controls the source address insertion or replacement for all transmitted frames.
Bit[30] specifies which MAC Address register (0 or 1) is used for source address insertion or re-
placement based on the values of Bits [29:28]: (R/W)
• 2’b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation.
• 2’b10: If Bit[30] is set to 0, the MAC inserts the content of the MAC Address 0 registers in
the SA field of all transmitted frames. If Bit[30] is set to 1 the MAC inserts the content of the
MAC Address 1 registers in the SA field of all transmitted frames.
• 2’b11: If Bit[30] is set to 0, the MAC replaces the content of the MAC Address 0 registers in
the SA field of all transmitted frames. If Bit[30] is set to 1, the MAC replaces the content of
the MAC Address 1 registers in the SA field of all transmitted frames.
ASS2KP When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets.
When Bit[20] (JE) is not set, the MAC considers all received frames of size more than 2K bytes
as Giant frames. When this bit is reset and Bit[20] (JE) is not set, the MAC considers all received
frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit[20] is
set, setting this bit has no effect on Giant Frame status. (R/W)
EMACWATCHDOG When this bit is set, the MAC disables the watchdog timer on the receiver. The
MAC can receive frames of up to 16,383 bytes. When this bit is reset, the MAC does not allow a
receive frame which more than 2,048 bytes (10,240 if JE is set high) or the value programmed in
Register (Watchdog Timeout Register). The MAC cuts off any bytes received after the watchdog
limit number of bytes. (R/W)
EMACJABBER When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC
can transfer frames of up to 16,383 bytes. When this bit is reset, the MAC cuts off the trans-
mitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during
transmission. (R/W)
EMACJUMBOFRAME When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022
bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.
(R/W)
EMACINTERFRAMEGAP These bits control the minimum IFG between frames during transmission.
(R/W)
• 3’b111: 40 bit times. In the half-duplex mode, the minimum IFG can be configured only for
64 bit times (IFG = 100). Lower values are not considered.
EMACDISABLECRS When set high, this bit makes the MAC transmitter ignore the MII CRS signal
during frame transmission in the half-duplex mode. This request results in no errors generated
because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC
transmitter generates such errors because of Carrier Sense and can even abort the transmissions.
(R/W)
EMACMII This bit selects the Ethernet line speed. It should be set to 1 for 10 or 100 Mbps operations.
In 10 or 100 Mbps operations, this bit, along with FES(EMACFESPEED) bit, it selects the exact
linespeed. In the 10/100 Mbps-only operations, the bit is always 1. (R/W)
EMACFESPEED This bit selects the speed in the MII, RMII interface. 0: 10 Mbps; 1: 100 Mbps.
(R/W)
EMACRXOWN When this bit is set, the MAC disables the reception of frames when the TX_EN is
asserted in the half-duplex mode. When this bit is reset, the MAC receives all packets that are
given by the PHY while transmitting. This bit is not applicable if the MAC is operating in the full-
duplex mode. (R/W)
EMACLOOPBACK When this bit is set, the MAC operates in the loopback mode MII. The MII Receive
clock input (CLK_RX) is required for the loopback to work properly, because the transmit clock is
not looped-back internally. (R/W)
EMACDUPLEX When this bit is set, the MAC operates in the full-duplex mode where it can transmit
and receive simultaneously. This bit is read only with default value of 1’b1 in the full-duplex-mode.
(R/W)
EMACRXIPCOFFLOAD When this bit is set, the MAC calculates the 16-bit one’s complement of the
one’s complement sum of all received Ethernet frame payloads. It also checks whether the IPv4
Header checksum (assumed to be bytes 25/26 or 29/30 (VLAN-tagged) of the received Ethernet
frame) is correct for the received frame and gives the status in the receive status word. The MAC
also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the
IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE
is deselected). When this bit is reset, this function is disabled. (R/W)
EMACRETRY When this bit is set, the MAC attempts only one transmission. When a collision occurs
on the MII interface, the MAC ignores the current frame transmission and reports a Frame Abort
with excessive collision error in the transmit frame status. When this bit is reset, the MAC attempts
retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex
mode. (R/W)
EMACPADCRCSTRIP When this bit is set, the MAC strips the Pad or FCS field on the incoming
frames only if the value of the length field is less than 1,536 bytes. All received frames with length
field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad
or FCS field. When this bit is reset, the MAC passes all incoming frames, without modifying them,
to the Host. (R/W)
EMACBACKOFFLIMIT The Back-Off limit determines the random integer number (r) of slot time de-
lays (512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission
attempt during retries after a collision. This bit is applicable only in the half-duplex mode.
• 11: k = min (n, 1), n = retransmission attempt. The random integer r takes the value in the
range 0 ~ 2000.
EMACTX When this bit is set, the transmit state machine of the MAC is enabled for transmission on
the MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of
the transmission of the current frame, and does not transmit any further frames. (R/W)
EMACRX When this bit is set, the receiver state machine of the MAC is enabled for receiving frames
from the MII. When this bit is reset, the MAC receive state machine is disabled after the completion
of the reception of the current frame, and does not receive any further frames from the MII. (R/W)
PLTF These bits control the number of preamble bytes that are added to the beginning of every Trans-
mit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.
2’b00: 7 bytes of preamble. 2’b01: 5 bytes of preamble. 2’b10: 3 bytes of preamble. (R/W)
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rv
rv
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se
se
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IF
M
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F
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DB
PC
DA
SA
(re
(re
PA
31 30 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0 0 0 0 0 0 0 Reset
RECEIVE_ALL When this bit is set, the MAC Receiver module passes all received frames, irrespective
of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering
is updated (pass or fail) in the corresponding bits in the Receive Status Word. When this bit is reset,
the Receiver module passes only those frames to the Application that pass the SA or DA address
filter. (R/W)
SAFE When this bit is set, the MAC compares the SA field of the received frames with the values
programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame. When
this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of
the Rx Status depending on the SA address comparison. (R/W)
SAIF When this bit is set, the Address Check block operates in inverse filtering mode for the SA
address comparison. The frames whose SA matches the SA registers are marked as failing the
SA Address filter. When this bit is reset, frames whose SA does not match the SA registers are
marked as failing the SA Address filter. (R/W)
PCF These bits control the forwarding of all control frames (including unicast and multicast Pause
frames). (R/W)
• 2’b00: MAC filters all control frames from reaching the application.
• 2’b01: MAC forwards all control frames except Pause frames to application even if they fail
the Address filter.
• 2’b10: MAC forwards all control frames to application even if they fail the Address Filter.
• 2’b11: MAC forwards control frames that pass the Address Filter.
The following conditions should be true for the Pause frames processing:
• Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2
(RFE) of Register (Flow Control Register) to 1.
• Condition 2: The destination address (DA) of the received frame matches the special multicast
address or the MAC Address 0 when Bit 3 (UP) of the Register(Flow Control Register) is set.
• Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.
DBF When this bit is set, the AFM(Address Filtering Module) module blocks all incoming broadcast
frames. In addition, it overrides all other filter settings. When this bit is reset, the AFM module
passes all received broadcast frames. (R/W)
PAM When set, this bit indicates that all received frames with a multicast destination address (first bit
in the destination address field is ’1’) are passed. (R/W)
DAIF When this bit is set, the Address Check block operates in inverse filtering mode for the DA
address comparison for both unicast and multicast frames. When reset, normal filtering of frames
is performed. (R/W)
PMODE When this bit is set, the Address Filter module passes all incoming frames irrespective of the
destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are
always cleared when PR(PRTR AT IO)isset.(R/W )
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M RI
rv
se
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IIC
IID
IIR
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M
M
M
31 16 15 11 10 6 5 2 1 0
MIIDEV This field indicates which of the 32 possible PHY devices are being accessed. (R/W)
MIIREG These bits select the desired MII register in the selected PHY device. (R/W)
• 4’b0000: When the APB clock frequency is 80 MHz, the MDC clock frequency is APB
CLK/42;
• 4’b0000: When the APB clock frequency is 40 MHz, the MDC clock frequency is APB
CLK/26.
MIIWRITE When set, this bit indicates to the PHY that this is a Write operation using the MII Data
register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the
MII Data register. (R/W)
MIIBUSY This bit should read logic 0 before writing to PHY Addr Register and PHY data Register.
During a PHY register access, the software sets this bit to 1’b1 to indicate that a Read or Write
access is in progress. PHY data Register is invalid until this bit is cleared by the MAC. Therefore,
PHY data Register (MII Data) should be kept valid until the MAC clears this bit during a PHY Write
operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is
cleared. The subsequent read or write operation should happen only after the previous operation
is complete. Because there is no acknowledgment from the PHY to MAC after a read or write
operation is completed, there is no change in the functionality of this bit even when the PHY is not
present. (R/WS/SC)
A
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AT
rv
D
se
II_
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M
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 Reset
MII_DATA This field contains the 16-bit data value read from the PHY after a Management Read
operation or the 16-bit data value to be written to the PHY before a Management Write operation.
(R/W)
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A
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U
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PL
TF
31 16 15 6 5 4 3 2 1 0
PAUSE_TIME This field holds the value to be used in the Pause Time field in the transmit control
frame. If the Pause Time bits is configured to be double-synchronized to the MII clock domain,
then consecutive writes to this register should be performed only after at least four clock cycles in
the destination clock domain. (R/W)
PLT This field configures the threshold of the Pause timer automatic retransmission of the Pause frame.
The threshold values should be always less than the Pause Time configured in Bits[31:16]. For
example, if PT = 100H (256 slot-times), and PLT = 01, then a second Pause frame is automatically
transmitted at 228 (256-28) slot times after the first Pause frame is transmitted. The following list
provides the threshold values for different values: (R/W)
• 2’b00: The threshold is Pause time minus 4 slot times (PT-4 slot times).
• 2’b01: The threshold is Pause time minus 28 slot times (PT-28 slot times).
• 2’b10: The threshold is Pause time minus 144 slot times (PT-144 slot times).
• 2’b11: The threshold is Pause time minus 256 slot times (PT-256 slot times). The slot time is
defined as the time taken to transmit 512 bits (64 bytes) on the MII interface.
UPFD A pause frame is processed when it has the unique multicast address specified in the IEEE
Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of
the station. This unicast address should be as specified in the EMACADDR0 High Register and
EMACADDR0 Low Register. When this bit is reset, the MAC only detects Pause frames with unique
multicast address. (R/W)
RFCE When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for
a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled.
(R/W)
TFCE In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to
transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled,
and the MAC does not transmit any Pause frames. In the half-duplex mode, when this bit is set,
the MAC enables the backpressure operation. When this bit is reset, the backpressure feature is
disabled. (R/W)
FCBBA This bit initiates a Pause frame in the full-duplex mode and activates the backpressure function
in the half-duplex mode if the TFCE bit is set. In the full-duplex mode, this bit should be read as
1’b0 before writing to the Flow Control register. To initiate a Pause frame, the Application must set
this bit to 1’b1. During a transfer of the Control Frame, this bit continues to be set to signify that
a frame transmission is in progress. After the completion of Pause frame transmission, the MAC
resets this bit to 1’b0. The Flow Control register should not be written to until this bit is cleared. In
the half-duplex mode, when this bit is set (and TFCE is set), then backpressure is asserted by the
MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending
a JAM pattern resulting in a collision. When the MAC is configured for the full-duplex mode, the
BPA is automatically disabled. (R/WS/SC)(FCB)/(R/W)(BPA(backpressure activate))
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TL
TL
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M
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31 26 25 24 23 22 21 20 19 18 17 16 15 10 9 8 7 6 5 4 3 2 1 0
MTLTSFFS When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot
accept any more frames for transmission. (RO)
MTLTFNES When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for
transmission. (RO)
MTLTFWCS When high, this bit indicates that the MTL Tx FIFO Write Controller is active and is trans-
ferring data to the Tx FIFO. (RO)
MTLTFRCS This field indicates the state of the Tx FIFO Read Controller: (RO)
MACTP When high, this bit indicates that the MAC transmitter is in the Pause condition (in the full-
duplex-mode) and hence does not schedule any frame for transmission. (RO)
MACTFCS This field indicates the state of the MAC Transmit Frame Controller module: (RO)
• 2’b01: Waiting for status of previous frame or IFG or backoff period to be over.
• 2’b10: Generating and transmitting a Pause frame (in the full-duplex mode).
MACTPES When high, this bit indicates that the MAC MII transmit protocol engine is actively trans-
mitting data and is not in the IDLE state. (RO)
MTLRFFLS This field gives the status of the fill-level of the Rx FIFO: (RO)
MTLRFRCS This field gives the state of the Rx FIFO read Controller: (RO)
MTLRFWCAS When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is
transferring a received frame to the FIFO. (RO)
MACRFFCS When high, this field indicates the active state of the FIFO Read and Write controllers
of the MAC Receive Frame Controller Module. MACRFFCS[1] represents the status of FIFO Read
controller. MACRFFCS[0] represents the status of small FIFO Write controller. (RO)
MACRPES When high, this bit indicates that the MAC MII receive protocol engine is actively receiving
data and not in IDLE state. (RO)
FR
UF
RW
T_
PM
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
WKUPPKTFILTER The MSB (31st bit) must be zero. Bit j[30:0] is the byte mask. If Bit 1/2/3/4
(byte number) of the byte mask is set, the CRC block processes the filter 0/1/2/3 Offset + j of the
incoming packet (RWKPTR is 0/1/2/3). (R/W)
• RWKPTR is 4: Bit 3/11/19/27 specifies the address type, defining the destination address
type of the pattern. When the bit is set, the pattern applies to only multicast packets; when
the bit is reset, the pattern applies only to unicast packet for filter 0/1/2/3. Bit 0/8/16/24 is
the enable bit for filter 0/1/2/3;
• RWKPTR is 5: This filter 0/1/2/3 offset register defines the offset (within the packet) from
which the filter 0/1/2/3 examines the packets;
• RWKPTR is 6: This filter 0 (bit[15:0])/1 (bit[31:16]) CRC16 register contains the CRC16 value
calculated from the pattern and also the byte mask programmed to the wake-up filter register
block; The polynomial:
G(x) = x16 + x15 + x2 + 1.
• RWKPTR is 7: This filter 2 bit[15:0])/3(bit[31:16]) CRC16 register contains the CRC16 value
calculated from the pattern and also the byte mask programmed to the wake-up filter register
block. The polynomial:
G(x) = x16 + x15 + x2 + 1.
ST
rv T
D
se VD
W N
PW PK EN
S
KP V
(re ILTR
RD TE
(re CA
N
)
d)
RW ed)
RW ed)
G C
(re RC
ed
TR
G T
ve
M PR
M PK
LU
rv
rv
KP
KF
r
se
se
se
K
K
LB
RW
RW
(re
G
31 30 29 28 24 23 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 Reset
RWKFILTRST When this bit is set, it resets the remote RWKPTR register to 3’b000. (R/WS/SC)
RWKPTR The maximum value of the pointer is 7 ,the detail information ,please refer to PMT_RWUFFR.
(RO)
GLBLUCAST When set, enables any unicast packet filtered by the MAC (DAFilter) address recognition
to be a remote wake-up frame. (R/W)
RWKPRCVD When set, this bit indicates the power management event is generated because of the
reception of a remote wake-up frame. This bit is cleared by a Read into this register. (R/SS/RC)
MGKPRCVD When set, this bit indicates that the power management event is generated because of
the reception of a magic packet. This bit is cleared by a Read into this register. (R/SS/RC)
RWKPKTEN hen set, enables generation of a power management event because of remote wake-up
frame reception. (R/W)
MGKPKTEN When set, enables generation of a power management event because of magic packet
reception. (R/W)
PWRDWN hen set, the MAC receiver drops all received frames until it receives the expected magic
packet or remote wake-up frame. This bit must only be set when MGKPKTEN, GLBLUCAST, or
RWKPKTEN bit is set high. (R/WS/SC)
S d)
)
ed
ed
ed
PL rve
TL IEN
TL IST
EN
RL IEX
(re XA
ST
TL EX
v
rv
rv
N
er
se
se
se
IE
PI
IT
PI
PI
P
P
P
s
(re
(re
(re
RL
RL
LP
LP
31 20 19 18 17 16 15 10 9 8 7 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LPITXA This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on
the transmit side.If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after
all outstanding frames and pending frames have been transmitted. The MAC comes out of the
LPI mode when the application sends any frame.When this bit is 0, the LPIEN bit directly controls
behavior of the MAC when it is entering or coming out of the LPI mode. (R/W)
PLS This bit indicates the link status of the PHY. When set, the link is considered to be okay (up) and
when reset, the link is considered to be down. (R/W)
LPIEN When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit
instructs the MAC to exit the LPI state and resume normal transmission.This bit is cleared when
the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for
transmission. (R/W/SC)
RLPIST When set, this bit indicates that the MAC is receiving the LPI pattern on the MII interface.
(R/W)
TLPIST When set, this bit indicates that the MAC is receiving the LPI pattern on the MII interface.
(R/W)
RLPIEX When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on
the MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a
read into this register. (R/SS/RC)
RLPIEN When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered
the LPI state. This bit is cleared by a read into this register. (R/SS/RC)
TLPIEX When set, this bit indicates that the MAC transmitter has exited the LPI state after the user
has cleared the LPIEN bit and the LPI_TW_Timer has expired.This bit is cleared by a read into this
register. (R/SS/RC)
TLPIEN When set, this bit indicates that the MAC Transmitter has entered the LPI state because of
the setting of the LPIEN bit. This bit is cleared by a read into this register. (R/SS/RC)
ER
ER
IM
IM
_T
)
_T
ed
W
LS
rv
_T
se
I_
I
LP
LP
(re
31 26 25 16 15 0
0 0 0 0 0 0 0 x 3 E 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LPI_LS_TIMER This field specifies the minimum time (in milliseconds) for which the link status from
the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC
does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI_LS_Timer reaches
the programmed terminal count. The default value of the LPI_LS_Timer is 1000 (1 sec) as defined
in the IEEE standard.(R/W)
LPI_TW_TIMER This field specifies the minimum time (in microseconds) for which the MAC waits after
it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The
TLPIEX status bit is set after the expiry of this timer.(R/W)
d)
S
ed
ed
ed
e
(re NTS
NT
rv
rv
rv
rv
TI
se
se
se
se
II
PM
(re
(re
(re
LP
31 11 10 9 8 4 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LPIINTS When the Energy Efficient Ethernet feature is enabled, this bit is set for any LPI state entry or
exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit[0] of Register (LPI Control
and Status Register). (RO)
PMTINTS This bit is set when a magic packet or remote wake-up frame is received in the power-down
mode (see Bit[5] and Bit[6] in the PMT Control and Status Register). This bit is cleared when both
Bits[6:5] are cleared because of a read operation to the PMT Control and Status register. This bit
is valid only when you select the optional PMT module during core configuration. (RO)
K
rv SK
AS
)
)
se A
M
ed
ed
ed
ed
(re NTM
NT
rv
rv
rv
TI
se
se
se
II
PM
(re
(re
(re
LP
31 11 10 9 8 4 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LPIINTMASK When set, this bit disables the assertion of the interrupt signal because of the setting
of the LPI Interrupt Status bit in Register (Interrupt Status Register). (R/W)
PMTINTMASK When set, this bit disables the assertion of the interrupt signal because of the setting
of PMT Interrupt Status bit in Register (Interrupt Status Register). (R/W)
I
_H
LE
S0
AB
ES
EN
DR
S_
)
ed
D
ES
_A
rv
DR
AC
se
AD
(re
M
31 30 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0FFFF Reset
MAC_ADDRESS0_HI This field contains the upper 16 bits (47:32) of the first 6-byte MAC address.
The MAC uses this field for filtering the received frames and inserting the MAC address in the
Transmit Flow Control (Pause) Frames. (R/W)
31 0
0x0FFFFFFFF Reset
EMACADDR0LOW_REG This field contains the lower 32 bits of the first 6-byte MAC address. This
is used by the MAC for filtering the received frames and inserting the MAC address in the Transmit
Flow Control (Pause) Frames. (R/W)
L
RO
RE 1
I
SS
_H
NT
DD LE
S1
_A AB
O
_C
S
CE _EN
RE
TE
DD
UR SS
BY
)
ed
_A
SO RE
K_
rv
AC
se
AS
D
AD
(re
M
M
31 30 29 24 23 16 15 0
ADDRESS_ENABLE1 When this bit is set, the address filter module uses the second MAC address
for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
(R/W)
SOURCE_ADDRESS When this bit is set, the EMACADDR1[47:0] is used to compare with the SA
fields of the received frame. When this bit is reset, the EMACADDR1[47:0] is used to compare with
the DA fields of the received frame. (R/W)
MASK_BYTE_CONTROL These bits are mask control bits for comparison of each of the
EMACADDR1 bytes. When set high, the MAC does not compare the corresponding byte of re-
ceived DA or SA with the contents of EMACADDR1 registers. Each bit controls the masking of the
bytes as follows:
You can filter a group of addresses (known as group address filtering) by masking one or more
bytes of the address. (R/W)
MAC_ADDRESS1_HI This field contains the upper 16 bits, Bits[47:32] of the second 6-byte MAC
address. (R/W)
31 0
0x0FFFFFFFF Reset
EMACADDR1LOW_REG This field contains the lower 32 bits of the second 6-byte MAC address.
The content of this field is undefined, so the register needs to be configured after the initialization
process. (R/W)
L2
RO
2
RE 2
I
SS
_H
NT
DD LE
S2
_A AB
O
_C
S
CE _EN
RE
TE
DD
UR SS
BY
d)
ve
_A
SO RE
K_
er
AC
AS
D
s
AD
(re
M
M
31 30 29 24 23 16 15 0
ADDRESS_ENABLE2 When this bit is set, the address filter module uses the third MAC address for
perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
(R/W)
SOURCE_ADDRESS2 When this bit is set, the EMACADDR2[47:0] is used to compare with the SA
fields of the received frame. When this bit is reset, the EMACADDR2[47:0] is used to compare with
the DA fields of the received frame. (R/W)
MASK_BYTE_CONTROL2 These bits are mask control bits for comparison of each of the
EMACADDR2 bytes. When set high, the MAC does not compare the corresponding byte of re-
ceived DA or SA with the contents of EMACADDR2 registers. Each bit controls the masking of the
bytes as follows:
You can filter a group of addresses (known as group address filtering) by masking one or more
bytes of the address. (R/W)
MAC_ADDRESS2_HI This field contains the upper 16 bits, Bits[47:32] of the third 6-byte MAC ad-
dress. (R/W)
31 0
0x0FFFFFFFF Reset
EMACADDR2LOW_REG This field contains the lower 32 bits of the third 6-byte MAC address. The
content of this field is undefined, so the register needs to be configured after the initialization pro-
cess. (R/W)
L3
RO
3
RE 3
I
SS
_H
NT
DD LE
S3
_A AB
O
_C
S
CE _EN
RE
TE
DD
UR SS
BY
d)
ve
_A
SO RE
K_
er
AC
AS
D
s
AD
(re
M
M
31 30 29 24 23 16 15 0
ADDRESS_ENABLE3 When this bit is set, the address filter module uses the fourth MAC address for
perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
(R/W)
SOURCE_ADDRESS3 When this bit is set, the EMACADDR3[47:0] is used to compare with the SA
fields of the received frame. When this bit is reset, the EMACADDR3[47:0] is used to compare with
the DA fields of the received frame. (R/W)
MASK_BYTE_CONTROL3 These bits are mask control bits for comparison of each of the
EMACADDR3 bytes. When set high, the MAC does not compare the corresponding byte of re-
ceived DA or SA with the contents of EMACADDR3 registers. Each bit controls the masking of the
bytes as follows:
You can filter a group of addresses (known as group address filtering) by masking one or more
bytes of the address. (R/W)
MAC_ADDRESS3_HI This field contains the upper 16 bits, Bits[47:32] of the fourth 6-byte MAC ad-
dress. (R/W)
31 0
0x0FFFFFFFF Reset
EMACADDR3LOW_REG This field contains the lower 32 bits of the fourth 6-byte MAC address.
The content of this field is undefined, so the register needs to be configured after the initialization
process. (R/W)
L4
RO
4
RE 4
I
SS
_H
NT
DD LE
S4
_A AB
O
_C
S
CE _EN
RE
TE
DD
UR SS
BY
d)
ve
_A
SO RE
K_
er
AC
AS
D
s
AD
(re
M
M
31 30 29 24 23 16 15 0
ADDRESS_ENABLE4 When this bit is set, the address filter module uses the fifth MAC address for
perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
(R/W)
SOURCE_ADDRESS4 When this bit is set, the EMACADDR4[47:0] is used to compare with the SA
fields of the received frame. When this bit is reset, the EMACADDR4[47:0] is used to compare with
the DA fields of the received frame. (R/W)
MASK_BYTE_CONTROL4 These bits are mask control bits for comparison of each of the
EMACADDR4 bytes. When set high, the MAC does not compare the corresponding byte of re-
ceived DA or SA with the contents of EMACADDR4 registers. Each bit controls the masking of the
bytes as follows:
You can filter a group of addresses (known as group address filtering) by masking one or more
bytes of the address. (R/W)
MAC_ADDRESS4_HI This field contains the upper 16 bits, Bits[47:32] of the fifth 6-byte MAC ad-
dress. (R/W)
31 0
0x0FFFFFFFF Reset
EMACADDR4LOW_REG This field contains the lower 32 bits of the fifth 6-byte MAC address. The
content of this field is undefined, so the register needs to be configured after the initialization pro-
cess. (R/W)
L5
RO
5
RE 5
I
SS
_H
NT
DD LE
S5
_A AB
O
_C
S
CE _EN
RE
TE
DD
UR SS
BY
d)
ve
_A
SO RE
K_
er
AC
AS
D
s
AD
(re
M
M
31 30 29 24 23 16 15 0
ADDRESS_ENABLE5 When this bit is set, the address filter module uses the sixth MAC address for
perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
(R/W)
SOURCE_ADDRESS5 When this bit is set, the EMACADDR5[47:0] is used to compare with the SA
fields of the received frame. When this bit is reset, the EMACADDR5[47:0] is used to compare with
the DA fields of the received frame. (R/W)
MASK_BYTE_CONTROL5 These bits are mask control bits for comparison of each of the
EMACADDR5 bytes. When set high, the MAC does not compare the corresponding byte of re-
ceived DA or SA with the contents of EMACADDR5 registers. Each bit controls the masking of the
bytes as follows:
You can filter a group of addresses (known as group address filtering) by masking one or more
bytes of the address. (R/W)
MAC_ADDRESS5_HI This field contains the upper 16 bits, Bits[47:32] of the sixth 6-byte MAC ad-
dress. (R/W)
31 0
0x0FFFFFFFF Reset
EMACADDR5LOW_REG This field contains the lower 32 bits of the sixth 6-byte MAC address. The
content of this field is undefined, so the register needs to be configured after the initialization pro-
cess. (R/W)
L6
RO
6
RE 6
I
SS
_H
NT
DD LE
S6
_A AB
O
_C
S
CE _EN
RE
TE
DD
UR SS
BY
d)
ve
_A
SO RE
K_
er
AC
AS
D
s
AD
(re
M
M
31 30 29 24 23 16 15 0
ADDRESS_ENABLE6 When this bit is set, the address filter module uses the seventh MAC address
for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
(R/W)
SOURCE_ADDRESS6 When this bit is set, the EMACADDR6[47:0] is used to compare with the SA
fields of the received frame. When this bit is reset, the EMACADDR6[47:0] is used to compare with
the DA fields of the received frame. (R/W)
MASK_BYTE_CONTROL6 These bits are mask control bits for comparison of each of the
EMACADDR6 bytes. When set high, the MAC does not compare the corresponding byte of re-
ceived DA or SA with the contents of EMACADDR6 registers. Each bit controls the masking of the
bytes as follows:
You can filter a group of addresses (known as group address filtering) by masking one or more
bytes of the address. (R/W)
MAC_ADDRESS6_HI This field contains the upper 16 bits, Bits[47:32] of the seventh 6-byte MAC
address. (R/W)
31 0
0x0FFFFFFFF Reset
EMACADDR6LOW_REG This field contains the lower 32 bits of the seventh 6-byte MAC address.
The content of this field is undefined, so the register needs to be configured after the initialization
process. (R/W)
L7
RO
7
RE 7
I
SS
_H
NT
DD LE
S7
_A AB
O
_C
S
CE _EN
RE
TE
DD
UR SS
BY
d)
ve
_A
SO RE
K_
er
AC
AS
D
s
AD
(re
M
M
31 30 29 24 23 16 15 0
ADDRESS_ENABLE7 When this bit is set, the address filter module uses the eighth MAC address
for perfect filtering. When this bit is reset, the address filter module ignores the address for filtering.
(R/W)
SOURCE_ADDRESS7 When this bit is set, the EMACADDR7[47:0] is used to compare with the SA
fields of the received frame. When this bit is reset, the EMACADDR7[47:0] is used to compare with
the DA fields of the received frame. (R/W)
MASK_BYTE_CONTROL7 These bits are mask control bits for comparison of each of the
EMACADDR7 bytes. When set high, the MAC does not compare the corresponding byte of re-
ceived DA or SA with the contents of EMACADDR7 registers. Each bit controls the masking of the
bytes as follows:
You can filter a group of addresses (known as group address filtering) by masking one or more
bytes of the address. (R/W)
MAC_ADDRESS7_HI This field contains the upper 16 bits, Bits[47:32] of the eighth 6-byte MAC
address. (R/W)
31 0
0x0FFFFFFFF Reset
EMACADDR7LOW_REG This field contains the lower 32 bits of the eighth 6-byte MAC address.
The content of this field is undefined, so the register needs to be configured after the initialization
process. (R/W)
)
UT
NK ) EO
ed M
_M D
DE
rv TI
NK EE
se R_
)
O
S
ed
ed
P
RX
(re BE
_S
v
rv
er
ID
se
AB
s
SM
(re
(re
(J
LI
LI
31 17 16 15 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
JABBER_TIMEOUT This bit indicates whether there is jabber timeout error (1’b1) in the received
frame. (RO)
LINK_SPEED This bit indicates the current speed of the link: (RO)
• 2’b01: 25 MHz.
LINK_MODE This bit indicates the current mode of operation of the link: (RO)
TO
)
)
(re GE
ed
ed
G
rv
rv
DO
DO
se
PW
(re
31 17 16 15 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Reset
PWDOGEN When this bit is set and Bit[23] (WD) of EMACCONFIG_REG is reset, the WTO field
(Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watch-
dog timeout for a received frame is controlled by the setting of Bit[23] (WD) and Bit[20] (JE) in
EMACCONFIG_REG. (R/W)
WDOGTO When Bit[16] (PWE) is set and Bit[23] (WD) of EMACCONFIG_REG is reset, this field is used
as watchdog timeout for a received frame. If the length of a received frame exceeds the value of
this field, such frame is terminated and declared as an error frame. (R/W)
UM
UM
_N
V
_N
DI
V
H_
DI
_
_
UT
UT
_O
_O
LK
LK
)
ed
_C
_C
rv
AC
AC
se
EM
EM
(re
31 8 7 4 3 0
EMAC_CLK_OUT_H_DIV_NUM RMII CLK using internal PLLA CLK, the half divider number, when
using RMII PHY. (R/W)
EMAC_CLK_OUT_DIV_NUM RMII CLK using internal PLLA CLK, the whole divider number, when
using RMII PHY. (R/W)
0M
00
0M
_1
_1
00
UM
UM
_1
_1
M
UM
L
_N
_N
E
U
_S
IV
_N
IV
_N
LK
_D
_D
IV
IV
_C
_H
_H
_D
_D
SC
SC
SC
SC
SC
)
_O
_O
_O
_O
_O
ed
rv
AC
AC
AC
AC
AC
se
EM
EM
EM
EM
EM
(re
31 25 24 23 18 17 12 11 6 5 0
0 0 0 0 0 0 0 0 0 1 9 19 Reset
EMAC_OSC_CLK_SEL Ethernet work using external PHY output clock or not for RMII CLK, when
using RMII PHY. When this bit is set to 1, external PHY CLK is used. When this bit is set to 0, PLLA
CLK is used. (R/W)
EM C_ ) K_T _EN
EN
N
SC N
X_
A d L X
_E
_O _E
EM rve II_C _R
XT SC
s e M LK
_E _O
(re C_ II_C
AC INT
d)
EM C_ )
A M
A d
ve
EM rve
er
se
s
(re
(re
31 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EL
_S
N TF
_I
HY
)
)
ed
ed
_P
rv
rv
AC
se
se
EM
(re
31 16 15 13 12 (re 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EMAC_PHY_INTF_SEL The PHY interface selected. 0x0: PHY MII, 0x4: PHY RMII. (R/W)
_R
e
rv
AC
se
EM
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EMAC_RAM_PD_EN Ethernet RAM power-down enable signal. Bit[0]: TX SRAM; Bit[1]: RX SRAM.
Setting the bit to 1 powers down the RAM. (R/W)
11.1 Overview
An I2 C (Inter-Integrated Circuit) bus can be used for communication with several external devices connected to
the same bus as ESP32. The ESP32 has dedicated hardware to communicate with peripherals on the I2 C
bus.
11.2 Features
The I2 C controller has the following features:
• Supports continuous data transmission with disabled Serial Clock Line (SCL)
Communication starts when a master sends out a start condition: it will pull the SDA line low, and will then pull
the SCL line high. It will send out nine clock pulses over the SCL line. The first eight pulses are used to shift out a
byte consisting of a 7-bit address and a read/write bit. If a slave with this address is active on the bus, the slave
can answer by pulling the SDA low on the ninth clock pulse. The master can then send out more 9-bit clock
pulse clusters and, depending on the read/write bit sent, the device or the master will shift out data on the SDA
line, with the other side acknowledging the transfer by pulling the SDA low on the ninth clock pulse. During data
transfer, the SDA line changes only when the SCL line is low. When the master has finished the communication, it
will send a stop condition on the bus by raising SDA, while SCL will already be high.
The ESP32 I2 C peripheral can handle the I2 C protocol, freeing up the processor cores for other tasks.
11.3.2 Architecture
An I2 C controller can operate either in master mode or slave mode. The I2C_MS_MODE register is used to select
the mode. Figure 49 shows the I2 C Master architecture, while Figure 50 shows the I2 C Slave architecture.
• RAM, the size of which is 32 x 8 bits, and it is directly mapped onto the address space of the CPU cores,
starting at address REG_I2C_BASE+0x100. Each byte of I2 C data is stored in a 32-bit word of memory
(so, the first byte is at +0x100, the second byte at +0x104, the third byte at +0x108, etc.) Users need to
set register I2C_NONFIFO_EN.
• A CMD_Controller and 16 command registers (cmd0 ~ cmd15), which are used by the I2 C Master to
control data transmission. One command at a time is executed by the I2 C controller.
• SCL_FSM: A state machine that controls the SCL clock. The I2C_SCL_HIGH_PERIOD_REG and
I2C_SCL_LOW_PERIOD_REG registers are used to configure the frequency and duty cycle of the signal on
the SCL line.
• DATA_Shifter which converts the byte data to an outgoing bitstream, or converts an incoming bitstream to
byte data. I2C_RX_LSB_FIRST and I2C_TX_LSB_FIRST can be used for configuring whether the LSB or
• SCL_Filter and SDA_Filter: Input noise filter for the I2C_Slave. The filter can be enabled or disabled by
configuring I2C_SCL_FILTER_EN and I2C_SDA_FILTER_EN. The filter can remove line glitches with pulse
width less than I2C_SCL_FILTER_THRES and I2C_SDA_FILTER_THRES ABP clock cycles.
Figure 51 is an I2 C sequence chart. When the I2 C controller works in master mode, SCL is an output signal. In
contrast, when the I2 C controller works in slave mode, the SCL becomes an input signal. The values assigned to
I2C_SDA_HOLD_REG and I2C_SDA_SAMPLE_REG are still valid in slave mode. Users need to configure the
values of I2C_SDA_HOLD_TIME and I2C_SDA_SAMPLE_TIME, according to the host characteristics, for the I2 C
slave to receive data properly. Table 55 shows available settings of SCL low and high level cycles when SCL is
configured to direct output mode. The settings determine the SCL output frequency fscl .
80 MHz
fscl =
SCL_Low_Level_Cycles + SCL_High_Level_Cycles
According to the I2 C protocol, each transmission of data begins with a START condition and ends with a STOP
condition. Data is transmitted by one byte at a time, and each byte has an ACK bit. The receiver informs the
transmitter to continue transmission by pulling down SDA, which indicates an ACK. The receiver can also
indicate it wants to stop further transmission by pulling up the SDA line, thereby not indicating an ACK.
Figure 51 also shows the registers that can configure the START bit, STOP bit, SDA hold time, and SDA sample
time.
Notice: If the I2 C pads are configured in open-drain mode, it will take longer for the signal lines to transition from
a low level to a high level. The transition duration is determined together by the pull-up resistor and capacitor.
The output frequency of SCL is relatively low in open-drain mode.
CMD_DONE: The CMD_DONE bit of every command can be read by software to tell if the command has been
handled by hardware.
op_code: op_code is used to indicate the command. The I2 C controller supports four commands:
• RSTART: op_code = 0 is the RSTART command to control the transmission of a START or RESTART I2 C
condition.
• WRITE: op_code = 1 is the WRITE command for the I2 C Master to transmit data.
• READ: op_code = 2 is the READ command for the I2 C Master to receive data.
• STOP: op_code = 3 is the STOP command to control the transmission of a STOP I2 C condition.
• END: op_code = 4 is the END command for continuous data transmission. When the END command is
given, SCL is temporarily disabled to allow software to reload the command and data registers for
subsequent events before resuming. Transmission will then continue seamlessly.
A complete data transmission process begins with an RSTART command, and ends with a STOP
command.
ack_value: When receiving data, this bit is used to indicate whether the receiver will send an ACK after this byte
has been received.
ack_exp: This bit is to set an expected ACK value for the transmitter.
ack_check_en: When transmitting a byte, this bit enables checking the ACK value received against the ack_exp
value. Checking is enabled by 1, while 0 disables it.
byte_num: This register specifies the length of data (in bytes) to be read or written. The maximum length is 255,
while the minimum is 1. When the op_code is RSTART, STOP or END, this value is meaningless.
Figure 53 shows the I2 C Master writing N bytes of data to an I2 C Slave. According to the I2 C protocol, the first
byte is the Slave address. As shown in the diagram, the first byte of the RAM unit has been populated with the
Slave’s 7-bit address plus the 1-bit read/write flag. In this case, the flag is zero, indicating a write operation. The
rest of the RAM unit holds N bytes of data ready for transmission. The cmd unit has been populated with the
sequence of commands for the operation.
For the I2 C master to begin an operation, the bus must not be busy, i.e. the SCL line must not be pulled low by
another device on the I2 C bus. The I2 C operation can only begin when the SCL line is released (made high) to
indicate that the I2 C bus is free. After the cmd unit and data are prepared, I2C_TRANS_START bit in
I2C_CTR_REG must be set to begin the configured I2 C Master operation. The I2 C Master then initiates a START
condition on the bus and progresses to the WRITE command which will fetch N+1 bytes from RAM and send
them to the Slave. The first of these bytes is the address byte.
When the transmitted data size exceeds I2C_NONFIFO_TX_THRES, an I2C_TX_SEND_EMPTY_INT interrupt will
be generated. After detecting the interrupt, software can read TXFIFO_END_ADDR in register RXFIFO_ST_REG,
get the last address of the data in the RAM and refresh the old data in the RAM. TXFIFO_END_ADDR will be
refreshed each time interrupt I2C_TX_SEND_EMPTY_INT or I2C_TRANS_COMPLETE_INT occurs.
When ack_check_en is set to 1, the Master will check the ACK value each time it sends a data byte. If the ACK
value received does not match ack_exp (the expected ACK value) in the WRITE command, then the Master will
generate an I2C_ACK_ERR_INT interrupt and stop the transmission.
During transmission, when the SCL is high, if the input value and output value of SDA do not match, then the
Master will generate an I2C_ARBITRATION_LOST_INT interrupt. When the transmission is finished, the Master
will generate an I2C_TRANS_COMPLETE_INT interrupt.
After detecting the START bit sent from the Master, the Slave will start receiving the address and comparing it to
its own. If the address does not match I2C_SLAVE_ADDR, then the Slave will ignore the rest of the transmission.
If they do match, the Slave will store the rest of the data into RAM in the receiving order. When the data size
exceeds I2C_NONFIFO_RX_THRES, an I2C_RX_REC_FULL_INT interrupt is generated. After detecting the
interrupt, software will get the starting and ending addresses in the RAM by reading RXFIFO_START_ADDR and
RXFIFO_END_ADDR bits in register RXFIFO_ST_REG, and fetch the data for further processing. Register
RXFIFO_START_ADDR is refreshed only once during each transmission, while RXFIFO_END_ADDR gets
refreshed every time when either I2C_RX_REC_FULL_INT or I2C_TRANS_COMPLETE_INT interrupt is
generated.
When the END command is not used, the I2 C master can transmit up to (14*255-1) bytes of valid data, and the
cmd unit is populated with RSTART + 14 WRITE + 1 STOP.
• If the Master fails to send a STOP bit, because the SDA is pulled low by other devices, then the Master
needs to be reset.
• If the Master fails to send a START bit, because the SDA or SCL is pulled low by other devices, then the
Master needs to be reset. It is recommended that the software uses a timeout period to implement the
reset.
• If the SDA is pulled low by the Slave during transmission, the Master can simply release it by sending it nine
SCL clock signals at the most.
It is important to note that the behaviour of another I2 C master or slave device on the bus may not always be
similar to that of the ESP32 I2 C peripheral in the master- or slave-mode operation described above. Please
consult the datasheets of the respective I2 C devices to ensure proper operation under all bus conditions.
The ESP32 I2 C controller uses 7-bit addressing by default. However, 10-bit addressing can also be used. In the
master, this is done by sending a second I2 C address byte after the first address byte. In the slave, the
I2C_SLAVE_ADDR_10BIT_EN bit in I2C_SLAVE_ADDR_REG can be set to activate a 10-bit addressing mode.
I2C_SLAVE_ADDR is used to configure the I2 C Slave address, as per usual. Figure 54 shows the equivalent of
I2 C Master operation writing N-bytes of data to an I2 C Slave with a 10-bit address. Since 10-bit Slave addresses
require an extra address byte, both the byte_num field of the WRITE command and the number of total bytes in
RAM increase by one.
When the END command is not used, the I2 C master can transmit up to (14*255-2) bytes of valid data to Slave
with 10-bit address.
One way many I2 C Slave devices are designed is by exposing a register block containing various settings. The
I2 C Master can write one or more of these registers by sending the Slave a register address. The ESP32 I2 C
Slave controller has hardware support for such a scheme.
Specifically, on the Slave, I2C_FIFO_ADDR_CFG_EN can be set so that the I2 C Master can write to a specified
register address inside the I2 C Slave memory block. Figure 55 shows the Master writing N-bytes of data byte0 ~
byte(N-1) from the RAM unit to register address M (determined by addrM in RAM unit) with the Slave. In this
mode, Slave can receive up to 32 bytes of valid data. When Master needs to transmit extra amount of data,
segmented transmission can be enabled.
Figure 55: I2 C Master Writes to addrM in RAM of Slave with 7-bit Address
If the data size exceeds the capacity of a 14-byte read/write cmd, the END command can be called to enable
segmented transmission. Figure 56 shows the Master writing data to the Slave, in three segments. The first
segment shows the configuration of the Master’s commands and the preparation of data in the RAM unit. When
the I2C_TRANS_START bit is enabled, the Master starts transmission. After executing the END command, the
Master will turn off the SCL clock and pull the SCL low to reserve the bus and prevent any other device from
transacting on the bus. The controller will generate an I2C_END_DETECT_INT interrupt to notify the
software.
Figure 56: Master Writes to Slave with 7-bit Address in Three Segments
After detecting an I2C_END_DETECT_INT interrupt, the software can refresh the contents of the cmd and RAM
blocks, as shown in the second segment. Subsequently, it should clear the I2C_END_DETECT_INT interrupt and
resume the transaction by setting the I2C_TRANS_START bit. To stop the transaction, it should configure the
cmd, as the third segment shows, and enable the I2C_TRANS_START bit to generate a STOP bit, after detecting
the I2C_END_DETECT_INT interrupt.
Please note that the other masters on the bus will be starved of bus time between two segments. The bus is only
released after a STOP signal is sent.
Note: When there are more than three segments, the address of an END command in the cmd should not be
altered into another command by the next segment.
Figure 57 shows the Master reading N-bytes of data from an Slave with a 7-bit address. At first, the Master
needs to send the address of the Slave, so cmd1 is a WRITE command. The byte that this command sends is
the slave address plus the R/W flag, which in this case is 1 and, therefore, indicates that this is going to be a read
operation. The Slave starts to send data to the Master if the addresses match. The Master will return ACK,
according to the ack_value in the READ command, upon receiving every byte. As can be seen from Figure 57,
READ is divided into two segments. The Master replies ACK to N-1 bytes in cmd2 and does not reply ACK to the
single byte READ command in cmd3, i.e., the last transmitted data. Users can configure it as they wish.
When storing the received data, Master will start from the first address in RAM. Byte0 (Slave address + 1-bit R/W
marker bit) will be overwritten.
When the END command is not used, the Master can transmit up to (13*255) bytes of valid data. The cmd unit is
populated with RSTART + 1 WRITE + 13 READ + 1 STOP.
Figure 58 shows the Master reading data from a slave with a 10-bit address. This mode can be enabled by
setting I2C_SLAVE_ADDR_10BIT_EN bit and preparing data to be sent in the slave RAM. In the Master, two
bytes of RAM are used for a 10-bit address. Finally, the I2C _TRANS_START bit must be set to enable one
transaction.
Figure 59 shows the Master reading data from a specified address in the Slave. This mode can be enabled by
setting I2C_FIFO_ADDR_CFG_EN and preparing the data to be read by the master in the Slave RAM block.
Subsequently, the address of the Slave and the address of the specified register (that is, M) have to be
determined by the master. Finally, the I2C_TRANS_START bit must be set in the Master to initiate the read
operation, following which the Slave will fetch N bytes of data from RAM and send them to the Master.
Figure 59: Master Reads N Bytes of Data from addrM in Slave with 7-bit Address
Figure 60 shows the Master reading N+M bytes of data in three segments from the Slave. The first segment
shows the configuration of the cmd and the preparation of data in the Slave RAM. When the I2C_TRANS_START
bit is enabled, the Master starts the operation. The Master will refresh the cmd after executing the END
command. It will clear the I2C_END_DETECT_INT interrupt, set the I2C_TRANS_START bit and resume the
transaction. To stop the transaction, the Master will configure the cmd, as the third segment shows, after
detecting the I2C_END_DETECT_INT interrupt. After setting the I2C_TRANS_START bit, Master will send a
STOP bit to stop the transaction.
Figure 60: Master Reads from Slave with 7-bit Address in Three Segments
11.3.7 Interrupts
• I2C_TX_SEND_EMPTY_INT: Triggered when the has sent nonfifo_tx_thres bytes of data.
• I2C_ACK_ERR_INT: Triggered when the Master receives an ACK that is not as expected, or when the Slave
receives an ACK whose value is 1.
• I2C_TIME_OUT_INT: Triggered when the SCL stays high or low for more than I2C_TIME_OUT clocks.
• I2C_ARBITRATION_LOST_INT: Triggered when the Master’s SCL is high, while the output value and input
value of the SDA do not match.
11.5 Registers
D
IO
ER
_P
W
LO
L_
)
ed
SC
rv
se
C_
(re
I2
31 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SCL_LOW_PERIOD This register is used to configure for how long SCL remains low in master
mode, in APB clock cycles. (R/W)
E_ UT L
RC _O VE
UT
FO E LE
O
A_ RC L_
C_ A _F T
C_ d D T
se _M ST T
I2 TR SB IRS
I2 rve O AR
(re MS S_ IRS
SD _FO SC
I2 SA ) E
C_ _L _F
C_ L _
I2 SC PLE
I2 TX SB
N
C_ _L
)
C_ M
d
ve
I2 RX
r
se
C_
(re
31 8
I2
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Reset
I2C_RX_LSB_FIRST This bit is used to control the storage mode for received data. (R/W)
1: receive data from the least significant bit;
0: receive data from the most significant bit.
I2C_TX_LSB_FIRST This bit is used to control the sending mode for data needing to be sent. (R/W)
1: send data from the least significant bit;
0: send data from the most significant bit.
I2C_TRANS_START Set this bit to start sending the data in txfifo. (R/W)
I2C_MS_MODE Set this bit to configure the module as an I2 C Master. Clear this bit to configure the
module as an I2 C Slave. (R/W)
I2C_SAMPLE_SCL_LEVEL 1: sample SDA data on the SCL low level; 0: sample SDA data on the
SCL high level. (R/W)
T
AS
ED
_L
TE
T
I2 TIM _LO Y SS
AS
TA
C_ B S E
_L
I2 BU E_ NS
I2 R BU DR
_S
NT
NT
E
K_ RW
I2 SL _O T
A
N
C_ S AD
AC E_ T
AT
_C
C
_C
C_ E S
C_ AV R
C_ AV U
AI
RE
ST
I2 SL _T
O
_M
FO
IF
_
E
L_
)
d)
I2 BY )
ed
ed
C_ d
FI
CL
C_ T
XF
ve
I2 rve
SC
TX
rv
rv
R
S
A
er
se
se
se
C_
C_
C_
C_
s
(re
(re
(re
(re
I2
I2
I2
I2
31 30 28 27 26 24 23 18 17 14 13 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SCL_STATE_LAST This field indicates the states of the state machine used to produce SCL.
(RO)
0: Idle; 1: Start; 2: Negative edge; 3: Low; 4: Positive edge; 5: High; 6: Stop
I2C_SCL_MAIN_STATE_LAST This field indicates the states of the I2 C module state machine. (RO)
0: Idle; 1: Address shift; 2: ACK address; 3: Rx data; 4: Tx data; 5: Send ACK; 6: Wait ACK
I2C_TXFIFO_CNT This field stores the amount of received data in RAM. (RO)
I2C_RXFIFO_CNT This field represents the amount of data needed to be sent. (RO)
I2C_SLAVE_ADDRESSED When configured as an I2 C Slave, and the address sent by the master is
equal to the address of the slave, then this bit will be of high level. (RO)
I2C_BUS_BUSY 1: the I2 C bus is busy transferring data; 0: the I2 C bus is in idle state. (RO)
I2C_ARB_LOST When the I2 C controller loses control of SCL line, this register changes to 1. (RO)
I2C_TIME_OUT When the I2 C controller takes more than I2C_TIME_OUT clocks to receive a data bit,
this field changes to 1. (RO)
I2C_SLAVE_RW When in slave mode, 1: master reads from slave; 0: master writes to slave. (RO)
I2C_ACK_REC This register stores the value of the received ACK bit. (RO)
M
e
rv
TI
se
C_
(re
I2
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_TIME_OUT_REG This register is used to configure the timeout for receiving a data bit in APB
clock cycles. (R/W)
EN
T_
BI
10
R_
R
DD
DD
_A
_A
VE
VE
d)
LA
LA
ve
S
S
er
C_
C_
s
(re
I2
I2
31 30 15 14 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SLAVE_ADDR_10BIT_EN This field is used to enable the slave 10-bit addressing mode in master
mode. (R/W)
I2C_SLAVE_ADDR When configured as an I2 C Slave, this field is used to configure the slave address.
(R/W)
DR
DR
AD
AD
T_
D_
DR
R
TA
R
N
AD
DD
_S
_E
T_
O
_A
IF
IF
R
ND
TA
XF
XF
_S
_E
_T
_T
O
FO
IF
IF
d)
FI
FI
XF
XF
e
RX
X
rv
_R
_R
_R
se
C_
C
C
(re
I2
I2
I2
I2
31 20 19 15 14 10 9 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_TXFIFO_END_ADDR This is the offset address of the last sent data, as described
in nonfifo_tx_thres register. The value refreshes when I2C_TX_SEND_EMPTY_INT or
I2C_TRANS_COMPLETE_INT interrupt is generated. (RO)
I2C_TXFIFO_START_ADDR This is the offset address of the first sent data, as described in non-
fifo_tx_thres register. (RO)
I2C_RXFIFO_END_ADDR This is the offset address of the last received data, as de-
scribed in nonfifo_rx_thres_register. This value refreshes when I2C_RX_REC_FULL_INT or
I2C_TRANS_COMPLETE_INT interrupt is generated. (RO)
I2C_RXFIFO_START_ADDR This is the offset address of the last received data, as described in non-
fifo_rx_thres_register. (RO)
N
S
RE
RE
_E
TH
_E G
TH
O CF
X_
X_
N
IF R_
_R
_T
NF DD
O
O
IF
IF
NO _A
NF
NF
d)
)
C_ O
ed
NO
O
ve
I2 FIF
rv
_N
er
se
C_
C_
s
C
(re
(re
I2
I2
I2
31 26 25 20 19 14 13 12 11 10
I2C_NONFIFO_TX_THRES When I2 C sends more than nonfifo_tx_thres bytes of data, it will generate
a tx_send_empty_int_raw interrupt and update the current offset address of the sent data. (R/W)
I2C_NONFIFO_RX_THRES When I2 C receives more than nonfifo_rx_thres bytes of data, it will gen-
erate a rx_send_full_int_raw interrupt and update the current offset address of the received data.
(R/W)
I2C_FIFO_ADDR_CFG_EN When this bit is set to 1, the byte received after the I2 C address byte
represents the offset address in the I2 C Slave RAM. (R/W)
AW RA AW
W
_I ST_ _IN W
_R T_ _R
CT O P RA
I2 TR _O TAR RA RA AW
NT IN T
TE N_L OM T_
C_ B _ P W W
C_ A U T W W
C_ E S T T_ R
I2 TIM S_ _IN _IN T_
I2 R TER OM _RA RA
DE IO _C IN
N
D_ AT AN TE_
C_ S C T T_
C_ A R L _I
I2 MA S_ _IN _IN
I2 TR _ER FUL TY
EN ITR TR LE
_
C_ K _ P
I2 AC EC _EM
N T
C_ _R D
I2 RX EN
N
C_ _S
)
ed
I2 TX
rv
A
se
C_
(re
I2
31 13 12 11 10 9 8 7 6 5 3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_RX_REC_FULL_INT_RAW The raw interrupt status bit for the I2C_RX_REC_FULL_INT interrupt.
(RO)
I2C_ACK_ERR_INT_RAW The raw interrupt status bit for the I2C_ACK_ERR_INT interrupt. (RO)
I2C_TRANS_START_INT_RAW The raw interrupt status bit for the I2C_TRANS_START_INT interrupt.
(RO)
I2C_TIME_OUT_INT_RAW The raw interrupt status bit for the I2C_TIME_OUT_INT interrupt. (RO)
I2C_END_DETECT_INT_RAW The raw interrupt status bit for the I2C_END_DETECT_INT interrupt.
(RO)
LR CL LR
_C T_ _C
R
_I ST_ _IN R
CT O P CL
I2 TR _O TAR CL CL LR
NT IN T
TE N_L OM T_
C _ E S T T_ C
C_ B _ P R R
C_ A U T R R
I2 TIM S_ _IN _IN T_
I2 R TER OM _CL CL
DE IO _C IN
N
D_ AT AN TE_
C_ S C T T_
C_ A R L _I
I2 MA S_ _IN _IN
I2 TR _ER FUL TY
EN ITR TR LE
_
C_ K _ P
I2 AC EC _EM
N T
C_ _R D
I2 RX EN
N
C_ _S
)
ed
I2 TX
rv
A
se
C_
(re
I2
31 13 12 11 10 9 8 7 6 5 3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
NA EN NA
A
_E T_ _E
_I ST_ _IN A
CT O P EN
I2 TR _O TAR EN EN A
NT IN T
N
TE N_L OM T_
C_ B _ P A A
C _ E S T T_ E
C_ A U T A A
I2 TIM S_ _IN _IN T_
I2 R TER OM _EN EN
DE IO _C IN
N
D_ AT AN TE_
C_ S C T T_
C_ A R L _I
I2 MA S_ _IN _IN
I2 TR _ER FUL TY
EN ITR TR LE
_
C_ K _ P
I2 AC EC _EM
N T
C_ _R D
I2 RX EN
N
C_ _S
)
ed
I2 TX
rv
A
se
C_
(re
I2
31 13 12 11 10 9 8 7 6 5 3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_ACK_ERR_INT_ENA The interrupt enable bit for the I2C_ACK_ERR_INT interrupt. (R/W)
I2C_TIME_OUT_INT_ENA The interrupt enable bit for the I2C_TIME_OUT_INT interrupt. (R/W)
I2C_END_DETECT_INT_ENA The interrupt enable bit for the I2C_END_DETECT_INT interrupt. (R/W)
T ST T
_S T_ _S
CT O P ST
NT IN T
_I ST_ _IN
T
TE N_L OM T_
C_ E S T T_ S
I2 TIM S_ _IN _IN T_
I2 R TER OM _ST ST
DE IO _C IN
I2 TR _O TAR ST ST
N
D_ AT AN TE_
C_ S C T T_
C_ A R L _I
I2 MA S_ _IN _IN
I2 TR _ER FUL TY
EN ITR TR LE
_
C_ K _ P
C_ A U T
C_ B _ P
I2 AC EC _EM
N T
C_ _R D
I2 RX EN
N
C_ _S
)
ed
I2 TX
rv
A
se
C_
(re
I2
31 13 12 11 10 9 8 7 6 5 3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_RX_REC_FULL_INT_ST The masked interrupt status bit for the I2C_RX_REC_FULL_INT inter-
rupt. (RO)
I2C_ACK_ERR_INT_ST The masked interrupt status bit for the I2C_ACK_ERR_INT interrupt. (RO)
I2C_TRANS_START_INT_ST The masked interrupt status bit for the I2C_TRANS_START_INT inter-
rupt. (RO)
I2C_TIME_OUT_INT_ST The masked interrupt status bit for the I2C_TIME_OUT_INT interrupt. (RO)
I2C_END_DETECT_INT_ST The masked interrupt status bit for the I2C_END_DETECT_INT interrupt.
(RO)
SD
rv
se
C_
(re
I2
31 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SDA_HOLD_TIME This register is used to configure the time to hold the data after the negative
edge of SCL, in APB clock cycles. (R/W)
E
M
TI
E_
PL
M
_SA
d)
DA
ve
S
er
C_
s
(re
I2
31 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SDA_SAMPLE_TIME This register is used to configure for how long SDA is sampled, in APB
clock cycles. (R/W)
D
O
RI
PE
H_
G
HI
L_
d)
ve
SC
r
se
C_
(re
I2
31 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SCL_HIGH_PERIOD This register is used to configure for how long SCL remains high in master
mode, in APB clock cycles. (R/W)
E
M
TI
_
LD
O
H
T_
AR
ST
L_
ed)
SC
rv
se
C_
(re
I2
31 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset
I2C_SCL_START_HOLD_TIME This register is used to configure the time between the negative edge
of SDA and the negative edge of SCL for a START condition, in APB clock cycles. (R/W)
E
M
TI
P_
TU
SE
T_
AR
ST
_R
)
ed
CL
rv
S
se
C_
(re
I2
31 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset
I2C_SCL_RSTART_SETUP_TIME This register is used to configure the time between the positive
edge of SCL and the negative edge of SDA for a RESTART condition, in APB clock cycles. (R/W)
E
IM
_T
LD
HO
P_
O
ST
L_
)
ed
SC
rv
se
C_
(re
I2
31 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SCL_STOP_HOLD_TIME This register is used to configure the delay after the STOP condition,
in APB clock cycles. (R/W)
SC
rv
se
C_
(re
I2
31 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_SCL_STOP_SETUP_TIME This register is used to configure the time between the positive edge
of SCL and the positive edge of SDA, in APB clock cycles. (R/W)
ES
HR
N
_E
_T
ER
ER
LT
LT
FI
FI
L_
L_
)
ed
SC
SC
rv
se
C_
C_
(re
I2
I2
31 4 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset
I2C_SCL_FILTER_THRES When a pulse on the SCL input has smaller width than this register value
in APB clock cycles, the I2 C controller will ignore that pulse. (R/W)
ES
HR
EN
_T
R_
ER
E
LT
LT
FI
FI
A_
A_
ed)
SD
SD
rv
se
C_
C_
(re
I2
I2
31 4 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 Reset
I2C_SDA_FILTER_THRES When a pulse on the SDA input has smaller width than this register value
in APB clock cycles, the I2 C controller will ignore that pulse. (R/W)
Dn
AN
AN
M
M
M
M
)
ed
CO
CO
rv
se
C_
C_
(re
I2
I2
31 30 14 13 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2C_COMMANDn_DONE When command n is done in I2 C Master mode, this bit changes to high
level. (R/W)
12. I²S
12.1 Overview
The I²S bus provides a flexible communication interface for streaming digital data in multimedia applications,
especially digital audio applications. The ESP32 includes two I²S interfaces: I2S0 and I2S1.
The I²S standard bus defines three signals: a clock signal, a channel selection signal, and a serial data signal. A
basic I²S data bus has one master and one slave. The roles remain unchanged throughout the communication.
The I²S modules on the ESP32 provide separate transmit and receive channels for high performance.
Figure 61 is the system block diagram of the ESP32 I²S module. In the figure above, the value of ”n” can be
either 0 or 1. There are two independent I²S modules embedded in ESP32, namely I2S0 and I2S1. Each I²S
module contains a Tx (transmit) unit and a Rx (receive) unit. Both the Tx unit and the Rx unit have a three-wire
interface that includes a clock line, a channel selection line and a serial data line. The serial data line of the Tx unit
is fixed as output, and the serial data line of the Rx unit is fixed as input. The clock line and the channel selection
line of the Tx and Rx units can be configured to both master transmitting mode and slave receiving mode. In the
LCD mode, the serial data line extends to the parallel data bus. Both the Tx unit and the Rx unit have a
32-bit-wide FIFO with a depth of 64. Besides, only I2S0 supports on-chip DAC/ADC modes, as well as receiving
and transmitting PDM signals.
The right side of Figure 61 shows the signal bus of the I²S module. The signal naming rule of the Rx and Tx units
is I²SnA_B_C, where ”n” stands for either I2S0 or I2S1; ”A” represents the direction of I²S module’s data bus
signal, ”I” represents input, ”O” represents output; ”B” represents signal function; ”C” represents the signal
direction, ”in” means that the signal is input into the I²S module, while ”out” means that the I²S module outputs
the signal. For a detailed description of the I²S signal bus, please refer to Table 57.
Table 57 describes the signal bus of the I²S module. Except for the I2Sn_CLK signal, all other signals are mapped
to the chip pin via the GPIO matrix and IO MUX. The I2Sn_CLK signal is mapped to the chip pin via the IO_MUX.
For details, please refer to the chapter about IO_MUX and the GPIO Matrix.
Note:
Assume that the bit width of the input/output signal is N, the input signal should be configured to I2SnI_Data_in[N-1:0],
and the output signal to I2SnO_Data_out[23:23-N+1]. Generally, for input signals, N=8 or 16; while for output signals,
N=8, 16 or 24 (note that I2S1 does not support 24-bit width).
12.2 Features
I²S mode
LCD mode
I²S interrupts
Notice:
• When using PLL_D2_CLK as the clock source, it is not recommended to divide it using decimals. For high
performance audio applications, the analog PLL output clock source APLL_CLK must be used to acquire
highly accurate I2Sn_CLK and BCK. For further details, please refer to the chapter entitled Reset and Clock.
• When ESP32 I²S works in slave mode, the master must use I2Sn_CLK as the master clock and fi2s >= 8 *
fBCK .
The relation between I2Sn_CLK frequency fi2s and the divider clock source frequency fpll can be seen in the
equation below:
fpll
fi2s =
N + ba
”N”, whose value is >=2, corresponds to the REG _CLKM_DIV_NUM [7:0] bits of register
I2S_CLKM_CONF_REG , ”b” is the I2S_CLKM_DIV_B[5:0] bit and ”a” is the I2S_CLKM_DIV_A[5:0] bit.
In master mode, the serial clock BCK in the I²S module is derived from I2Sn_CLK, that is:
fi2s
fBCK =
M
In master transmitting mode, ”M”, whose value is >=2, is the I2S_TX_BCK_DIV_NUM[5:0] bit of register
I2S_SAMPLE_RATE_CONF_REG. In master receiving mode, ”M” is the I2S_RX_BCK_DIV_NUM[5:0] bit of
register I2S_SAMPLE_RATE_CONF_REG.
As is shown in Figure 63, the Philips I²S bus specifications require that the WS signal starts to change a BCK
clock cycle earlier than the SD signal, which means that the WS signal takes effect a clock cycle before the first
bit of the current channel-data transmission, while the WS signal continues until the end of the current
channel-data transmission. The SD signal line transmits the most significant bit of audio data first. If the
I2S_RX_MSB_SHIFT bit and the I2S_TX_MSB_SHIFT bit of register I2S_CONF_REG are set to 1, respectively,
the I²S module will use the Philips standard when receiving and transmitting data.
The MSB alignment standard is shown in Figure 64. WS and SD signals both change simultaneously on the
falling edge of BCK under the MSB alignment standard. The WS signal continues until the end of the current
channel-data transmission, and the SD signal line transmits the most significant bit of audio data first. If the
I2S_RX_MSB_SHIFT and I2S_TX_MSB_SHIFT bits of register I2S_CONF_REG are cleared, the I²S module will
use the MSB alignment standard when receiving and transmitting data.
As is shown in Figure 65, under the short frame synchronization mode of the PCM standard, the WS signal starts
to change a BCK clock cycle earlier than the SD signal, which means that the WS signal takes effect a clock
cycle earlier than the first bit of the current channel-data transmission and continues for one extra BCK clock
cycle. The SD signal line transmits the most significant bit of audio data first. If the I2S_RX_SHORT_SYNC and
I2S_TX_SHORT_SYNC bits of register I2S_CONF_REG are set, the I²S module will receive and transmit data in
the short frame synchronization mode.
written into FIFO first and then read from FIFO. There are two approaches to accessing the FIFO; one is to
directly access the FIFO using a CPU, the other is to access the FIFO using a DMA controller.
When RX_LEN is greater than I2S_RX_DATA_NUM[5:0], the received data, which is buffered in FIFO, has
reached the set threshold and needs to be read out to prevent an overflow. When TX_LEN is less than
I2S_TX_DATA_NUM[5:0], the transmitted data, which is buffered in FIFO, has not reached the set threshold and
software can continue feeding data into FIFO.
I2S_TX_FIFO_MOD[2:0] Description
0 16-bit dual channel data
Tx FIFO mode0 2 32-bit dual channel data
3 32-bit single channel data
Tx FIFO mode1 1 16-bit single channel data
At the first stage, there are two modes for data to be sent and written into FIFO. In Tx FIFO mode0, the Tx
data-to-be-sent are written into FIFO according to the time order. In Tx FIFO mode1, the data-to-be-sent are
divided into 16 high- and 16 low-order bits. Then, both the 16 high- and 16 low-order bits are recomposed and
′
written into FIFO. The details are shown in Figure 66 with the corresponding registers listed in Table 58. Dn
′′
consists of 16 high-order bits of Dn and 16 zeros. Dn consists of 16 low-order bits of Dn and 16 zeros. That is
′ ′′
to say, Dn = {Dn [31 : 16], 16′ h0}, Dn = {Dn [15 : 0], 16′ h0}.
At the second stage, the system reads data that will be sent from FIFO, according to the relevant register
configuration. The mode in which the system reads data from FIFO is relevant to the configuration of
I2S_TX_FIFO_MOD[2.0] and I2S_TX_CHAN_MOD[2:0]. I2S_TX_FIFO_MOD[2.0] determines whether the data are
16-bit or 32-bit, as shown in Table 58, while I2S_TX_CHAN_MOD[2:0] determines the format of the
data-to-be-sent, as shown in Table 59.
I2S_TX_CHAN_MOD[2:0] Description
0 Dual channel mode
Mono mode
When I2S_TX_MSB_RIGHT equals 0, the left-channel data are ”holding”
1 their values and the right-channel data change into the left-channel data.
When I2S_TX_MSB_RIGHT equals 1, the right-channel data are ”holding”
their values and the left-channel data change into the right-channel data.
Mono mode
When I2S_TX_MSB_RIGHT equals 0, the right-channel data are ”holding”
2 their values and the left-channel data change into the right-channel data.
When I2S_TX_MSB_RIGHT equals 1, the left-channel data are ”holding”
their values and the right-channel data change into the left-channel data.
Mono mode
When I2S_TX_MSB_RIGHT equals 0, the left-channel data are constants
3 in the range of REG[31:0].
When I2S_TX_MSB_RIGHT equals 1, the right-channel data are constants
in the range of REG[31:0].
Mono mode
When I2S_TX_MSB_RIGHT equals 0, the right-channel data are constants
4 in the range of REG[31:0].
When I2S_TX_MSB_RIGHT equals 1, the left-channel data are constants
in the range of REG[31:0].
The output of the third stage is determined by the mode of the I²S and I2S_TX_BITS_MOD[5:0] bits of register
I2S_SAMPLE_RATE_CONF_REG.
• The input serial-bit stream is transformed into a 64-bit parallel-data stream in I²S mode. In LCD mode, the
input parallel-data stream will be extended to a 64-bit parallel-data stream.
• Data are read from FIFO by CPU/DMA and written into the internal memory.
At the first stage of receiving data, the received-data stream is expanded to a zero-padded parallel-data stream
with 32 high-order bits and 32 low-order bits, according to the level of the I2SnI_WS_out (or I2SnI_WS_in) signal.
The I2S_RX_MSB_RIGHT bit of register I2S_CONF_REG is used to determine how the data are to be
expanded.
For example, as is shown in Figure 67, if the width of serial data is 16 bits, when I2S_RX_RIGHT_FIRST equals 1,
Data0 will be discarded and I²S will start receiving data from Data1. If I2S_RX_MSB_RIGHT equals 1, data of the
first stage would be {0xF EDC0000, 0x32100000}. If I2S_RX_MSB_RIGHT equals 0, data of the first stage would
be {0x32100000, 0xF EDC0000}. When I2S_RX_RIGHT_FIRST equals 0, I²S will start receiving data from Data0.
If I2S_RX_MSB_RIGHT equals 1, data of the first stage would be {0xF EDC0000, 0x76540000}. If
I2S_RX_MSB_RIGHT equals 0, data of the first stage would be {0x76540000, 0xF EDC0000}.
As is shown in Table 60 and Figure 68, at the second stage, the received data of the Rx unit is written into FIFO.
There are four modes of writing received data into FIFO. Each mode corresponds to a value of
I2S_RX_FIFO_MOD[2:0] bit.
Table 60: Modes of Writing Received Data into FIFO and the Corresponding Register Configuration
At the third stage, CPU or DMA will read data from FIFO and write them into the internal memory directly. The
register configuration that each mode corresponds to is shown in Table 61.
Table 61: The Register Configuration to Which the Four Modes Correspond
I2S_RX_SLAVE_MOD bit and I2S_TX_SLAVE_MOD bit of register I2S_CONF_REG can configure I²S to slave
receiving mode and slave transmitting mode, respectively.
I2S_TX_START bit of register I2S_CONF_REG is used to enable transmission. When I²S is in master transmitting
mode and this bit is set, the module will keep driving the clock signal and data of left and right channels. If FIFO
sends out all the buffered data and there are no new data to shift, the last batch of data will be looped on the
data line. When this bit is reset, master will stop driving clock and data lines. When I²S is configured to slave
transmitting mode and this bit is set, the module will wait for the master BCK clock to enable a transmit
operation.
The I2S_RX_START bit of register I2S_CONF_REG is used to enable a receive operation. When I²S is in master
transmitting mode and this bit is set, the module will keep driving the clock signal and sampling the input data
stream until this bit is reset. If I²S is configured to slave receiving mode and this bit is set, the receiving module
will wait for the master BCK clock to enable a receiving operation.
The output clock of PDM is mapped to the I2S0*_WS_out signal. Its configuration is identical to I²S’s BCK.
Please refer to section 12.3, ”The Clock of I²S Module”, for further details. The bit width for both received and
transmitted I²S PCM signals is 16 bits.
The PDM transmitting module is used to convert PCM signals into PDM signals, as shown in Figure 69. HPF is a
high-speed channel filter, and LPF is a low-speed channel filter. The PDM signal is derived from the PCM signal,
after upsampling and filtering. Signal I2S_TX_PDM_HP_BYPASS of register I2S_PDM_CONF_REG can be set to
bypass the HPF at the PCM input. Filter module group0 carries out the upsampling. If the frequency of the PDM
signal is fpdm and the frequency of the PCM signal is fpcm , the relation between fpdm and fpcm is given by:
I2S_T X_P DM _F P
fpdm = 64×fpcm ×
I2S_T X_P DM _F S
The upsampling factor of 64 is the result of the two upsampling stages.
Table 62 lists the configuration rates of the I2S_TX_PDM_FP bit and the I2S_TX_PDM_FS bit of register
I2S_PDM_FREQ_CONF_REG, whose output PDM signal frequency remains 48×128 KHz at different PCM signal
frequencies.
The I2S_TX_PDM_SINC_OSR2 bit of I2S_PDM_CONF_REG is the upsampling rate of the Filter group0.
⌊ ⌋
I2S_T X_P DM _F P
I2S_T X_P DM _SIN C_OSR2 =
I2S_T X_P DM _F S
As is shown in Figure 70, the I2S_TX_PDM_EN bit and the I2S_PCM2PDM_CONV_EN bit of register
I2S_PDM_CONF_REG should be set to 1 to use the PDM sending module. The
I2S_TX_PDM_SIGMADELTA_IN_SHIFT bit, I2S_TX_PDM_SINC_IN_SHIFT bit, I2S_TX_PDM_LP_IN_SHIFT bit
and I2S_TX_PDM_HP_IN_SHIFT bit of register I2S_PDM_CONF_REG are used to adjust the size of the input
signal of each filter module.
As is shown in Figure 71, the I2S_RX_PDM_EN bit and the I2S_PDM2PCM_CONV_EN bit of register
I2S_PDM_CONF_REG should be set to 1, in order to use the PDM receiving module. As is shown in Figure 72,
the PDM receiving module will convert the received PDM signal into a 16-bit PCM signal. Filter group1 is used to
downsample the PDM signal, and the I2S_RX_PDM_SINC_DSR_16_EN bit of register I2S_PDM_CONF_REG is
used to adjust the corresponding down-sampling rate.
Table 63 shows the configuration of the I2S_RX_PDM_SINC_DSR_16_EN bit whose PCM signal frequency
remains 48 KHz at different PDM signal frequencies.
• ADC/DAC mode
The clock configuration of the LCD master transmitting mode is identical to I²S’ clock configuration. In the LCD
mode, the frequency of WS is half of f BCK .
The I2S_LCD_EN bit of register I2S_CONF2_REG needs to be set and the I2S_TX_SLAVE_MOD bit of register
I2S_CONF_REG needs to be cleared, in order to configure I²S to the LCD master transmitting mode. Meanwhile,
data should be sent under the correct mode, according to the I2S_TX_CHAN_MOD[2:0] bit of register
I2S_CONF_CHAN_REG and the I2S_TX_FIFO_MOD[2:0] bit of register I2S_FIFO_CONF_REG. The WS signal
needs to be inverted when it is routed through the GPIO Matrix. For details, please refer to the chapter about
IO_MUX and the GPIO Matrix. The I2S_LCD_TX_SDX2_EN bit and the I2S_LCD_TX_WRX2_EN bit of register
I2S_CONF2_REG should be set to the LCD master transmitting mode, so that both the data bus and WR signal
work in the appropriate mode.
As is shown in Figure 74 and Figure 75, the I2S_LCD_TX_WRX2_EN bit should be set to 1 and the
I2S_LCD_TX_SDX2_EN bit should be set to 0 in the data frame, form 1. Both I2S_LCD_TX_SDX2_EN bit and
I2S_LCD_TX_WRX2_EN bit are set to 1 in the data frame, form 2.
The PCLK in the Camera module connects to I2SnI_WS_in in the I²S module, as Figure 76 shows.
When I²S is in the camera slave receiving mode, and when I2Sn_H_SYNC, I2S_V_SYNC and I2S_H_REF are
held high, the master starts transmitting data, that is,
Thus, during data transmission, these three signals should be kept at a high level. For example, if the
I2Sn_V_SYNC signal of a camera is at low level during data transmission, it will be inverted when routed to the I²S
module. ESP32 supports signal inversion through the GPIO matrix. For details, please refer to the chapter about
IO_MUX and the GPIO Matrix.
In order to make I²S work in camera mode, the I2S_LCD_EN bit and the I2S_CAMERA_EN bit of register
I2S_CONF2_REG are set to 1, the I2S_RX_SLAVE_MOD bit of register I2S_CONF_REG is set to 1, the
I2S_RX_MSB_RIGHT bit and the I2S_RX_RIGHT_FIRST bit of I2S_CONF_REG are set to 0. Thus, I²S works in
the LCD slave receiving mode. At the same time, in order to use the correct mode to receive data, both the
I2S_RX_CHAN_MOD[2:0] bit of register I2S_CONF_CHAN_REG and the I2S_RX_FIFO_MOD[2:0] bit of register
I2S_FIFO_CONF_REG are set to 1.
Firstly, the I2S_LCD_EN bit of register I2S_CONF2_REG is set to 1, and the I2S_RX_SLAVE_MOD bit of register
I2S_CONF_REG is set to 0, so that the I2S0 module works in LCD master receiving mode, and the I2S0 module
clock is configured such that the WS signal of I2S0 outputs an appropriate frequency. Then, the
APB_CTRL_SARADC_DATA_TO_I2S bit of register APB_CTRL_APB_SARADC_CTRL_REG is set to 1. Enable
I²S to receive data after configuring the relevant registers of SARADC. For details, please refer to Chapter
On-Chip Sensors and Analog Signal Processing.
The I2S0 module should be configured to master transmitting mode when it connects to the on-chip DAC. Figure
78 shows the signal connection between the I2S0 module and the DAC. The DAC’s control module regards
I2S_CLK as the clock in this configuration. As shown in Figure 79, when the data bus inputs data to the DAC’s
control module, the latter will input right-channel data to DAC1 module and left-channel data to DAC2 module.
When using the I²S DMA module, 8 bits of data-to-be-transmitted are shifted to the left by 8 bits of
data-to-be-received into the DMA double-byte type of buffer.
• I2S_IN_DSCR_EMPTY_INT: Triggered when there are no valid receiving linked lists left.
• I2S_OUT_DONE_INT: Triggered when all transmitted and buffered data have been read.
Configuration registers
I2S_CONF_REG Configuration and start/stop bits 0x3FF4F008 0x3FF6D008 R/W
I2S_CONF1_REG PCM configuration register 0x3FF4F0A0 0x3FF6D0A0 R/W
ADC/LCD/camera configuration
I2S_CONF2_REG 0x3FF4F0A8 0x3FF6D0A8 R/W
register
Signal delay and timing parame-
I2S_TIMING_REG 0x3FF4F01C 0x3FF6D01C R/W
ters
I2S_FIFO_CONF_REG FIFO configuration 0x3FF4F020 0x3FF6D020 R/W
I2S_CONF_SINGLE_DATA_REG Static channel output value 0x3FF4F028 0x3FF6D028 R/W
I2S_CONF_CHAN_REG Channel configuration 0x3FF4F02C 0x3FF6D02C R/W
I2S_LC_HUNG_CONF_REG Timeout detection configuration 0x3FF4F074 0x3FF6D074 R/W
I2S_CLKM_CONF_REG Bitclock configuration 0x3FF4F0AC 0x3FF6D0AC R/W
I2S_SAMPLE_RATE_CONF_REG Sample rate configuration 0x3FF4F0B0 0x3FF6D0B0 R/W
I2S_PD_CONF_REG Power-down register 0x3FF4F0A4 0x3FF6D0A4 R/W
I2S_STATE_REG I2S status register 0x3FF4F0BC 0x3FF6D0BC RO
DMA registers
I2S_LC_CONF_REG DMA configuration register 0x3FF4F060 0x3FF6D060 R/W
I2S_RXEOF_NUM_REG Receive data count 0x3FF4F024 0x3FF6D024 R/W
DMA transmit linked list configu-
I2S_OUT_LINK_REG 0x3FF4F030 0x3FF6D030 R/W
ration and address
DMA receive linked list configura-
I2S_IN_LINK_REG 0x3FF4F034 0x3FF6D034 R/W
tion and address
The address of transmit link de-
I2S_OUT_EOF_DES_ADDR_REG 0x3FF4F038 0x3FF6D038 RO
scriptor producing EOF
The address of receive link de-
I2S_IN_EOF_DES_ADDR_REG 0x3FF4F03C 0x3FF6D03C RO
scriptor producing EOF
The address of transmit buffer
I2S_OUT_EOF_BFR_DES_ADDR_REG 0x3FF4F040 0x3FF6D040 RO
producing EOF
The address of current inlink de-
I2S_INLINK_DSCR_REG 0x3FF4F048 0x3FF6D048 RO
scriptor
The address of next inlink de-
I2S_INLINK_DSCR_BF0_REG 0x3FF4F04C 0x3FF6D04C RO
scriptor
The address of next inlink data
I2S_INLINK_DSCR_BF1_REG 0x3FF4F050 0x3FF6D050 RO
buffer
The address of current outlink de-
I2S_OUTLINK_DSCR_REG 0x3FF4F054 0x3FF6D054 RO
scriptor
The address of next outlink de-
I2S_OUTLINK_DSCR_BF0_REG 0x3FF4F058 0x3FF6D058 RO
scriptor
The address of next outlink data
I2S_OUTLINK_DSCR_BF1_REG 0x3FF4F05C 0x3FF6D05C RO
buffer
I2S_LC_STATE0_REG DMA receive status 0x3FF4F06C 0x3FF6D06C RO
I2S_LC_STATE1_REG DMA transmit status 0x3FF4F070 0x3FF6D070 RO
Pulse density (DE) modulation registers
I2S_PDM_CONF_REG PDM configuration 0x3FF4F0B4 0x3FF6D0B4 R/W
12.8 Registers
G
RE
R_
_W
FO
FI
S_
I2
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0
EG
D _R
_R
FO
FI
S_
I2
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0
I2S_FIFO_RD_REG Stores the data that I²S receives from FIFO. (RO)
I2 TX SB T_S NC
I2 RX SB SH NC
I2 TX LA _FI T
I2 RX LAV _M T
I2 TX TA _M D
I2 RX SB RIG K
TX ES E T
I2 TX ON IG T
ES T T
S
T
S_ _S VE RS
S T
S_ _R T FT
S_ _M R Y
S_ _R _R E
S_ _S E O
S_ _M _ C
S_ _M _ H
S _ _M _ Y
_R E SE
S_ _S RT O
S_ _M O H
S_ _S T R
S_ _R _ IF
I2 RX HO T_S
I2 RX IFO RES
I2 TX SB BA
I2 X GH _FI
I2 TX IGH HI
R
S_ _M P
ET
S_ _S O
S_ _F T
S_ _S R
S_ _F _
I2 RX LOO
I2 RX TAR
I2 RX ON
I2 X O
I2 TX IFO
H
I
d)
S_ _
I2 SIG
ve
R
T
er
S_
s
(re
I2
31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_SIG_LOOPBACK Enable signal loopback mode, with transmitter module and receiver module
sharing the same WS and BCK signals. (R/W)
I2S_RX_MSB_RIGHT Set this to place right-channel data at the MSB in the receive FIFO. (R/W)
I2S_TX_MSB_RIGHT Set this bit to place right-channel data at the MSB in the transmit FIFO. (R/W)
I2S_RX_MONO Set this bit to enable receiver’s mono mode in PCM standard mode. (R/W)
I2S_TX_MONO Set this bit to enable transmitter’s mono mode in PCM standard mode. (R/W)
I2S_RX_SHORT_SYNC Set this bit to enable receiver in PCM standard mode. (R/W)
I2S_TX_SHORT_SYNC Set this bit to enable transmitter in PCM standard mode. (R/W)
I2S_RX_MSB_SHIFT Set this bit to enable receiver in Philips standard mode. (R/W)
I2S_TX_MSB_SHIFT Set this bit to enable transmitter in Philips standard mode. (R/W)
E_ RA RA W
AW
se T F R_ IN RA
S_ T R_ R IN RA
S _ d N T_ _ A
IN W W
NT W
I2 TX UN _IN RAW AW
AK A _R W
I2 U C _E TY_ T_
I2 TX FU TY_ _R W
_I A
_R
W
E_ TA_ AW
TA T_R
S_ _P L IN AW
_T _D INT _RA
S_ _W P T RA
S_ _R L IN W
S_ D C P IN
S_ _W P T W
RA
S_ _H G _ R
I2 RX FU TY_ RA
I2 IN_ _DS EM F_
I2 RX UN INT T_
I2 TX EM _IN RA
I2 RX EM _IN T_
DA IN
T_
RX UT L_ T
O
_
S_ _R G T_
S_ _H E_ _I
S_ T R_ E
I2 OU SC L_
I2 X N F O
R
A
L
S_ D _E
S_ D T
I2 IN_ _TO
I2 N_ C
O
S
U
)
I2 IN_ )
ed
S_ S
S_ T
I2 OU
rv
T
I
se
S_
(re
I2
31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_OUT_TOTAL_EOF_INT_RAW The raw interrupt status bit for the I2S_OUT_TOTAL_EOF_INT in-
terrupt. (RO)
I2S_IN_DSCR_EMPTY_INT_RAW The raw interrupt status bit for the I2S_IN_DSCR_EMPTY_INT in-
terrupt. (RO)
I2S_OUT_DSCR_ERR_INT_RAW The raw interrupt status bit for the I2S_OUT_DSCR_ERR_INT in-
terrupt. (RO)
I2S_IN_DSCR_ERR_INT_RAW The raw interrupt status bit for the I2S_IN_DSCR_ERR_INT interrupt.
(RO)
I2S_OUT_EOF_INT_RAW The raw interrupt status bit for the I2S_OUT_EOF_INT interrupt. (RO)
I2S_OUT_DONE_INT_RAW The raw interrupt status bit for the I2S_OUT_DONE_INT interrupt. (RO)
I2S_IN_SUC_EOF_INT_RAW The raw interrupt status bit for the I2S_IN_SUC_EOF_INT interrupt.
(RO)
I2S_IN_DONE_INT_RAW The raw interrupt status bit for the I2S_IN_DONE_INT interrupt. (RO)
I2S_TX_HUNG_INT_RAW The raw interrupt status bit for the I2S_TX_HUNG_INT interrupt. (RO)
I2S_RX_HUNG_INT_RAW The raw interrupt status bit for the I2S_RX_HUNG_INT interrupt. (RO)
I2S_TX_REMPTY_INT_RAW The raw interrupt status bit for the I2S_TX_REMPTY_INT interrupt. (RO)
I2S_TX_WFULL_INT_RAW The raw interrupt status bit for the I2S_TX_WFULL_INT interrupt. (RO)
I2S_RX_REMPTY_INT_RAW The raw interrupt status bit for the I2S_RX_REMPTY_INT interrupt.
(RO)
I2S_RX_WFULL_INT_RAW The raw interrupt status bit for the I2S_RX_WFULL_INT interrupt. (RO)
I2S_TX_PUT_DATA_INT_RAW The raw interrupt status bit for the I2S_TX_PUT_DATA_INT interrupt.
(RO)
I2S_RX_TAKE_DATA_INT_RAW The raw interrupt status bit for the I2S_RX_TAKE_DATA_INT inter-
rupt. (RO)
se T F R_ IN ST
S_ T R_ R IN ST
S _ d N T_ _ T
I2 rve _DO _IN INT T_S
T
(re OU _EO ER R_ T_
I2 U C _E TY_ T_
E_ ST ST
_S
_I T
I2 TX UN _IN ST T
TA T_S
_T _D INT _ST
S_ D C P IN
S_ _W P T ST
NT
S _ _ H G T_ S
ST
E_ TA_ T
I2 TX FU TY_ _ST
I2 IN_ _DS EM F_
I2 RX UN _IN T_
I2 RX FU TY_ ST
I2 TX EM _IN ST
AK A _S
I2 RX EM _IN T_
DA IN
T_
RX UT L_ T
O
S_ _P L IN
S_ _R G T_
S_ _R L IN
IN
S_ _W P T
S_ _H E _I
S_ T R_ E
I2 OU SC L_
I2 X N F O
R
A
L
S_ _D _E
S_ D T
I2 IN_ _TO
I2 X C
O
S
U
d)
I2 IN_ )
S_ S
S_ T
ve
I2 OU
T
T
er
S_
s
(re
I2
31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_IN_DSCR_ERR_INT_ST The masked interrupt status bit for the I2S_IN_DSCR_ERR_INT inter-
rupt. (RO)
I2S_OUT_EOF_INT_ST The masked interrupt status bit for the I2S_OUT_EOF_INT interrupt. (RO)
I2S_OUT_DONE_INT_ST The masked interrupt status bit for the I2S_OUT_DONE_INT interrupt. (RO)
I2S_IN_SUC_EOF_INT_ST The masked interrupt status bit for the I2S_IN_SUC_EOF_INT interrupt.
(RO)
I2S_IN_DONE_INT_ST The masked interrupt status bit for the I2S_IN_DONE_INT interrupt. (RO)
I2S_TX_HUNG_INT_ST The masked interrupt status bit for the I2S_TX_HUNG_INT interrupt. (RO)
I2S_RX_HUNG_INT_ST The masked interrupt status bit for the I2S_RX_HUNG_INT interrupt. (RO)
I2S_TX_REMPTY_INT_ST The masked interrupt status bit for the I2S_TX_REMPTY_INT interrupt.
(RO)
I2S_TX_WFULL_INT_ST The masked interrupt status bit for the I2S_TX_WFULL_INT interrupt. (RO)
I2S_RX_REMPTY_INT_ST The masked interrupt status bit for the I2S_RX_REMPTY_INT interrupt.
(RO)
I2S_RX_WFULL_INT_ST The masked interrupt status bit for the I2S_RX_WFULL_INT interrupt. (RO)
I2S_TX_PUT_DATA_INT_ST The masked interrupt status bit for the I2S_TX_PUT_DATA_INT inter-
rupt. (RO)
I2S_RX_TAKE_DATA_INT_ST The masked interrupt status bit for the I2S_RX_TAKE_DATA_INT inter-
rupt. (RO)
E_ EN EN A
se T F R_ IN EN
S_ T R_ R IN EN
S_ d N T_ _ N
NA
IN A A
NT A
I2 U C _E TY_ T_
I2 TX UN _IN ENA NA
_I N
AK A _E A
_E
I2 TX FU TY_ _EN A
A
TA T_E
_T _D INT _EN
E_ TA_ NA
S_ _W P T EN
S_ _P L IN A
S_ D C P IN
EN
S_ _R L IN A
S_ _H G _ E
S_ _W P T A
I2 RX FU TY_ EN
I2 IN_ _DS EM F_
I2 RX UN INT T_
I2 TX EM _IN EN
I2 RX EM _IN T_
DA IN
T_
RX UT L_ T
O
_
S_ _R G T_
S_ _H E_ _I
S_ T R_ E
I2 OU SC L_
I2 X N F O
R
A
L
S_ D _E
S_ D T
I2 IN_ _TO
I2 N_ C
O
S
U
)
I2 IN_ )
ed
S_ S
S_ T
I2 OU
rv
T
I
se
S_
(re
I2
31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_OUT_EOF_INT_ENA The interrupt enable bit for the I2S_OUT_EOF_INT interrupt. (R/W)
I2S_OUT_DONE_INT_ENA The interrupt enable bit for the I2S_OUT_DONE_INT interrupt. (R/W)
I2S_IN_SUC_EOF_INT_ENA The interrupt enable bit for the I2S_IN_SUC_EOF_INT interrupt. (R/W)
I2S_IN_DONE_INT_ENA The interrupt enable bit for the I2S_IN_DONE_INT interrupt. (R/W)
I2S_TX_HUNG_INT_ENA The interrupt enable bit for the I2S_TX_HUNG_INT interrupt. (R/W)
I2S_RX_HUNG_INT_ENA The interrupt enable bit for the I2S_RX_HUNG_INT interrupt. (R/W)
I2S_TX_REMPTY_INT_ENA The interrupt enable bit for the I2S_TX_REMPTY_INT interrupt. (R/W)
I2S_TX_WFULL_INT_ENA The interrupt enable bit for the I2S_TX_WFULL_INT interrupt. (R/W)
I2S_RX_REMPTY_INT_ENA The interrupt enable bit for the I2S_RX_REMPTY_INT interrupt. (R/W)
I2S_RX_WFULL_INT_ENA The interrupt enable bit for the I2S_RX_WFULL_INT interrupt. (R/W)
E_ CL CL R
se T F R_ IN CL
S_ T R_ R IN CL
LR
S _ d N T_ _ L
IN R R
NT R
I2 U C _E TY_ T_
I2 TX UN _IN CLR LR
_C
_I L
AK A _C R
I2 TX FU TY_ _C R
R
TA T_C
_T _D INT _CL
E_ TA_ LR
S_ _W P T CL
S_ D C P IN
S_ _P L IN LR
S_ _H G _ C
S_ _R L IN R
CL
S_ _W P T R
I2 IN_ _DS EM F_
I2 RX UN INT T_
I2 RX FU TY_ CL
I2 TX EM _IN CL
I2 RX EM _IN T_
DA IN
T_
RX UT L_ T
O
_
S_ _R G T_
S_ _H E_ _I
S_ T R_ E
I2 OU SC L_
I2 X N F O
R
A
L
S_ D _E
S_ D T
I2 IN_ _TO
I2 N_ C
O
S
U
d)
I2 IN_ )
S_ S
S_ T
ve
I2 OU
T
er
I
S_
s
(re
I2
31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
NC SW AY
AY
AY
AY
AY
AY
EL
Y
EL
Y
EL
AY
LA
EL
AY
LA
EL
AY
_D
EL
_D
_D
V
EL
CK SW
DE
_D
EL
DE
_D
EL
_D
LE
S_ A_E _IN
UT
UT
_D
_D
UT
N_
_D
UT
S_ DSY C_
N_
_
S_ _D AB
UT
N
_O
_O
IN
IN
_O
IN
_I
O
_I
_ YN
_I
O
N
S_
CK
S_
S_
S_ BCK
CK
CK
D_
D_
S
TX S
_W
_W
_W
_W
_B
_B
_S
)
_B
_B
_S
ed
T
_
DA
I2 X
RX
RX
RX
RX
RX
TX
TX
TX
TX
TX
TX
rv
R
se
S_
S_
S_
S_
S_
S_
S_
S_
S_
S_
(re
I2
I2
I2
I2
I2
I2
I2
I2
I2
I2
I2
I2
I2
31 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_TX_BCK_IN_INV Set this bit to invert the BCK signal into the slave transmitter. (R/W)
I2S_RX_DSYNC_SW Set this bit to synchronize signals into the receiver in double sync method.
(R/W)
I2S_TX_DSYNC_SW Set this bit to synchronize signals into the transmitter in double sync method.
(R/W)
I2S_RX_BCK_OUT_DELAY Number of delay cycles for BCK signal out of the receiver. (R/W)
I2S_RX_WS_OUT_DELAY Number of delay cycles for WS signal out of the receiver. (R/W)
I2S_TX_SD_OUT_DELAY Number of delay cycles for SD signal out of the transmitter. (R/W)
I2S_TX_WS_OUT_DELAY Number of delay cycles for WS signal out of the transmitter. (R/W)
I2S_TX_BCK_OUT_DELAY Number of delay cycles for BCK signal out of the transmitter. (R/W)
I2S_RX_SD_IN_DELAY Number of delay cycles for SD signal into the receiver. (R/W)
I2S_RX_WS_IN_DELAY Number of delay cycles for WS signal into the receiver. (R/W)
I2S_RX_BCK_IN_DELAY Number of delay cycles for BCK signal into the receiver. (R/W)
I2S_TX_WS_IN_DELAY Number of delay cycles for WS signal into the transmitter. (R/W)
I2S_TX_BCK_IN_DELAY Number of delay cycles for BCK signal into the transmitter. (R/W)
E_ N
EN
RC _E
FO CE
D_ R
O FO
_M D_
UM
UM
D
D
IF MO
_N
_N
_M
_M
N
_F O_
TA
A
O
_E
O
AT
DA
TX IF
IF
IF
CR
)
_D
S_ _F
_F
_F
ed
X_
DS
I2 RX
RX
TX
TX
rv
_R
se
S_
S_
S_
S_
S_
S
(re
I2
I2
I2
I2
I2
I2
31 21 20 19 18 16 15 13 12 11 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 32 32 Reset
31 0
64 Reset
31 0
0 Reset
I2S_CONF_SINGLE_DATA_REG The right channel or the left channel outputs constant values stored
in this register according to TX_CHAN_MOD and I2S_TX_MSB_RIGHT. (R/W)
D
O
O
_M
M
N_
AN
HA
CH
_C
)
ed
_
RX
TX
rv
se
S_
S_
(re
I2
I2
31 5 4 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
I2S_RX_CHAN_MOD I²S receiver channel mode configuration bits. Please refer to Section 12.4.5 for
further details. (R/W)
I2S_TX_CHAN_MOD I²S transmitter channel mode configuration bits. Please refer to Section 12.4.4
for further details. (R/W)
R
P
DD
TO
UT K S
O LIN RE
_A
S_ T K_
NK
I2 OU LIN
LI
I2 OU )
)
S_ d
ed
S_ T
UT
I2 rve
rv
_O
se
se
S
(re
(re
I2
31 30 29 28 27 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset
DR
P
TO
IN K ES
D
S_ IN R
_A
I2 INL K_
NK
S_ IN
I2 INL )
d)
S_ d
LI
I2 rve
e
rv
IN
se
se
S_
(re
(re
I2
31 30 29 28 27 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
E EN
I2 AH _R TE ST K
S_ B P_ E C
S_ d F U N
s e T R S T_
O _
I2 AH O P_T BA
I2 OU ) _M ST
(re OU DSC UR RS
ST
I2 OU CR _B R
R
D
S_ B S ST
S_ S T E
S_ T _B U
_R ST _R
I2 IN_ _LO O_W
I2 IND _DA WN
IN _R O
I2 OU M_F T
A
S_ T IF
S_ T O
S_ L O
S_ T T
I2 OU CK_
I2 OU AU
ST
M
O
_
d)
S_ E
S_ T
ve
I2 CH
er
S_
s
(re
I2
31 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Reset
I2S_CHECK_OWNER Set this bit to check the owner bit by hardware. (R/W)
I2S_OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx
buffer has been transmitted. (R/W)
I2S_AHBM_FIFO_RST Set this bit to reset AHB interface cmdFIFO of DMA. (R/W)
31 0
0x000000000 Reset
31 0
0x000000000 Reset
FT
NA
HI
_S
_E
UT
UT
UT
EO
EO
EO
IM
IM
IM
_T
_T
_T
O
O
IF
IF
IF
d)
_F
_F
_F
ve
LC
LC
LC
r
se
S_
S_
S_
(re
I2
I2
I2
31 12 11 10 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0x010 Reset
I2S_LC_FIFO_TIMEOUT_SHIFT The bits are used to set the tick counter threshold. The tick counter
is reset when the counter value >= 88000/2i2s_lc_fifo_timeout_shift . (R/W)
I2S_LC_FIFO_TIMEOUT When the value of FIFO hung counter is equal to this bit value, sending
data-timeout interrupt or receiving data-timeout interrupt will be triggered. (R/W)
S
AS
AS
NF
NF
YP
YP
CM EN
CO
O
_B
_C
_B
_P P_
_
CM
CM
CM
R X TO
_P
)
S_ _S
_P
_P
ed
RX
I2 TX
TX
TX
rv
se
S_
S_
S_
S_
(re
I2
I2
I2
I2
31 9 8 7 6 4 3 2 0
I2S_TX_STOP_EN Set this bit and the transmitter will stop transmitting BCK signal and WS signal
when tx FIFO is empty. (R/W)
I2S_RX_PCM_BYPASS Set this bit to bypass the Compress/Decompress module for the received
data. (R/W)
I2S_TX_PCM_BYPASS Set this bit to bypass the Compress/Decompress module for the transmitted
data. (R/W)
E_ U
PD
RC P
O E_
_F RC
FO O
FI _F
d)
I2 rve )
I2 FIF )
se d
S_ d
S_ O
e
(re rve
rv
se
se
(re
(re
31 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 Reset
EN
N
A_ X2 N
T_
EN _E
E S N
ER R E
rv N TAR
M _W X2_
(re D_ C_ _E
LC AD LID
CA _TX D
S_ D _S
S_ T_ A
I2 EX R_V
I2 LC TX
_
d)
S_ )
d
S_ E
S_ D
ve
e
I2 INT
I2 LC
er
se
S_
s
(re
I2
I2
31 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Reset
I2S_EXT_ADC_START_EN Set this bit to enable the start of external ADC . (R/W)
I2S_LCD_TX_SDX2_EN Set this bit to duplicate data pairs (Data Frame, Form 2) in LCD mode. (R/W)
M
NU
B
_A
_
) A
IV
IV
IV
ed N
_D
_D
_D
rv _E
KM
KM
se KA
)
ed
LK
(re CL
CL
CL
rv
_C
se
S_
S_
S_
S
(re
I2
I2
I2
I2
31 22 21 20 19 14 13 8 7 0
M
NU
NU
D
V_
_
O
IV
DI
_M
_M
D
K_
K_
TS
TS
BC
BC
BI
BI
)
ed
X_
X_
X_
X_
rv
_R
_R
_T
_T
se
S
(re
I2
I2
I2
I2
31 24 23 18 17 12 11 6 5 0
0 0 0 0 0 0 0 0 16 16 6 6 Reset
I2S_RX_BITS_MOD Set the bits to configure the bit length of I²S receiver channel. (R/W)
I2S_TX_BITS_MOD Set the bits to configure the bit length of I²S transmitter channel. (R/W)
T
IF
SH
TA N
N_
DE 6_E
T
_I
IF
1
FT
FT
DM EN NV N
N
_S _DS S
SH
R_
2
DM INC PAS
_P M_ CO _E
_E
L
HI
SR
HI
_
_S
TX D _ NV
_S
IN
O
S Y
C_
IN
C_
IN
S_ _P M O
TX M_ _B
P_
I2 RX 2PD _C
P_
IG
IN
IN
S_ PD HP
N
_H
_S
_S
S_ M M
_E
_L
_ _
I2 PC 2PC
RX DM
DM
DM
DM
D
)
)
S_ _P
_P
_P
_P
_P
_P
S_ M
ed
ed
I2 PD
I2 TX
TX
TX
TX
TX
rv
rv
se
se
S_
S_
S_
S_
S_
S_
(re
(re
I2
I2
I2
I2
I2
I2
I2
31 26 25 24 23 22 21 20 19 18 17 16 15 8 7 4 3 2 1 0
I2S_TX_PDM_HP_BYPASS Set this bit to bypass the transmitter’s PDM HP filter. (R/W)
I2S_RX_PDM_SINC_DSR_16_EN PDM downsampling rate for filter group 1 in receiver mode. (R/W)
1: downsampling rate = 128;
0: downsampling rate = 64.
I2S_TX_PDM_SIGMADELTA_IN_SHIFT Adjust the size of the input signal into filter module. (R/W)
0: divided by 2; 1: multiplied by 1; 2: multiplied by 2; 3: multiplied by 4.
I2S_TX_PDM_SINC_IN_SHIFT Adjust the size of the input signal into filter module. (R/W)
0: divided by 2; 1: multiplied by 1; 2: multiplied by 2; 3: multiplied by 4.
I2S_TX_PDM_LP_IN_SHIFT Adjust the size of the input signal into filter module. (R/W)
0: divided by 2; 1: multiplied by 1; 2: multiplied by 2; 3: multiplied by 4.
I2S_TX_PDM_HP_IN_SHIFT Adjust the size of the input signal into filter module. (R/W)
0: divided by 2; 1: multiplied by 1; 2: multiplied by 2; 3: multiplied by 4.
S
_F
_F
DM
D M
d)
_P
_P
e
TX
TX
rv
se
S_
S_
(re
I2
I2
31 20 19 10 9 0
BA K
CK
T_ AC
E SE _B
DL RE T
_I _ SE
TX IFO RE
S_ _F _
I2 TX IFO
d)
S_ _F
ve
I2 RX
er
S_
s
(re
I2
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
I2S_RX_FIFO_RESET_BACK This bit is used to confirm if the Rx FIFO reset is done. 1: reset is not
ready; 0: reset is ready. (RO)
I2S_TX_FIFO_RESET_BACK This bit is used to confirm if the Tx FIFO reset is done. 1: reset is not
ready; 0: reset is ready. (RO)
I2S_TX_IDLE The status bit of the transmitter. 1: the transmitter is idle; 0: the transmitter is busy.
(RO)
13.1 Overview
Embedded applications often require a simple method of exchanging data between devices that need minimal
system resources. The Universal Asynchronous Receiver/Transmitter (UART) is one such standard that can
realize a flexible full-duplex data exchange among different devices. The three UART controllers available on a
chip are compatible with UART-enabled devices from various manufacturers. The UART can also carry out an
IrDA (Infrared Data Exchange), or function as an RS-485 modem.
All UART controllers integrated in the ESP32 feature an identical set of registers for ease of programming and
flexibility. In this documentation, these controllers are referred to as UARTn, where n = 0, 1, and 2, referring to
UART0, UART1, and UART2, respectively.
A typical UART frame begins with a START bit, followed by a “character” and an optional parity bit for error
detection, and it ends with a STOP condition. The UART controllers available on the ESP32 provide hardware
support for multiple lengths of data and STOP bits. In addition, the controllers support both software and
hardware flow control, as well as DMA, for seamless high-speed data transfer. This allows the developer to
employ multiple UART ports in the system with minimal software overhead.
Figure 80 shows the basic block diagram of the UART controller. The UART block can derive its clock from two
sources: the 80-MHz APB_CLK, or the reference clock REF_TICK (please refer to Chapter Reset and Clock for
more details). These two clock sources can be selected by configuring UART_TICK_REF_ALWAYS_ON.
Then, a divider in the clock path divides the selected clock source to generate clock signals that drive the UART
module. UART_CLKDIV_REG contains the clock divider value in two parts — UART_CLKDIV (integral part) and
UART_CLKDIV_FRAG (decimal part).
The UART controller can be further broken down into two functional blocks — the transmit block and the receive
block.
The transmit block contains a transmit-FIFO buffer, which buffers data awaiting to be transmitted. Software can
write Tx_FIFO via APB, and transmit data into Tx_FIFO via DMA. Tx_FIFO_Ctrl is used to control read- and
write-access to the Tx_FIFO. When Tx_FIFO is not null, Tx_FSM reads data via Tx_FIFO_Ctrl, and transmits data
out according to the set frame format. The outgoing bit stream can be inverted by appropriately configuring the
register UART_TXD_INV.
The receive-block contains a receive-FIFO buffer, which buffers incoming data awaiting to be processed. The
input bit stream, rxd_in, is fed to the UART controller. Negation of the input stream can be controlled by
configuring the UART_RXD_INV register. Baudrate_Detect measures the baud rate of the input signal by
measuring the minimum pulse width of the input bit stream. Start_Detect is used to detect a START bit in a frame
of incoming data. After detecting the START bit, RX_FSM stores data retrieved from the received frame into
Rx_FIFO through Rx_FIFO_Ctrl.
Software can read data in the Rx_FIFO through the APB. In order to free the CPU from engaging in data transfer
operations, the DMA can be configured for sending or receiving data.
HW_Flow_Ctrl is able to control the data flow of rxd_in and txd_out through standard UART RTS and CTS flow
control signals (rtsn_out and ctsn_in). SW_Flow_Ctrl controls the data flow by inserting special characters in the
incoming and outgoing data flow. When UART is in Light-sleep mode (refer to Chapter Low-Power
Management), Wakeup_Ctrl will start counting pulses in rxd_in. When the number or positive edges of RxD signal
is greater than or equal to (UART_ACTIVE_THRESHOLD+2), a wake_up signal will be generated and sent to
RTC. RTC will then wake up the UART controller. Note that only UART1 and UART2 support Light-sleep mode
and that rxd_in cannot be input through GPIO Matrix but only through IO_MUX.
Three UART controllers share a 1024 × 8-bit RAM space. As illustrated in Figure 81, RAM is allocated in different
blocks. One block holds 128 × 8-bit data. Figure 81 illustrates the default RAM allocated to Tx_FIFO and
Rx_FIFO of the three UART controllers. Tx_FIFO of UARTn can be extended by setting UARTn_TX_SIZE, while
Rx_FIFO of UARTn can be extended by setting UARTn_RX_SIZE.
NOTICE: Extending the FIFO space of a UART controller may take up the FIFO space of another UART
controller.
If none of the UART controllers is active, setting UART_MEM_PD, UART1_MEM_PD, and UART2_MEM_PD can
prompt the RAM to enter low-power mode.
In UART0, bit UART_TXFIFO_RST and bit UART_RXFIFO_RST can be set to reset Tx_FIFO or Rx_FIFO,
respectively. In UART1, bit UART1_TXFIFO_RST and bit UART1_RXFIFO_RST can be set to reset Tx_FIFO or
Rx_FIFO, respectively.
Note:
UART2 doesn’t have any register to reset Tx_FIFO or Rx_FIFO, and the UART1_TXFIFO_RST and UART1_RXFIFO_RST
in UART1 may impact the functioning of UART2. Therefore, these 2 registers in UART1 should only be used when the
Tx_FIFO and Rx_FIFO in UART2 do not have any data.
In order to use the baud rate detection feature, some random data should be sent to the receiver before starting
the UART communication stream. This is required so that the baud rate can be determined based on the pulse
width. UART_LOWPULSE_MIN_CNT stores minimum low-pulse width, UART_HIGHPULSE_MIN_CNT stores
minimum high-pulse width. By reading these two registers, software can calculate the baud rate of the
transmitter.
The length of a character (BIT0 to BITn) can comprise 5 to 8 bits and can be configured by UART_BIT_NUM.
When UART_PARITY_EN is set, the UART controller hardware will add the appropriate parity bit after the data.
UART_PARITY is used to select odd parity or even parity. If the receiver detects an error in the input character,
interrupt UART_PARITY_ERR_INT will be generated. If the receiver detects an error in the frame format, interrupt
UART_FRM_ERR_INT will be generated.
Interrupt UART_TX_DONE_INT will be generated when all data in Tx_FIFO have been transmitted. When
UART_TXD_BRK is set, the transmitter sends several NULL characters after the process of sending data is
completed. The number of NULL characters can be configured by UART_TX_BRK_NUM. After the transmitter
finishes sending all NULL characters, interrupt UART_TX_BRK_DONE_INT will be generated. The minimum
interval between data frames can be configured with UART_TX_IDLE_NUM. If the idle time of a data frame is
equal to, or larger than, the configured value of register UART_TX_IDLE_NUM, interrupt
UART_TX_BRK_IDLE_DONE_INT will be generated.
Figure 83 shows a special AT_CMD character format. If the receiver constantly receives UART_AT_CMD_CHAR
characters and these characters satisfy the following conditions, interrupt UART_AT_CMD_CHAR_DET_INT will
be generated.
• Between the first UART_AT_CMD_CHAR and the last non-UART_AT_CMD_CHAR, there are at least
UART_PER_IDLE_NUM APB clock cycles.
• Between every UART_AT_CMD_CHAR character there must be less than UART_RX_GAP_TOUT APB
clock cycles.
• The number of received UART_AT_CMD_CHAR characters must be equal to, or greater than,
UART_CHAR_NUM.
• Between the last UART_AT_CMD_CHAR character received and the next non-UART_AT_CMD_CHAR,
there are at least UART_POST_IDLE_NUM APB clock cycles.
Figure 84 illustrates how the UART hardware flow control works. In hardware flow control, a high state of the
output signal rtsn_out signifies that a data transmission is requested, while a low state of the same signal notifies
the counterpart to stop data transmission until rtsn_out is pulled high again. There are two ways for a transmitter
to realize hardware flow control:
If the UART controller detects an edge on ctsn_in, it will generate interrupt UART_CTS_CHG_INT and will stop
transmitting data, once the current data transmission is completed.
The high level of the output signal dtrn_out signifies that the transmitter has finished data preparation. UART
controller will generate interrupt UART_DSR_CHG_INT, after it detects an edge on the input signal dsrn_in. After
the software detects the above-mentioned interrupt, the input signal level of dsrn_in can be figured out by
reading UART_DSRN. The software then decides whether it is able to receive data at that time or not.
Setting UART_LOOPBACK will enable the UART loopback detection function. In this mode, the output signal
txd_out of UART is connected to its input signal rxd_in, rtsn_out is connected to ctsn_in, and dtrn_out is
connected to dsrn_out. If the data transmitted corresponds to the data received, UART is able to transmit and
receive data normally.
Software can force the transmitter to stop transmitting data by setting UART_FORCE_XOFF, as well as force the
transmitter to continue sending data by setting UART_FORCE_XON.
UART can also control the software flow by transmitting special characters. Setting UART_SW_FLOW_CON_EN
will enable the software flow control function. If the number of data bytes that UART has received exceeds that of
the UART_XOFF threshold, the UART controller can send UART_XOFF_CHAR to instruct its counterpart to stop
data transmission.
When UART_SW_FLOW_CON_EN is 1, software can send flow control characters at any time. When
UART_SEND_XOFF is set, the transmitter will insert a UART_XOFF_CHAR and send it after the current data
transmission is completed. When UART_SEND_XON is set, the transmitter will insert a UART_XON_CHAR and
send it after the current data transmission is completed.
• UART_TX_DONE_INT: Triggered when the transmitter has sent out all FIFO data.
• UART_TX_BRK_IDLE_DONE_INT: Triggered when the transmitter’s idle state has been kept to a minimum
after sending the last data.
• UART_TX_BRK_DONE_INT: Triggered when the transmitter completes sending NULL characters, after all
data in transmit-FIFO are sent.
• UART_SW_XOFF_INT: Triggered, if the receiver gets an Xon char when UART_SW_FLOW_CON_EN is set
to 1.
• UART_SW_XON_INT: Triggered, if the receiver gets an Xoff char when UART_SW_FLOW_CON_EN is set
to 1.
• UART_RXFIFO_TOUT_INT: Triggered when the receiver takes more time than RX_TOUT_THRHD to receive
a byte.
• UART_BRK_DET_INT: Triggered when the receiver detects a 0 level after the STOP bit.
• UART_CTS_CHG_INT: Triggered when the receiver detects an edge change of the CTSn signal.
• UART_DSR_CHG_INT: Triggered when the receiver detects an edge change of the DSRn signal.
• UART_RXFIFO_OVF_INT: Triggered when the receiver gets more data than the FIFO can store.
• UART_PARITY_ERR_INT: Triggered when the receiver detects a parity error in the data.
• UART_TXFIFO_EMPTY_INT: Triggered when the amount of data in the transmit-FIFO is less than what
tx_mem_cnttxfifo_cnt specifies.
• UART_RXFIFO_FULL_INT: Triggered when the receiver gets more data than what (rx_flow_thrhd_h3,
rx_flow_thrhd) specifies.
• UHCI_SEND_S_REG_Q_INT: When using the single_send registers to send a series of short packets, this is
triggered when DMA has sent a short packet.
• UHCI_OUTLINK_EOF_ERR_INT: Triggered when there are some errors in EOF in the outlink descriptor.
• UHCI_IN_DSCR_EMPTY_INT: Triggered when there are not enough inlinks for DMA.
• UHCI_OUT_DSCR_ERR_INT: Triggered when there are some errors in the inlink descriptor.
• UHCI_IN_DSCR_ERR_INT: Triggered when there are some errors in the outlink descriptor.
• UHCI_IN_ERR_EOF_INT: Triggered when there are some errors in EOF in the inlink descriptor.
• UHCI_TX_HUNG_INT: Triggered when DMA takes much time to read data from RAM.
13.5 Registers
Y TE
D_B
_R
FO
FI
RX
d)
ve
T_
r
se
R
UA
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RXFIFO_RD_BYTE This register stores one byte of data, as read from the Rx_FIFO. (RO)
UA T_ _B E_ TY_ _IN W AW
UA T_ FIF N_ T_ _RA W AW
W
RA
R GL RK L A IN W
R TX ON RI R RA R
R RX O IN T RA R
UA T_ _D PA _ER T_ NT_
UA _ _X F_ IN T_ T_
UA T_ _B _ID T_R RR_ RA
UA T_ ITC _D E_D W T_
RA W
UA T_ FIF HG T_ W W
RT SW OF ET_ IN _IN
W
T_ A
R BR O IN RA W
R TX RK IN E T_
UL _ AW
XF _E R_ AW W
R TX 5_ M IN _I
R RX C IN A A
IN _R
UA T_ R_ G_ T_R T_R
_R IFO ER T_R A
UA T_ 48 FR H_ ET
UA T_ _X _D NE_ NE
UA T_ RIT R_ _IN AW
UA T_ M_ _OV T_ W
UA T_ K_ _TO T_R W
L_ INT
_F T Y R
RT TXF Y_ IN T_R
UA T_ S_ ET_ T_I W
R FR O _IN RA
R RS 5_ AS _D
O P T_
R SW H O O
R CT D U A
R PA ER F R
R DS CH IN N
IF M IN
UA T_ 48 CL AR
R RS 5_ H
UA T_ 48 D_C
R RS M
UA _ C
RT AT_
)
ed
UA T_
rv
se
R
UA
(re
31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RS485_CLASH_INT_RAW The raw interrupt status bit for the UART_RS485_CLASH_INT in-
terrupt. (RO)
UART_TX_DONE_INT_RAW The raw interrupt status bit for the UART_TX_DONE_INT interrupt. (RO)
UART_GLITCH_DET_INT_RAW The raw interrupt status bit for the UART_GLITCH_DET_INT inter-
rupt. (RO)
UART_SW_XOFF_INT_RAW The raw interrupt status bit for the UART_SW_XOFF_INT interrupt. (RO)
UART_SW_XON_INT_RAW The raw interrupt status bit for the UART_SW_XON_INT interrupt. (RO)
UART_RXFIFO_TOUT_INT_RAW The raw interrupt status bit for the UART_RXFIFO_TOUT_INT in-
terrupt. (RO)
UART_BRK_DET_INT_RAW The raw interrupt status bit for the UART_BRK_DET_INT interrupt. (RO)
UART_CTS_CHG_INT_RAW The raw interrupt status bit for the UART_CTS_CHG_INT interrupt. (RO)
UART_DSR_CHG_INT_RAW The raw interrupt status bit for the UART_DSR_CHG_INT interrupt.
(RO)
UART_RXFIFO_OVF_INT_RAW The raw interrupt status bit for the UART_RXFIFO_OVF_INT inter-
rupt. (RO)
UART_FRM_ERR_INT_RAW The raw interrupt status bit for the UART_FRM_ERR_INT interrupt. (RO)
UART_PARITY_ERR_INT_RAW The raw interrupt status bit for the UART_PARITY_ERR_INT inter-
rupt. (RO)
UART_RXFIFO_FULL_INT_RAW The raw interrupt status bit for the UART_RXFIFO_FULL_INT inter-
rupt. (RO)
R TX ON RI R ST ST
R RX O IN T ST ST
ST
UA T_ _D PA _ER T_ NT_
UA _ _X F_ IN T_ T_
T_
UA T_ _B _ID T_S RR_ ST
RT SW OF ET_ IN _IN
R GL RK L T IN
T_ T
R TX RK IN E T_
R TX 5_ M IN _I
IN _S
R RX C IN T T
ST
UA T_ FIF N_ T_ _ST
UA T_ R_ G_ T_S T_S
UA T_ 48 FR H_ ET
UA _ _X D E_ E
UA T_ _B E_ TY_ _IN
UL _ T
_R IFO ER T_S T
L_ INT
_F TY S
RT SW H_ ON ON
RT TXF Y_ IN T_S
UA T_ RIT R_ _IN T
R RS 5_ AS _D
R FR O _IN ST
O P T_
XF _E R_ T
R BR O IN ST
R DS CH IN N
R PA ER F S
R CT D U T
UA T_ ITC _D E_D
UA T_ K_ _TO T_S
UA T_ M_ _OV T_
IF M IN
UA T_ 48 CL AR
UA T_ S_ ET_ T_I
UA T_ FIF HG T_
R RS 5_ H
UA T_ 48 D_C
R RS M
UA _ C
RT AT_
d)
ve
UA T_
er
R
s
UA
(re
31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_TX_DONE_INT_ST The masked interrupt status bit for the UART_TX_DONE_INT interrupt.
(RO)
UART_GLITCH_DET_INT_ST The masked interrupt status bit for the UART_GLITCH_DET_INT inter-
rupt. (RO)
UART_SW_XOFF_INT_ST The masked interrupt status bit for the UART_SW_XOFF_INT interrupt.
(RO)
UART_SW_XON_INT_ST The masked interrupt status bit for the UART_SW_XON_INT interrupt. (RO)
UART_BRK_DET_INT_ST The masked interrupt status bit for the UART_BRK_DET_INT interrupt.
(RO)
UART_CTS_CHG_INT_ST The masked interrupt status bit for the UART_CTS_CHG_INT interrupt.
(RO)
UART_DSR_CHG_INT_ST The masked interrupt status bit for the UART_DSR_CHG_INT interrupt.
(RO)
UART_RXFIFO_OVF_INT_ST The masked interrupt status bit for the UART_RXFIFO_OVF_INT inter-
rupt. (RO)
UART_FRM_ERR_INT_ST The masked interrupt status bit for the UART_FRM_ERR_INT interrupt.
(RO)
UART_PARITY_ERR_INT_ST The masked interrupt status bit for the UART_PARITY_ERR_INT inter-
rupt. (RO)
UA T_ _B E_ TY_ _IN A NA
UA T_ FIF N_ T_ _EN A NA
A
EN
R TX ON RI R EN E
R RX O IN T EN E
R GL RK L N IN A
UA T_ _D PA _ER T_ NT_
UA _ _X F_ IN T_ T_
UA T_ _B _ID T_E RR_ EN
UA T_ ITC _D E_D A T_
EN A
RT SW OF ET_ IN _IN
UA T_ FIF HG T_ A A
T_ N
A
R TX RK IN E T_
R BR O IN EN A
R TX 5_ M IN _I
R RX C IN N N
UL _ NA
XF _E R_ NA A
IN _E
_R IFO ER T_E N
UA T_ R_ G_ T_E T_E
UA T_ 48 FR H_ ET
UA T_ _X _D NE_ NE
UA T_ RIT R_ _IN A
UA T_ M_ _OV T_ A
L_ INT
UA T_ K_ _TO T_E A
_F T Y E
RT TXF Y_ IN T_E
UA T_ S_ ET_ T_I A
R PA ER F EN
R FR O _IN EN
R RS 5_ AS _D
O P T_
R SW H O O
R CT D U N
R DS CH IN N
IF M IN
UA T_ 48 CL AR
R RS 5_ H
UA T_ 48 D_C
R RS M
UA _ C
RT AT_
)
ed
UA T_
rv
se
R
UA
(re
31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_TX_DONE_INT_ENA The interrupt enable bit for the UART_TX_DONE_INT interrupt. (R/W)
UART_SW_XOFF_INT_ENA The interrupt enable bit for the UART_SW_XOFF_INT interrupt. (R/W)
UART_SW_XON_INT_ENA The interrupt enable bit for the UART_SW_XON_INT interrupt. (R/W)
UART_BRK_DET_INT_ENA The interrupt enable bit for the UART_BRK_DET_INT interrupt. (R/W)
UART_CTS_CHG_INT_ENA The interrupt enable bit for the UART_CTS_CHG_INT interrupt. (R/W)
UART_DSR_CHG_INT_ENA The interrupt enable bit for the UART_DSR_CHG_INT interrupt. (R/W)
UART_FRM_ERR_INT_ENA The interrupt enable bit for the UART_FRM_ERR_INT interrupt. (R/W)
UA T_ _B E_ TY_ _IN R LR
UA T_ FIF N_ T_ _CL LR LR
R
CL
R TX ON RI R CL C
R RX O IN T C C
R GL RK L L IN R
UA T_ _D PA _ER T_ NT_
UA _ _X F_ IN T_ T_
UA T_ _B _ID T_C RR_ CL
UA T_ ITC _D E_D R T_
CL R
RT SW OF ET_ IN _IN
UA T_ FIF HG T_ R R
T_ L
R
R TX RK IN E T_
R BR O IN CL R
R TX 5_ M IN _I
IN _C
UL _ LR
R RX C IN L L
_R IFO ER T_C LR
UA T_ R_ G_ T_C T_C
UA T_ 48 FR H_ ET
UA T_ _X _D NE_ NE
UA T_ RIT R_ _IN LR
UA T_ M_ _OV T_ LR
L_ INT
_F T Y C
XF _E R_ LR
RT TXF Y_ IN T_C
UA T_ K_ _TO T_C R
UA T_ S_ ET_ T_I R
R RS 5_ AS _D
O P T_
R SW H O O
R PA ER F C
R CT D U L
R DS CH IN N
R FR O _IN C
IF M IN
UA T_ 48 CL AR
R RS 5_ H
UA T_ 48 D_C
R RS M
UA T_ _C
)
R AT
ed
UA T_
rv
se
R
UA
(re
31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RXFIFO_FULL_INT_CLR Set this bit to clear the UART_RXFIFO_FULL_INT interrupt. This bit
can be set only when data in Rx_FIFO is less than UART_RXFIFO_FULL_THRHD. (WO)
AG
FR
_
IV
IV
D
D
LK
LK
)
ed
_C
_C
rv
RT
RT
se
UA
UA
(re
31 24 23 20 19 0
N
_E
LT
UD
FI
H_
BA
TC
O
UT
LI
d)
)
ed
_G
_A
e
rv
rv
RT
RT
se
se
UA
UA
(re
(re
31 16 15 8 7 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x010 0 0 0 0 0 0 0 0 Reset
UART_GLITCH_FILT When the input pulse width is lower than this value, the pulse is ignored. This
register is used in the autobauding process. (R/W)
UT
UT
NT
N T
O
_O
_C
_C
X_
X
O
FO
UR
UT
rv RN
rv RN
(re T_ SN
(re T_ SN
IF
UA T_ D
FI
RT TXD
F
T_
T_
s e DS
R CT
se DT
R RX
RX
R RT
)
TX
ed
ed
_S
_S
UA T_
UA _
T_
UA T_
T_
RT
RT
R
R
UA
UA
UA
UA
UA
UA
31 30 29 28 27 24 23 16 15 14 13 12 11 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_TXD This bit represents the level of the internal UART RxD signal. (RO)
UART_RTSN This bit corresponds to the level of the internal UART CTS signal. (RO)
UART_DTRN This bit corresponds to the level of the internal UAR DSR signal. (RO)
UART_ST_UTX_OUT This register stores the state of the transmitter’s finite state machine. 0:
TX_IDLE; 1: TX_STRT; 2: TX_DAT0; 3: TX_DAT1; 4: TX_DAT2; 5: TX_DAT3; 6: TX_DAT4; 7:
TX_DAT5; 8: TX_DAT6; 9: TX_DAT7; 10: TX_PRTY; 11: TX_STP1; 12: TX_STP2; 13: TX_DL0;
14: TX_DL1. (RO)
UART_TXFIFO_CNT (tx_mem_cnt, txfifo_cnt) stores the number of bytes of valid data in transmit-
FIFO. tx_mem_cnt stores the three most significant bits, txfifo_cnt stores the eight least significant
bits. (RO)
UART_RXD This bit corresponds to the level of the internal UART RxD signal. (RO)
UART_CTSN This bit corresponds to the level of the internal UART CTS signal. (RO)
UART_DSRN This bit corresponds to the level of the internal UAR DSR signal. (RO)
UART_ST_URX_OUT This register stores the value of the receiver’s finite state machine. 0: RX_IDLE;
1: RX_STRT; 2: RX_DAT0; 3: RX_DAT1; 4: RX_DAT2; 5: RX_DAT3; 6: RX_DAT4; 7: RX_DAT5; 8:
RX_DAT6; 9: RX_DAT7; 10: RX_PRTY; 11: RX_STP1; 12:RX_STP2; 13: RX_DL1. (RO)
UART_RXFIFO_CNT (rx_mem_cnt, rxfifo_cnt) stores the number of bytes of valid data in the receive-
FIFO. rx_mem_cnt register stores the three most significant bits, rxfifo_cnt stores the eight least
significant bits. (RO)
N
O
S_
AY
M
W
NU
UA T_ DA_ AC N
AL
R IR T NV
R IR W NV
R TX E T
R TX D N
R IR O T
R IR B E
R IR T L
R IR R K
RT SW BR X
UA T_ DA_ _RS
IT EN
T_
UA T_ FIF _RS
F_
UA T_ DA_ X_E
UA T_ DA_ CT
UA T_ OP W_
UA T_ DA_ X_I
UA T_ DA_ X_I
UA T_ D_ PL
_ _ K
UM
UA T_ S_ V
UA T_ _FL N
UA T_ FIF V
UA SW DTR
BI
UA T_ S_ V
UA T_ D_ V
_S TS
RE
RT TXD INV
UA T_ R_ V
AR Y_
R LO O
R CT IN
R TX IN
R T N
R RX IN
Y
R DS IN
R RX O
P_
RT _R
RT _N
_P IT
K_
I
UA T_ R_
UA _ _
TO
RT PAR
IC
IT
R T
d)
)
ed
D
R
_B
_T
ve
UA T_
UA _
v
RT
RT
er
er
R
s
s
UA
UA
UA
UA
(re
(re
31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 Reset
UART_TICK_REF_ALWAYS_ON This register is used to select the clock; 1: APB clock; 0: REF_TICK.
(R/W)
UART_DTR_INV Set this bit to invert the level of the UART DTR signal. (R/W)
UART_RTS_INV Set this bit to invert the level of the UART RTS signal. (R/W)
UART_TXD_INV Set this bit to invert the level of the UART TxD signal. (R/W)
UART_DSR_INV Set this bit to invert the level of the UART DSR signal. (R/W)
UART_CTS_INV Set this bit to invert the level of the UART CTS signal. (R/W)
UART_RXD_INV Set this bit to invert the level of the UART Rxd signal. (R/W)
UART_TXFIFO_RST Set this bit to reset the UART transmit-FIFO. NOTICE: UART2 doesn’t have any
register to reset Tx_FIFO or Rx_FIFO, and the UART1_TXFIFO_RST and UART1_RXFIFO_RST in
UART1 may impact the functioning of UART2. Therefore, these two registers in UART1 should
only be used when the Tx_FIFO and Rx_FIFO in UART2 do not have any data. (R/W)
UART_RXFIFO_RST Set this bit to reset the UART receive-FIFO. NOTICE: UART2 doesn’t have any
register to reset Tx_FIFO or Rx_FIFO, and the UART1_TXFIFO_RST and UART1_RXFIFO_RST in
UART1 may impact the functioning of UART2. Therefore, these two registers in UART1 should
only be used when the Tx_FIFO and Rx_FIFO in UART2 do not have any data. (R/W)
UART_TX_FLOW_EN Set this bit to enable the flow control function for the transmitter. (R/W)
UART_LOOPBACK Set this bit to enable the UART loopback test mode. (R/W)
UART_IRDA_RX_INV Set this bit to invert the level of the IrDA receiver. (R/W)
UART_IRDA_TX_INV Set this bit to invert the level of the IrDA transmitter. (R/W)
UART_IRDA_WCTL 1: The IrDA transmitter’s 11th bit is the same as its 10th bit; 0: set IrDA trans-
mitter’s 11th bit to 0. (R/W)
UART_IRDA_TX_EN This is the start enable bit of the IrDA transmitter. (R/W)
UART_IRDA_DPLX Set this bit to enable the IrDA loopback mode. (R/W)
UART_TXD_BRK Set this bit to enable the transmitter to send NULL, when the process of sending
data is completed. (R/W)
UART_SW_DTR This register is used to configure the software DTR signal used in software flow
control. (R/W)
UART_SW_RTS This register is used to configure the software RTS signal used in software flow con-
trol. (R/W)
UART_STOP_BIT_NUM This register is used to set the length of the stop bit; 1: 1 bit, 2: 1.5 bits.
(R/W)
UART_BIT_NUM This register is used to set the length of data; 0: 5 bits, 1: 6 bits, 2: 7 bits, 3: 8
bits. (R/W)
UART_PARITY_EN Set this bit to enable the UART parity check. (R/W)
UART_PARITY This register is used to configure the parity check mode; 0: even, 1: odd. (R/W)
D
RH
HD
TH
HR
HD
HD
Y_
_T
HR
HR
PT
N
N
L
_E
UL
_T
_E
_T
M
W
_F
UT
UT
_E
O
LO
O
O
O
TO
FL
F
IF
_T
_F
FI
X_
X_
XF
RX
RX
RX
d)
)
ed
_R
_T
ve
T_
T_
T_
T_
rv
RT
RT
er
se
R
R
s
UA
UA
UA
UA
UA
UA
(re
(re
31 30 24 23 22 16 15 14 8 7 6 0
UART_RX_TOUT_EN This is the enable bit for the UART receive-timeout function. (R/W)
UART_RX_TOUT_THRHD This register is used to configure the UART receiver’s timeout value when
receiving a byte. When using APB_CLK as the clock source, the register counts by UART baud
APB_CLK frequency
cycle. When using REF_TICK as the clock source, the register counts by (REF_TICK frequency)*8 . (R/W)
UART_RX_FLOW_EN This is the flow enable bit of the UART receiver; 1: choose software flow control
by configuring the sw_rts signal; 0: disable software flow control. (R/W)
UART_RX_FLOW_THRHD When the receiver gets more data than its threshold value, the receiver
produces a signal that tells the transmitter to stop transferring data. The threshold value is
(rx_flow_thrhd_h3, rx_flow_thrhd). (R/W)
UART_TXFIFO_EMPTY_THRHD When the data amount in transmit-FIFO is less than its thresh-
old value, it will produce a TXFIFO_EMPTY_INT_RAW interrupt. The threshold value is
(tx_mem_empty_thrhd, txfifo_empty_thrhd). (R/W)
UART_RXFIFO_FULL_THRHD When the receiver gets more data than its threshold value, the re-
ceiver will produce an RXFIFO_FULL_INT_RAW interrupt. The threshold value is (rx_flow_thrhd_h3,
rxfifo_full_thrhd). (R/W)
_L
rv
RT
se
UA
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x0FFFFF Reset
UART_LOWPULSE_MIN_CNT This register stores the value of the minimum duration of the low-level
pulse. It is used in the baud rate detection process. (RO)
NT
_C
IN
M
E_
S
UL
HP
IG
d)
_H
ve
RT
er
s
UA
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x0FFFFF Reset
UART_HIGHPULSE_MIN_CNT This register stores the value of the minimum duration of the high
level pulse. It is used in baud rate detection process. (RO)
T
CN
E_
GD
_E
XD
d)
_R
ve
RT
r
se
UA
(re
31 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000 Reset
UART_RXD_EDGE_CNT This register stores the count of the RxD edge change. It is used in the
baud rate detection process. (RO)
NE
N_
O
W L
RT XO E_ FF
_C
W FF N
LO E
R FO _X F
UA T_ RC ON
UA T_ RC _XO
_S NO XO
_F _D
UA T_ ND OF
R SE _X
R FO E
UA T_ ND
R SE
d)
ve
UA T_
r
se
R
UA
(re
31 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_FORCE_XOFF Set this bit to set the internal CTSn and stop the transmitter from sending data.
(R/W)
UART_FORCE_XON Set this bit to clear the internal CTSn and enable the transmitter to continue
sending data. (R/W)
UART_XONOFF_DEL Set this bit to remove the flow-control char from the received data. (R/W)
UART_SW_FLOW_CON_EN Set this bit to enable software flow control. It is used with register
sw_xon or sw_xoff. (R/W)
LD
HO
ES
HR
_T
VE
TI
C
)
ed
_A
rv
RT
se
UA
(re
31 10 9 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0F0 Reset
UART_ACTIVE_THRESHOLD When the number of positive edges of RxD signal is larger than or
equal to (UART_ACTIVE_THRESHOLD+2), the system emerges from Light-sleep mode and be-
comes active. (R/W)
LD
LD
HO
HO
ES
S
R
RE
HA
HR
A
CH
TH
_C
_T
N_
N_
FF
FF
O
XO
X
_X
_X
T_
T_
RT
RT
R
R
UA
UA
UA
UA
31 24 23 16 15 8 7 0
UART_XOFF_CHAR This register stores the Xoff flow control char. (R/W)
UART_XON_CHAR This register stores the Xon flow control char. (R/W)
UART_XOFF_THRESHOLD When the data amount in receive-FIFO is more than what this register
indicates, it will send an Xoff char, with uart_sw_flow_con_en set to 1. (R/W)
UART_XON_THRESHOLD When the data amount in receive-FIFO is less than what this register in-
dicates, it will send an Xon char, with uart_sw_flow_con_en set to 1. (R/W)
D
RH
UM
M
TH
NU
_N
E_
K_
LE
DL
BR
ID
I
X_
X_
X_
)
ed
_R
_T
_T
rv
RT
RT
RT
se
UA
UA
UA
(re
31 28 27 20 19 10 9 0
UART_TX_BRK_NUM This register is used to configure the number of zeros (0) sent, after the process
of sending data is completed. It is active when txd_brk is set to 1. (R/W)
UART_TX_IDLE_NUM This register is used to configure the duration between transfers. (R/W)
UART_RX_IDLE_THRHD When the receiver takes more time to receive Byte data than what this
register indicates, it will produce a frame-end signal. (R/W)
UA _ _ _ TX M
UM
EN N
RT DL1 5TX Y_ _NU
RT DL0 EN RX_ _E
_N
UA T_ 48 XB LY
LY
R S R D
_D
N
UA _ 48 X
TX
R T S _R
_E
S4 N
5_
5
5
85
_ R _E
48
UA _ 8 4
RS
RT RS
d)
R
R
ve
T_
UA T_
r
se
R
UA
UA
(re
31 10 9 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UART_RS485_TX_DLY_NUM This register is used to delay the transmitter’s internal data signal.
(R/W)
UART_RS485_RX_DLY_NUM This register is used to delay the receiver’s internal data signal. (R/W)
UART_RS485RXBY_TX_EN 1: enable the RS-485 transmitter to send data, when the RS-485 re-
ceiver line is busy; 0: the RS-485 transmitter should not send data, when its receiver is busy.
(R/W)
UART_RS485TX_RX_EN Set this bit to enable the transmitter’s output signal loop back to the re-
ceiver’s input signal. (R/W)
UART_DL1_EN Set this bit to delay the STOP bit by 1 bit. (R/W)
UART_DL0_EN Set this bit to delay the STOP bit by 1 bit after DL1. (R/W)
_P
e
rv
RT
se
UA
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0186A00 Reset
UART_PRE_IDLE_NUM This register is used to configure the idle-time duration before the first
at_cmd is received by the receiver. When the duration is less than what this register indicates,
it will not take the next data received as an at_cmd char. (R/W)
M
NU
E_
DL
_I
ST
PO
d)
ve
T_
er
R
s
UA
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0186A00 Reset
UART_POST_IDLE_NUM This register is used to configure the duration between the last at_cmd
and the next data. When the duration is less than what this register indicates, it will not take the
previous data as an at_cmd char. (R/W)
UT
O
_T
AP
G
X_
d)
_R
ve
RT
r
se
UA
(re
31 24 23 0
0 0 0 0 0 0 0 0 0x0001E00 Reset
UART_RX_GAP_TOUT This register is used to configure the interval between the at_cmd chars.
When the interval is greater than the value of this register, it will not take the data as continuous
at_cmd chars. The register should be configured to more than half of the baud rate. (R/W)
D_
R_
MC
HA
T_
d)
_C
_A
e
rv
RT
RT
se
UA
UA
(re
31 16 15 8 7 0
UART_CHAR_NUM This register is used to configure the number of continuous at_cmd chars re-
ceived by the receiver. (R/W)
UART_AT_CMD_CHAR This register is used to configure the content of an at_cmd char. (R/W)
D
RH
HD
H3
_H
3
_H
TH
_H
HR
D_
LD
LD
Y_
HD
_T
RH
HO
HO
PT
LL
HR
TH
ES
M
_T
RE
_F
_E
_
HR
W
UT
D
EM
EM
TH
E
ZE
O
_T
_P
IZ
TO
FL
M
N_
SI
M
FF
EM
X_
X_
X_
X_
X_
X_
O
XO
)
UA ed)
d
ed
_M
R
_R
_R
_R
_X
_T
_T
ve
T_
T_
rv
rv
RT
RT
RT
RT
RT
RT
RT
er
se
se
R
R
s
UA
UA
UA
UA
UA
UA
UA
UA
(re
(re
(re
31 30 28 27 25 24 23 22 21 20 18 17 15 14 11 10 7 6 3 2 1 0
UART_TX_SIZE This register is used to configure the amount of memory allocated to the transmit-
FIFO. The default number is 128 bytes. (R/W)
UART_RX_SIZE This register is used to configure the amount of memory allocated to the receive-
FIFO. The default number is 128 bytes. (R/W)
UART_MEM_PD Set this bit to power down the memory. When the reg_mem_pd register is set to 1
for all UART controllers, Memory will enter the low-power mode. (R/W)
_C
_C
EM
EM
M
M
X_
X_
d)
_R
_T
e
rv
RT
RT
se
UA
UA
(re
31 6 5 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
NT
_C
IN
M
E_
DG
SE
O
d)
_P
ve
RT
er
s
UA
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x0FFFFF Reset
UART_POSEDGE_MIN_CNT This register stores the count of RxD positive edges. It is used in the
autobaud detection process. (RO)
T
CN
_
IN
M
E_
G
ED
EG
)
ed
_N
rv
RT
se
UA
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x0FFFFF Reset
UART_NEGEDGE_MIN_CNT This register stores the count of RxD negative edges. It is used in the
autobaud detection process. (RO)
N
EP _E EN _E
CI RC _ID N EN
_S D _ OF
UH I_C RT F_E C_
CI EA REC _E
C A O R
UH I_U N_E E_C
UH _H _ LE
_U T E
T0 E
E
ER N
CI AR 2_C
AR 1_C
_C
_E
C E D
UH I_L CO
UH I_U RT
d)
)
C A
C N
ed
ed
UH I_U
ve
UH I_E
rv
rv
er
se
se
C
C
s
UH
UH
(re
(re
(re
31 22 21 20 19 18 17 16 15 12 11 10 9 8 0
0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_SEPER_EN Set this bit to use a special char and separate the data frame. (R/W)
UHCI_UART2_CE Set this bit to use UART2 and transmit or receive data. (R/W)
UHCI_UART1_CE Set this bit to use UART1 and transmit or receive data. (R/W)
UHCI_UART0_CE Set this bit to use UART and transmit or receive data. (R/W)
UH I_I SU EO INT W W
C N_ O IN N _R
CI X_ NG INT AW W
C X N NT T_ W
C U C _ Y_ IN
C N_ R_ _ A A
C N_ S M R _
UH I_T _HU G_ _R RA
UH I_R _HU E_I _IN RA
W
T_ W
T_ T_R W
X_ AR IN AW
RA
IN A
C N_ C F _R
AR IN RA
C U C O F_
C X N F T_
_R ST _ _R
UH _O S _E O
ST T_ T_
CI N_D INK L_E
UH I_I TL TA
C U O
UH I_O T_T
C U
d)
UH I_O
ve
er
C
s
UH
(re
31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_IN_DSCR_ERR_INT_RAW The raw interrupt status bit for the UHCI_IN_DSCR_ERR_INT in-
terrupt. (RO)
UHCI_OUT_EOF_INT_RAW The raw interrupt status bit for the UHCI_OUT_EOF_INT interrupt. (RO)
UHCI_OUT_DONE_INT_RAW The raw interrupt status bit for the UHCI_OUT_DONE_INT interrupt.
(RO)
UHCI_IN_ERR_EOF_INT_RAW The raw interrupt status bit for the UHCI_IN_ERR_EOF_INT interrupt.
(RO)
UHCI_IN_SUC_EOF_INT_RAW The raw interrupt status bit for the UHCI_IN_SUC_EOF_INT inter-
rupt. (RO)
UHCI_IN_DONE_INT_RAW The raw interrupt status bit for the UHCI_IN_DONE_INT interrupt. (RO)
UHCI_TX_HUNG_INT_RAW The raw interrupt status bit for the UHCI_TX_HUNG_INT interrupt. (RO)
UHCI_RX_HUNG_INT_RAW The raw interrupt status bit for the UHCI_RX_HUNG_INT interrupt. (RO)
UHCI_TX_START_INT_RAW The raw interrupt status bit for the UHCI_TX_START_INT interrupt. (RO)
UHCI_RX_START_INT_RAW The raw interrupt status bit for the UHCI_RX_START_INT interrupt.
(RO)
C U O R _ _ T
UH I_I TL TA _Q INT _IN
C N_ O IN N _S
C U O EG _ M
C U C O F_ _S
C U C _ Y_ IN
C N_ S M R _
C N_ R_ _ T T
UH I_O T_T _R _Q _W
UH I_T _HU G_ _S ST
UH I_R _HU E_I _IN ST
UH I_T DO _EO _IN T
C U _S EG LL
ST
C N_ C F _S
C X N NT T_
IN T
AR IN ST
C X N F T_
X_ AR IN T
CI X_ NG INT T
T_ T_S
_R ST _ _S
UH I_O ND _R FU
T_
UH I_I SU EO INT
ST T_ T_
C E _A O_
UH _S D IF
CI EN INF
UH I_S A_
C M
)
ed
UH I_D
rv
se
C
UH
(re
31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_IN_DSCR_ERR_INT_ST The masked interrupt status bit for the UHCI_IN_DSCR_ERR_INT in-
terrupt. (RO)
UHCI_OUT_EOF_INT_ST The masked interrupt status bit for the UHCI_OUT_EOF_INT interrupt.
(RO)
UHCI_OUT_DONE_INT_ST The masked interrupt status bit for the UHCI_OUT_DONE_INT interrupt.
(RO)
UHCI_IN_ERR_EOF_INT_ST The masked interrupt status bit for the UHCI_IN_ERR_EOF_INT inter-
rupt. (RO)
UHCI_IN_SUC_EOF_INT_ST The masked interrupt status bit for the UHCI_IN_SUC_EOF_INT inter-
rupt. (RO)
UHCI_IN_DONE_INT_ST The masked interrupt status bit for the UHCI_IN_DONE_INT interrupt. (RO)
UHCI_TX_HUNG_INT_ST The masked interrupt status bit for the UHCI_TX_HUNG_INT interrupt.
(RO)
UHCI_RX_HUNG_INT_ST The masked interrupt status bit for the UHCI_RX_HUNG_INT interrupt.
(RO)
UHCI_TX_START_INT_ST The masked interrupt status bit for the UHCI_TX_START_INT interrupt.
(RO)
UHCI_RX_START_INT_ST The masked interrupt status bit for the UHCI_RX_START_INT interrupt.
(RO)
A
UH I_O DS K_E EO INT NA _EN
UH _O S R T _ NA
UH I_I TL TA _Q INT _IN
UH I_I SU EO INT A A
CI N_D SC MP RR _E
C N_ O IN N _E
C U O EG _ M
C U C O F_ _E
C U C _ Y_ IN
C N_ R_ _ N N
CI X_ NG INT NA A
C X N NT T_ A
UH I_O T_T _R _Q _W
UH I_T _HU G_ _E EN
UH I_R _HU E_I _IN EN
A
T_ A
T_ T_E A
X_ AR IN NA
EN
C U _S EG LL
IN N
AR IN EN
C N_ C F _E
C X N F T_
_R ST _ _E
UH I_O ND _R FU
ST T_ T_
C E _A O_
UH _S D IF
CI EN INF
UH I_S A_
C M
d)
UH I_D
ve
er
C
s
UH
(re
31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UHCI_OUT_EOF_INT_ENA The interrupt enable bit for the UHCI_OUT_EOF_INT interrupt. (R/W)
UHCI_OUT_DONE_INT_ENA The interrupt enable bit for the UHCI_OUT_DONE_INT interrupt. (R/W)
UHCI_IN_DONE_INT_ENA The interrupt enable bit for the UHCI_IN_DONE_INT interrupt. (R/W)
UHCI_TX_HUNG_INT_ENA The interrupt enable bit for the UHCI_TX_HUNG_INT interrupt. (R/W)
UHCI_RX_HUNG_INT_ENA The interrupt enable bit for the UHCI_RX_HUNG_INT interrupt. (R/W)
UHCI_TX_START_INT_ENA The interrupt enable bit for the UHCI_TX_START_INT interrupt. (R/W)
UHCI_RX_START_INT_ENA The interrupt enable bit for the UHCI_RX_START_INT interrupt. (R/W)
R
UH I_O DS K_E EO INT LR _CL
C U O R _ _ L
UH _O S R T _ LR
UH I_O T_E R_E ERR INT T_C
UH I_I TL TA _Q INT _IN
UH I_I SU EO INT R R
C N_ O IN N _C
C U C O F_ _C
C U O EG _ M
C U C _ Y_ IN
C N_ R_ _ L L
CI X_ NG INT LR R
C X N NT T_ R
UH I_O T_T _R _Q _W
UH I_T _HU G_ _C CL
UH I_R _HU E_I _IN CL
R
T_ R
T_ T_C R
X_ AR IN LR
CL
C U _S EG LL
C N_ C F _C
IN L
AR IN CL
C X N F T_
_R ST _ _C
UH I_O ND _R FU
ST T_ T_
C E _A O_
UH I_S ND FIF
C E IN
UH I_S A_
C M
d)
UH I_D
ve
er
C
s
UH
(re
31 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UL Y
_F PT
L
UT M
_O _E
CI UT
d)
UH I_O
ve
r
se
C
UH
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Reset
TA
H
DA
US
_W
_P
O
FO
F
FI
FI
UT
UT
d)
)
ed
_O
_O
ve
rv
r
CI
CI
se
se
UH
UH
(re
(re
31 17 16 15 9 8 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000 Reset
UHCI_OUTFIFO_PUSH Set this bit to push data into DMA FIFO. (R/W)
UHCI_OUTFIFO_WDATA This is the data that need to be pushed into DMA FIFO. (R/W)
DA
O
_R
_P
O
FO
IF
FI
NF
)
d)
ed
IN
e
_I
rv
rv
_
CI
CI
se
se
UH
UH
(re
(re
31 17 16 15 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x0000 Reset
UHCI_INFIFO_POP Set this bit to pop data from DMA FIFO. (R/W)
UHCI_INFIFO_RDATA This register stores the data popping from DMA FIFO. (RO)
_S RT T
NK TA R
LI _S TA
R
P
_O L _R K
DD
TO
UT INK ES
CI UT INK AR
UH I_O TL K_P
_A
NK
C U IN
LI
UH _O L
CI UT
UT
)
ed
UH I_O
O
rv
_
CI
se
C
UH
UH
(re
31 30 29 28 27 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset
UHCI_OUTLINK_PARK 1: the outlink descriptor’s FSM is in idle state; 0: the outlink descriptor’s FSM
is working. (RO)
UHCI_OUTLINK_RESTART Set this bit to restart the outlink descriptor from the last address. (R/W)
UHCI_OUTLINK_STOP Set this bit to stop dealing with the outlink descriptor. (R/W)
UHCI_OUTLINK_ADDR This register stores the least significant 20 bits of the first outlink descriptor’s
address. (R/W)
DR
P
CI NLI _R K
NL _ T
O
_I NK ES
UH I_I INK PAR
D
_A
C NL _
UH I_I INK
K
IN
C NL
NL
)
ed
UH I_I
_I
rv
CI
se
C
UH
UH
(re
31 30 29 28 27 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0x000000 Reset
UHCI_INLINK_PARK 1: the inlink descriptor’s FSM is in idle state; 0: the inlink descriptor’s FSM is
working. (RO)
UHCI_INLINK_START Set this bit to start dealing with the inlink descriptors. (R/W)
UHCI_INLINK_STOP Set this bit to stop dealing with the inlink descriptors. (R/W)
UHCI_INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor’s
address. (R/W)
E
_R
SU E
N
M
UM N
K_ _R
_E
_S Q_E
EC UM
CK SE
CH N
(re TX_ CK_
HE K_
_C C
_ A
CI HE
CI X_
)
UH ed)
ed
UH I_C
UH I_T
rv
rv
se
se
C
C
UH
(re
31 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SC EN
N
UH _R DB SC N
UH I_T _C0 ES EN
_T DB C N
C0 S N
_E
CI X_ _E _E
CI X_ _ES _E
X_ _E _E
C X _ C_
C X _E _
_E C_
C X _ _
UH I_R _11 SC
C X _E
UH I_R _13
)
C X
ed
UH I_R
rv
se
C
UH
(re
31 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 Reset
UHCI_RX_13_ESC_EN Set this bit to enable replacing flow control char 0x13, when DMA sends data.
(R/W)
UHCI_RX_11_ESC_EN Set this bit to enable replacing flow control char 0x11, when DMA sends data.
(R/W)
UHCI_RX_DB_ESC_EN Set this bit to enable replacing 0xdb char, when DMA sends data. (R/W)
UHCI_RX_C0_ESC_EN Set this bit to enable replacing 0xc0 char, when DMA sends data. (R/W)
UHCI_TX_13_ESC_EN Set this bit to enable decoding flow control char 0x13, when DMA receives
data. (R/W)
UHCI_TX_11_ESC_EN Set this bit to enable decoding flow control char 0x11, when DMA receives
data. (R/W)
UHCI_TX_DB_ESC_EN Set this bit to enable decoding 0xdb char, when DMA receives data. (R/W)
UHCI_TX_C0_ESC_EN Set this bit to enable decoding 0xc0 char, when DMA receives data. (R/W)
FT
FT
NA
NA
HI
HI
_S
_E
_S
_E
UT
UT
UT
UT
UT
UT
EO
EO
EO
EO
EO
EO
IM
IM
IM
IM
IM
IM
_T
_T
_T
_T
_T
_T
FO
O
IF
IF
IF
IF
IF
FI
XF
XF
XF
XF
XF
)
RX
ed
_R
_R
_T
_T
_T
rv
_
CI
CI
CI
CI
CI
CI
se
UH
UH
UH
UH
UH
UH
(re
31 24 23 22 20 19 12 11 10 8 7 0
UHCI_RXFIFO_TIMEOUT_ENA This is the enable bit for DMA send-data timeout. (R/W)
UHCI_RXFIFO_TIMEOUT_SHIFT The tick count is cleared when its value is equal to or greater than
(17’d8000»reg_rxfifo_timeout_shift). (R/W)
UHCI_RXFIFO_TIMEOUT This register stores the timeout value. When DMA takes more time to read
data from RAM than what this register indicates, it will produce the UHCI_RX_HUNG_INT interrupt.
(R/W)
UHCI_TXFIFO_TIMEOUT_SHIFT The tick count is cleared when its value is equal to or greater than
(17’d8000»reg_txfifo_timeout_shift). (R/W)
UHCI_TXFIFO_TIMEOUT This register stores the timeout value. When DMA takes more time to
receive data than what this register indicates, it will produce the UHCI_TX_HUNG_INT interrupt.
(R/W)
0
AR
HA
CH
C
2_
2_
2
Q
EQ
EQ
SE
_S
_S
C_
SC
SC
)
ES
d
ve
_E
_E
I_
r
CI
CI
se
C
UH
UH
UH
(re
31 24 23 16 15 8 7 0
UHCI_ESC_SEQ2_CHAR1 This register stores the second char used to replace the reg_esc_seq2 in
data. (R/W)
UHCI_ESC_SEQ2_CHAR0 This register stores the first char used to replace the reg_esc_seq2 in
data. (R/W)
UHCI_ESC_SEQ2 This register stores the flow_control char to turn off the flow_control. (R/W)
14. LED_PWM
14.1 Introduction
The LED_PWM controller is primarily designed to control the intensity of LEDs, although it can be used to
generate PWM signals for other purposes as well. It has 16 channels which can generate independent
waveforms that can be used to drive RGB LED devices. For maximum flexibility, the high-speed as well as the
low-speed channels can be driven from one of four high-speed/low-speed timers. The PWM controller also has
the ability to automatically increase or decrease the duty cycle gradually, allowing for fades without any processor
interference. To increase resolution, the LED_PWM controller is also able to dither between two values, when a
fractional PWM value is configured.
The LED_PWM controller has eight high-speed and eight low-speed PWM generators. In this document, they will
be referred to as hschn and lschn, respectively. These channels can be driven from four timers which will be
indicated by h_timerx and l_timerx.
Figure 86 illustrates a PWM channel with its selected timer; in this instance a high-speed channel and associated
high-speed timer.
14.2.2 Timers
A high-speed timer consists of a multiplexer to select one of two clock sources: either REF_TICK or APB_CLK.
For more information on the clock sources, please see Chapter Reset And Clock. The input clock is divided
down by a divider first. The division factor is specified by LEDC_CLK_DIV_NUM_HSTIMERx which contains a
fixed point number: the highest 10 bits represent the integer portion A, while the lowest eight bits contain the
fractional portion B. The effective division factor is as follows:
B
LEDC_CLK_DIV _N U M _HST IM ERx = A 256
Figure 87 shows the input/output clock when the fractional portion B is not 0. As shown in the firgure, the 256
output clocks consist of B output clocks as result of division by (A+1) divider and (256-B) output clocks as result
of division by A divider. The B output clocks are evenly distributed in the 256 output clocks.
The output clock of the divider is the base clock for the counter which will count up to the value specified in
LEDC_HSTIMERx_DUTY_RES. An overflow interrupt will be generated once the counting value reaches
2LEDC_HST IM ERx_DU T Y _RES − 1, at which point the counter restarts counting from 0. It is also possible to
reset, suspend, and read the values of the counter by software.
The output signal of the timer is the 20-bit value generated by the counter. The cycle period of this signal defines
the frequency of the signals of any PWM channels connected to this timer. This frequency depends on both the
division factor of the divider, as well as the range of the counter:
The low-speed timers l_timerx on the low-speed channel differ from the high-speed timers h_timerx in two
aspects:
1. Where the high-speed timer clock source can be clocked from REF_TICK or APB_CLK, the low-speed
timers are sourced from either REF_TICK or SLOW_CLOCK. The SLOW_CLOCK source can be either
APB_CLK (80 MHz) or 8 MHz, and can be selected using LEDC_APB_CLK_SEL.
2. The high-speed counter and divider are glitch-free, which means that if the software modifies the maximum
counter or divisor value, the update will come into effect after the next overflow interrupt. In contrast, the
low-speed counter and divider will update these values only when LEDC_LSTIMERx_PARA_UP is set.
14.2.3 Channels
A channel takes the 20-bit value from the counter of the selected high-speed timer and compares it to a set of
two values in order to set the channel output. The first value it is compared to is the content of
LEDC_HPOINT_HSCHn; if these two match, the output will be latched high. The second value is the sum of
LEDC_HPOINT_HSCHn and LEDC_DUTY_HSCHn[24..4]. When this value is reached, the output is latched low.
By using these two values, the relative phase and the duty cycle of the PWM output can be set. Figure 88
illustrates this.
LEDC_DUTY_HSCHn is a fixed-point register with four fractional bits. As mentioned before, when
LEDC_DUTY_HSCHn[24..4] is used in the PWM calculation directly, LEDC_DUTY_HSCHn[3..0] can be used to
dither the output. If this value is non-zero, with a statistical chance of LEDC_DUTY_HSCHn[3..0]/16, the actual
PWM pulse will be one cycle longer. This effectively increases the resolution of the PWM generator to 25 bits, but
at the cost of a slight jitter in the duty cycle.
The channels also have the ability to automatically fade from one duty cycle value to another. This feature is
enabled by setting LEDC_DUTY_START_HSCHn. When this bit is set, the PWM controller will automatically
increment or decrement the value in LEDC_DUTY_HSCHn, depending on whether the bit
LEDC_DUTY_INC_HSCHn is set or cleared, respectively. The speed the duty cycle changes is defined as such:
every time the LEDC_DUTY_CYCLE_HSCHn cycles, the content of LEDC_DUTY_SCALE_HSCHn is added to or
subtracted from LEDC_DUTY_HSCHn[24..4]. The length of the fade can be limited by setting
LEDC_DUTY_NUM_HSCHn: the fade will only last that number of cycles before finishing. A finished fade also
generates an interrupt.
Notes
• When LEDC is in fade mode, configure the second fade only after LEDC_DUTY_CHNG_END_HSCHn or
LEDC_DUTY_CHNG_END_LSCHn interrupt is generated.
• When LEDC is in decremental fade mode and LEDC_DUTY_HSCHn is 2LEDC_HST IM ERx_DU T Y _RES ,
LEDC_DUTY_SCALE_HSCHn cannot be set to 1. When LEDC is in decremental fade mode and
LEDC_DUTY_LSCHn is 2LEDC_LST IM ERx_DU T Y _RES , LEDC_DUTY_SCALE_LSCHn cannot be set to 1.
14.2.4 Interrupts
• LEDC_DUTY_CHNG_END_LSCHn_INT: Triggered when a fade on a low-speed channel has finished.
• LEDC_HS_TIMERx_OVF_INT: Triggered when a high-speed timer has reached its maximum counter value.
• LEDC_LS_TIMERx_OVF_INT: Triggered when a low-speed timer has reached its maximum counter value.
14.4 Registers
_H Hn
Hn
EL SC
SC
IM T_E Hn
_S _H
U SC
N
DC _O _H
LE SIG _LV
ER
_ E
DC IDL
)
ed
_T
LE C_
rv
se
D
LE
(re
31 4 3 2 1 0
0x00000000 0 0 0 Reset
LEDC_IDLE_LV_HSCHn This bit is used to control the output value when high-speed channel n is
inactive. (R/W)
LEDC_SIG_OUT_EN_HSCHn This is the output enable control bit for high-speed channel n. (R/W)
LEDC_TIMER_SEL_HSCHn There are four high-speed timers. These two bits are used to select one
of them for high-speed channel n: (R/W)
0: select hstimer0;
1: select hstimer1;
2: select hstimer2;
3: select hstimer3.
_H
rv
DC
se
LE
(re
31 20 19 0
LEDC_HPOINT_HSCHn The output value changes to high when htimerx(x=[0,3]), selected by high-
speed channel n, has reached LEDC_HPOINT_HSCHn[19:0]. (R/W)
Hn
SC
_H
Y
UT
d)
_D
ve
DC
er
s
LE
(re
31 25 24 0
LEDC_DUTY_HSCHn The register is used to control output duty. When hstimerx(x=[0,3]), selected
by high-speed channel n, has reached LEDC_LPOINT_HSCHn, the output signal changes to low.
(R/W)
LEDC_LPOINT_HSCHn=LEDC_LPOINT_HSCHn[19:0]+LEDC_DUTY_HSCHn[24:4] (1)
LEDC_LPOINT_HSCHn=LEDC_LPOINT_HSCHn[19:0]+LEDC_DUTY_HSCHn[24:4] +1) (2)
See the Functional Description for more information on when (1) or (2) is chosen.
n
CH H n
CH
CH
Hn
HS SC
n
HS
HS
SC
C_ H
E_
E_
IN T_
_H
CL
AL
Y_ AR
M
NU
SC
CY
UT _ST
Y_
Y_
Y_
_D TY
UT
UT
UT
DC DU
_D
_D
_D
LE C_
DC
DC
DC
D
LE
LE
LE
31 30 29 20 19 10 9 LE 0
LEDC_DUTY_INC_HSCHn This register is used to increase or decrease the duty of output signal for
high-speed channel n. (R/W)
LEDC_DUTY_NUM_HSCHn This register is used to control the number of times the duty cycle is
increased or decreased for high-speed channel n. (R/W)
LEDC_DUTY_CYCLE_HSCHn This register is used to increase or decrease the duty cycle every time
LEDC_DUTY_CYCLE_HSCHn cycles for high-speed channel n. (R/W)
LEDC_DUTY_SCALE_HSCHn This register is used to increase or decrease the step scale for high-
speed channel n. (R/W)
_R
Hn
SC
Y_H
UT
d)
_D
ve
DC
er
s
LE
(re
31 25 24 0
LEDC_DUTY_HSCHn_R This register represents the current duty cycle of the output signal for high-
speed channel n. (RO)
_L Hn
Hn
C
U SC n
_S _LS
SC
DC _O _L CH
IM T_E Hn
LE SIG _LV LS
N
EL
_ E P_
DC IDL _U
ER
LE C_ RA
d)
D PA
_T
ve
LE C_
r
se
D
LE
(re
31 5 4 3 2 1 0
0x0000000 0 0 0 0 Reset
LEDC_IDLE_LV_LSCHn This bit is used to control the output value, when low-speed channel n is
inactive. (R/W)
LEDC_SIG_OUT_EN_LSCHn This is the output enable control bit for low-speed channel n. (R/W)
LEDC_TIMER_SEL_LSCHn There are four low-speed timers, the two bits are used to select one of
them for low-speed channel n. (R/W)
0: select lstimer0;
1: select lstimer1;
2: select lstimer2;
3: select lstimer3.
n
CH
LS
T_
IN
PO
)
ed
_H
rv
DC
se
LE
31
(re 20 19 0
LEDC_HPOINT_LSCHn The output value changes to high when lstimerx(x=[0,3]), selected by low-
speed channel n, has reached LEDC_HPOINT_LSCHn[19:0]. (R/W)
n
CH
LS
Y_
UT
d)
_D
ve
DC
r
se
LE
(re
31 25 24 0
LEDC_DUTY_LSCHn The register is used to control output duty. When lstimerx(x=[0,3]), chosen by
low-speed channel n, has reached LEDC_LPOINT_LSCHn,the output signal changes to low. (R/W)
LEDC_LPOINT_LSCHn=(LEDC_HPOINT_LSCHn[19:0]+LEDC_DUTY_LSCHn[24:4]) (1)
LEDC_LPOINT_LSCHn=(LEDC_HPOINT_LSCHn[19:0]+LEDC_DUTY_LSCHn[24:4] +1) (2)
See the Functional Description for more information on when (1) or (2) is chosen.
n
CH Hn
CH
CH
Hn
LS SC
n
LS
LS
SC
C_ L
E_
IN T_
_L
LE
AL
Y_ AR
YC
NU
SC
UT _ST
_C
Y_
Y_
_D TY
TY
UT
UT
DC DU
DU
_D
_D
LE C_
C_
DC
DC
D
D
LE
LE
LE
LE
31 30 29 20 19 10 9 0
LEDC_DUTY_INC_LSCHn This register is used to increase or decrease the duty of output signal for
low-speed channel n. (R/W)
LEDC_DUTY_NUM_LSCHn This register is used to control the number of times the duty cycle is
increased or decreased for low-speed channel n. (R/W)
LEDC_DUTY_SCALE_LSCHn This register is used to increase or decrease the step scale for low-
speed channel n. (R/W)
_D
e
rv
DC
se
LE
(re
31 25 24 0
LEDC_DUTY_LSCHn_R This register represents the current duty of the output signal for low-speed
channel n. (RO)
x
ER
ES
IM
x _ T Rx
ST
_R
ER RS E
E
IM x_ TIM
_H
Y
US
UT
M
PA
ST ER HS
D
NU
x_
_H TIM L_
V_
ER
DC HS SE
DI
IM
LE C_ K_
K_
ST
D TIC
CL
)
ed
_H
LE C_
_
rv
DC
DC
se
D
LE
LE
LE
(re
31 26 25 24 23 22 5 4 0
LEDC_TICK_SEL_HSTIMERx This bit is used to select APB_CLK or REF_TICK for high-speed timer
x. (R/W)
1: APB_CLK;
0: REF_TICK.
LEDC_HSTIMERx_RST This bit is used to reset high-speed timer x. The counter value will be ’zero’
after reset. (R/W)
LEDC_HSTIMERx_PAUSE This bit is used to suspend the counter in high-speed timer x. (R/W)
LEDC_CLK_DIV_NUM_HSTIMERx This register is used to configure the division factor for the divider
in high-speed timer x. The least significant eight bits represent the fractional part. (R/W)
LEDC_HSTIMERx_DUTY_RES This register is used to control the range of the counter in high-speed
timer x. The counter range is [0, 2LEDC_HST IM ERx_DU T Y _RES ], the maximum bit width for counter
is 20. (R/W)
_H
e
rv
DC
se
LE
(re
31 20 19 0
0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LEDC_HSTIMERx_CNT Software can read this register to get the current counter value of high-speed
timer x. (RO)
x
ER
S
M
x _ T Rx
IM x_ TIM P
RE
TI
ST ER LS _U
S
ER RS E
Y_
_L
US
_L TIM L_ RA
T
M
DU
DC LS SE PA
PA
NU
LE C_ K_ Rx_
x_
V_
ER
D TIC E
DI
LE C_ TIM
IM
K_
ST
CL
d)
D LS
_L
ve
LE C_
_
DC
DC
er
D
s
LE
LE
LE
(re
31 27 26 25 24 23 22 5 4 0
LEDC_TICK_SEL_LSTIMERx This bit is used to select SLOW_CLK or REF_TICK for low-speed timer
x. (R/W)
1: SLOW_CLK;
0: REF_TICK.
LEDC_LSTIMERx_RST This bit is used to reset low-speed timer x. The counter will show 0 after
reset. (R/W)
LEDC_LSTIMERx_PAUSE This bit is used to suspend the counter in low-speed timer x. (R/W)
LEDC_CLK_DIV_NUM_LSTIMERx This register is used to configure the division factor for the divider
in low-speed timer x. The least significant eight bits represent the fractional part. (R/W)
LEDC_LSTIMERx_DUTY_RES This register is used to control the range of the counter in low-speed
timer x. The counter range is [0, 2LEDC_LST IM ERx_DU T Y _RES ], the max bit width for counter is
20. (R/W)
_L
rv
DC
se
LE
(re
31 20 19 0
0x0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LEDC_LSTIMERx_CNT Software can read this register to get the current counter value of low-speed
timer x. (RO)
31
31
0
0
0
0
14. LED_PWM
0
0
Espressif Systems
(re (re
0
0
se se
rv rv
e ed
0
0
d) )
interrupt. (RO)
interrupt. (RO)
interrupt. (RO)
interrupt. (RO)
0
0
0
24
0
24
0
0
23
23
LE LE
D D
0
0
22
22
LE C_ LE C_
D DU DC DU
0
0
21
21
LE C_ TY LE _ TY
D DU _C D DU _C
0
0
20
20
LE C_ TY HN LE C_ TY HN
D DU _C G D DU _C G
0
0
19
19
LE C_ TY HN _E LE C_ TY HN _E
D DU _C G ND D DU _C G ND
0
0
18
18
LE C_ TY HN _E _L LE C_ TY HN _E _L
D DU _C G ND SC D DU _C G ND SC
0
0
17
17
LE C_ TY HN _E _L H7 LE C_ TY HN _E _L H7
D DU _C G ND SC _ D DU _C G ND SC _
0
0
16
16
LE C_ TY HN _E _L H6 INT LE C_ TY HN _E _L H6 INT
D DU _C G ND SC _ _S D DU _C G ND SC _ _R
0
0
15
15
LEDC_DUTY_CHNG_END_LSCHn_INT_ST The
LEDC_DUTY_CHNG_END_HSCHn_INT_ST The
LE C_ TY HN _E _L H5 INT T LE C_ TY HN _E _L H5 INT AW
D DU _C G ND SC _ _S D DU _C G ND SC _ _R
396
LEDC_DUTY_CHNG_END_LSCHn_INT_RAW The
0
0
14
14
LEDC_DUTY_CHNG_END_HSCHn_INT_RAW The
LE C_ TY HN _E _L H4 INT T LE C_ TY HN _E _L H4 INT AW
D DU _C G ND SC _ _S D DU _C G ND SC _ _R
0
0
13
13
LE C_ TY HN _E _L H3 INT T LE C_ TY HN _E _L H3 INT AW
D DU _C G ND SC _ _S D DU _C G ND SC _ _R
0
0
12
12
LE C_ TY HN _E _L H2 INT T LE C_ TY HN _E _L H2 INT AW
raw
raw
D DU _C G ND SC _ _S D DU _C G ND SC _ _R
masked
masked
0
0
11
11
LE C_ TY HN _E _L H1 INT T LE C_ TY HN _E _L H1 INT AW
D DU _C G ND SC _ _S D DU _C G ND SC _ _R
0
0
10
10
9
9
0
0
LE C_ TY HN _E _H CH INT T LE C_ TY HN _E _H CH INT AW
D DU _C G ND S 7_ _S D DU _C G ND S 7_ _R
8
8
0
0
LE C_ TY HN _E _H CH INT T LE C_ TY HN _E _H CH INT AW
interrupt
interrupt
D DU _C G ND S 6_ _ D DU _C G ND S 6_ _
interrupt
interrupt
7
7
0
0
DC DU _C G ND SC 5_ _S DC DU _C G ND SC 5_ _R
6
6
0
0
LE _ TY HN _E _H H INT T LE _ TY HN _E _H H INT AW
D LS _C G ND S 4_ _ D LS _C G ND S 4_ _
5
5
0
0
status
D LS E G ND S 3_ _ D LS E G ND S 3_ _
status
status
4
4
0
0
3
3
0
0
bit
D LS E _O _IN S 1_ _ D LS E _O _IN S 1_ _
bit
bit
2
2
0
0
1
1
0
0
for
for
for
T
0
0
LE C_ TIM R3 VF T_ T LE C_ TIM R3 VF T_ AW AW
DC HS E _O _IN ST DC HS E _O _IN RA
T R V
_H IM 2_ F T_ T R V
_H IM 2_ F T_ W
ST ER O _IN ST ST ER O _IN RA
0 Reset
0 Reset
IM 1_ VF_ T_ IM 1_ VF_ T_ W
ER O IN ST ER O IN RA
0_ VF_ T_ 0_ VF_ T_ W
O IN ST O IN RA
31
31
0
0
0
0
(WO)
14. LED_PWM
0
0
Espressif Systems
(re (re
0
0
se se
rv rv
rupt. (R/W)
rupt. (R/W)
ed ed
0
0
) )
0
0
0
24
0
24
0
0
23
23
LE LE
D D
0
0
22
22
LE C_ LE C_
DC DU DC DU
0
0
21
21
LE _ TY LE _ TY
D DU _C D DU _C
0
0
20
20
LE C_ TY HN LE C_ TY HN
D DU _C G D DU _C G
0
0
19
19
LE C_ TY HN _E LE C_ TY HN _E
D DU _C G ND D DU _C G ND
0
0
18
18
LE C_ TY HN _E _L LE C_ TY HN _E _L
D DU _C G ND SC D DU _C G ND SC
0
0
17
17
LE C_ TY HN _E _L H7 LE C_ TY HN _E _L H7
D DU _C G ND SC _ D DU _C G ND SC _
0
0
16
16
LE C_ TY HN _E _L H6 INT LE C_ TY HN _E _L H6 INT
D DU _C G ND SC _ _C D DU _C G ND SC _ _E
0
0
15
15
LE C_ TY HN _E _L H5 INT LR LE C_ TY HN _E _L H5 INT NA
LEDC_DUTY_CHNG_END_LSCHn_INT_CLR Set
D DU _C G ND SC _ _C D DU _C G ND SC _ _E
LEDC_DUTY_CHNG_END_HSCHn_INT_CLR Set
LEDC_DUTY_CHNG_END_LSCHn_INT_ENA The
397
LEDC_DUTY_CHNG_END_HSCHn_INT_ENA The
0
0
14
14
LE C_ TY HN _E _L H4 INT LR LE C_ TY HN _E _L H4 INT NA
D DU _C G ND SC _ _C D DU _C G ND SC _ _E
0
0
13
13
LE C_ TY HN _E _L H3 INT LR LE C_ TY HN _E _L H3 INT NA
D DU _C G ND SC _ _C D DU _C G ND SC _ _E
0
0
LE C_ TY HN _E _L H2 INT LR LE C_ TY HN _E _L H2 INT NA
LEDC_DUTY_CHNG_END_HSCHn_INT interrupt. (R/W)
D DU _C G ND SC _ _C D DU _C G ND SC _ _E
this
0
0
11
11
this
LE C_ TY HN _E _L H1 INT LR LE C_ TY HN _E _L H1 INT NA
D DU _C G ND SC _ _C D DU _C G ND SC _ _E
0
0
10
10
LE C_ TY HN _E _H H0 INT LR LE C_ TY HN _E _H H0 INT NA
interrupt
D DU _C G ND S _ _C D DU _C G ND S _ _E
9
9
0
0
LE C_ TY HN _E _H CH INT LR LE C_ TY HN _E _H CH INT NA
D DU _C G ND S 7_ _C D DU _C G ND S 7_ _E
8
8
bit
0
0
bit
LE C_ TY HN _E _H CH INT LR LE C_ TY HN _E _H CH INT NA
D DU _C G ND S 6_ _ D DU _C G ND S 6_ _
7
7
0
0
6
6
0
0
enable
enable
LE _ TY HN _E _H H INT LR LE _ TY HN _E _H H INT NA
D LS _C G ND S 4_ _ D LS _C G ND S 4_ _
to
to
5
5
0
0
4
4
0
0
D LS E _O ND S 2_ _ D LS E _O ND S 2_ _
bit
3
3
0
0
2
2
0
0
clear
clear
1
1
0
0
for
0
0
LE C_ TIM R3 VF T_ LR LR LE C_ TIM R3 VF T_ A NA
DC HS E _O _IN CL DC HS E _O _IN EN
T R V
_H IM 2_ F T_ R T R V
_H IM 2_ F T_ A
ST ER O _IN CL ST ER O _IN EN
0 Reset
0 Reset
IM 1_ VF_ T_ R IM 1_ VF_ T_ A
ER O IN CL ER O IN EN
0_ VF_ T_ R 0_ VF_ T_ A
O IN CL O IN EN
EL
S
K_
CL
B_
AP
d)
ve
C_
er
D
s
LE
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
15.1 Introduction
The RMT (Remote Control) module is primarily designed to send and receive infrared remote control signals that
implement on-off keying in a carrier frequency, but due to its design it can be used to generate various types of
signals. An RMT transmitter does this by reading consecutive duration values of an active and inactive output
from the built-in RAM block, optionally modulating it with a carrier wave. A receiver will inspect its input signal,
optionally filtering it, and will place the lengths of time the signal is active and inactive in the RAM block.
The RMT module has eight channels, numbered zero to seven; registers, signals and blocks that are duplicated
in each channel are indicated by an n which is used as a placeholder for the channel number.
The RMT module contains eight channels. Each channel has both a transmitter and a receiver, but only one of
them can be active in every channel. The eight channels share a 512x32-bit RAM block which can be read and
written by the processor cores over the APB bus, read by the transmitters, and written by the receivers. The
transmitted signal can optionally be modulated by a carrier wave. Each channel is clocked by a divided-down
signal derived from either the APB bus clock or REF_TICK.
The data structure in RAM is shown in Figure 91. Each 32-bit value contains two 16-bit entries, with two fields in
every entry, ”level” and ”period”. ”Level” indicates whether a high-/low-level value was received or is going to be
sent, while ”period” points out the divider-clock cycles for which the level lasts. A zero period is interpreted as an
end-marker: the transmitter will stop transmitting once it has read this, and the receiver will write this, once it has
detected that the signal it received has gone idle.
Normally, only one block of 64x32-bit worth of data can be sent or received. If the data size is larger than this
block size, blocks can be extended or the channel can be configured for the wraparound mode.
The RMT RAM can be accessed via the APB bus. The initial address is 0x3FF56800. The RAM block is divided
into eight 64x32-bit blocks. By default, each channel uses one block (block zero for channel zero, block one for
channel one, and so on). Users can extend the memory to a specific channel by configuring the
RMT_MEM_SIZE_CHn register; setting this to >1 will prompt the channel to use the memory of subsequent
channels as well. The RAM address range of channel n is start_addr_CHn to end_addr_CHn, which is defined
by:
To protect a receiver from overwriting the blocks a transmitter is about to transmit, RMT_MEM_OWNER_CHn
can be configured to designate the owner, be it a transmitter or receiver, of channel n’s RAM block. This way, if
this ownership is violated, the RMT_CHn_ERR interrupt will be generated.
Note: When enabling the continuous transmission mode by setting RMT_REG_TX_CONTI_MODE, the
transmitter will transmit the data on the channel continuously, that is, from the first byte to the last one, then from
the first to the last again, and so on. In this mode, there will be an idle level lasting one clk_div cycle between N
and N+1 transmissions.
15.2.3 Clock
The main clock of a channel is generated by taking either the 80 MHz APB clock or REF_TICK (usually 1MHz),
according to the state of RMT_REF_ALWAYS_ON_CHn. (For more information on clock sources, please see
Chapter Reset And Clock.) Then, the aforementioned state gets scaled down using a configurable 8-bit divider to
create the channel clock which is used by both the carrier wave generator and the counter. The divider value can
be set by configuring RMT_DIV_CNT_CHn.
15.2.4 Transmitter
When the RMT_TX_START_CHn register is 1, the transmitter of channel n will start reading and sending data
from RAM. The transmitter will receive a 32-bit value each time it reads from RAM. Of these 32 bits, the low
16-bit entry is sent first and the high entry second.
To transmit more data than can be fitted in the channel’s RAM, the wraparound mode can be enabled. In this
mode, when the transmitter has reached the last entry in the channel’s memory, it will loop back to the first byte.
To use this mechanism for sending more data than can be fitted in the channel’s RAM, fill the RAM with the initial
events and set RMT_CHn_TX_LIM_REG to cause an RMT_CHn_TX_THR_EVENT_INT interrupt before the
wraparound happens. Then, when the interrupt happens, the already sent data should be replaced by
subsequent events, so that when the wraparound happens the transmitter will seamlessly continue sending the
new events.
With or without the wraparound mode enabled, transmission ends when an entry with zero length is
encountered. When this happens, the transmitter will generate an RMT_CHn_TX_END_INT interrupt and return
to the idle state. When a transmitter is in the idle state, the output level defaults to end-mark 0. Users can also
configure RMT_IDLE_OUT_EN_CHn and RMT_IDLE_OUT_LV_CHn to control the output level manually.
The output of the transmitter can be modulated using a carrier wave by setting RMT_CARRIER_EN_CHn. The
carrier frequency and duty cycle can be configured by adjusting the carrier’s high and low durations in
channel-clock cycles, in RMT_CARRIER_HIGH_CHn and RMT_CARRIER_LOW_CHn.
15.2.5 Receiver
When RMT_RX_EN_CHn is set to 1, the receiver in channel n becomes active, measuring the duration between
input signal edges. These will be written as period/level value pairs to the channel RAM in the same fashion as
the transmitter sends them. Receiving ends, when the receiver detects no change in signal level for more than
RMT_IDLE_THRES_CHn channel clock ticks. The receiver will write a final entry with 0 period, generate an
RMT_CHn_RX_END_INT_RAW interrupt and return to the idle state.
The receiver has an input signal filter which can be configured using RMT_RX_FILTER_EN_CHn: The filter will
remove pulses with a length of less than RMT_RX_FILTER_THRES_CHn in APB clock periods.
When the RMT module is inactive, the RAM can be put into low-power mode by setting the RMT_MEM_PD
register to 1.
15.2.6 Interrupts
• RMT_CHn_TX_THR_EVENT_INT: Triggered when the amount of data the transmitter has sent matches the
value of RMT_CHn_TX_LIM_REG.
• RMT_CHn_TX_END_INT: Triggered when the transmitter has finished transmitting the signal.
15.4 Registers
Hn Hn
_C _C
EN _LV
n
CH
n
CH
R_ T
Hn
S_
IE OU
E_
_C
E
RR R_
HR
IZ
T_ AR D
NT
CA RIE
P
_S
_T
RM _C M_
_C
EM
LE
RM _M )
V
T d
T E
ID
DI
RM rve
M
T_
T_
T_
se
RM
RM
RM
(re
31 30 29 28 27 24 23 8 7 0
RMT_MEM_PD This bit is used to power down the entire RMT RAM block. (It only exists in
RMT_CH0CONF0). 1: power down memory; 0: power up memory. (R/W)
RMT_CARRIER_OUT_LV_CHn This bit is used for configuration when the carrier wave is being trans-
mitted. Transmit on low output level with 1, and transmit on high output level with 0. (R/W)
RMT_CARRIER_EN_CHn This is the carrier modulation enable-control bit for channel n. Carrier mod-
ulation is enabled with 1, while carrier modulation is disabled with 0. (R/W)
RMT_MEM_SIZE_CHn This register is used to configure the amount of memory blocks allocated to
channel n. (R/W)
RMT_IDLE_THRES_CHn In receive mode, when no edge is detected on the input signal for longer
than REG_IDLE_THRES_CHn channel clock cycles, the receive process is finished. (R/W)
RMT_DIV_CNT_CHn This register is used to set the divider for the channel clock of channel n. (R/W)
Hn
CH Hn
CH Hn
_C
T_ _C
R_ _C
Hn
n
T d W O Hn
_S _C ST Hn
n
F_ W V_C n
T_ S_O n
ES
RE AL _L CH
RS N
CN AY H
NE DE
TA Hn _C
RM rve M_ TI_ _C
TX N _R C
HR
Hn
T_ _E R T_
T_ EF_ UT N_
se E N EN
W S
O M
_T
_C
RM _R E_O T_E
RM R _ R
(re _M CO R_
ER
T_ EM D_
RT
T X_ TE
T L U
ILT
R
RM ID _O
RM T IL
RM _M M_
_F
T_ _F
T_ LE
d)
RM _M )
E
RX
X
RM _ID
ve
RM R
T_
T_
er
T
s
RM
RM
RM
(re
31 20 19 18 17 16 15 8 7 6 5 4 3 2 1 0
RMT_IDLE_OUT_EN_CHn This is the output enable-control bit for channel n in IDLE state. (R/W)
RMT_IDLE_OUT_LV_CHn This bit configures the level of output signals in channel n when the latter
is in IDLE state. (R/W)
RMT_REF_ALWAYS_ON_CHn This bit is used to select the channel’s base clock. 1:clk_apb;
0:clk_ref. (R/W)
RMT_REF_CNT_RST_CHn Setting this bit resets the clock divider of channel n. (R/W)
RMT_RX_FILTER_THRES_CHn In receive mode, channel n ignores input pulse when the pulse width
is smaller than this value in APB clock periods. (R/W)
RMT_TX_CONTI_MODE_CHn If this bit is set, instead of going to an idle state when transmission
ends, the transmitter will restart transmission. This results in a repeating output signal. (R/W)
RMT_MEM_OWNER_CHn This bit marks channel n’s RAM block ownership. Number 1 indicates
that the receiver is using the RAM, while 0 indicates that the transmitter is using the RAM. (R/W)
RMT_MEM_RD_RST_CHn Set this bit to reset the read-RAM address for channel n by accessing the
transmitter. (R/W)
RMT_MEM_WR_RST_CHn Set this bit to reset the write-RAM address for channel n by accessing
the receiver. (R/W)
31
31
RM RM
T T
0
0
30
30
RM _C RM _C
T H T H
0
0
29
29
RM _C 7_T RM _C 7_T
(RO)
T H X_ T H X_
0
0
28
28
RM _C 6_T TH RM _C 6_T TH
Espressif Systems
T H X_ R T H X_ R
0
0
27
27
rupt. (RO)
rupt. (RO)
rupt. (RO)
RM _C 5_T TH _EV RM _C 5_T TH _EV
T H X_ R E T H X_ R E
0
0
26
26
RM _C 4_T TH _EV NT_ RM _C 4_T TH _EV NT_
T H X_ R E IN T H X_ R E IN
0
0
25
25
RM _C 3_T TH _EV NT_ T_ RM _C 3_T TH _EV NT_ T_
T H X_ R E IN ST T H X_ R E IN RA
0
0
24
24
RM _C 2_T TH _EV NT_ T_ RM _C 2_T TH _EV NT_ T_ W
15. Remote Control Peripheral
T H X_ R E IN ST T H X_ R E IN RA
0
0
23
RM _C 1_T TH _EV NT_ T_ 23 RM _C 1_T TH _EV NT_ T_ W
T H X_ R E IN ST T H X_ R E IN RA
0
0
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
RMT_CHn_TX_THR_EVENT_INT_ST The
0
0
17
17
0
0
16
16
0
0
15
15
RM _C 5_E EN _IN RM C _E N IN
H R
T D T_ T H R D T_
405
0
0
14
14
T X T T_ T H X T T_ W
0
0
masked
13
13
0
0
12
12
0
0
11
11
0
0
10
10
9
9
0
0
interrupt
RM _C 3_E EN _IN RM _C 3_E EN _IN
T H R D T_ T H R D T_
8
8
0
0
7
7
0
0
Register 15.3: RMT_INT_RAW_REG (0x00A0)
6
6
0
0
T D T_ T D T_
status
5
5
0
0
4
4
0
0
3
3
0
0
bit
RM _C 1_E EN _IN RM _C 1_E EN _IN
T H R D T_ T H R D T_
2
2
0
0
1
1
0
0
for
T H X_ D T T H X_ D AW W
0
0
RMT_CHn_ERR_INT_ST The masked interrupt status bit for the RMT_CHn_ERR_INT interrupt. (RO)
RMT_CHn_TX_END_INT_ST The masked interrupt status bit for the RMT_CHn_TX_END_INT inter-
RMT_CHn_RX_END_INT_ST The masked interrupt status bit for the RMT_CHn_RX_END_INT inter-
the
RMT_CHn_TX_END_INT_RAW The raw interrupt status bit for the RMT_CHn_TX_END_INT interrupt.
RMT_CHn_RX_END_INT_RAW The raw interrupt status bit for the RMT_CHn_RX_END_INT inter-
the
0_ X_E T_ _S 0_ X_E T_ _R W
0 Reset
0 Reset
TX N ST T TX N RA AW
_E D_ _E D_ W
ND INT ND INT
31
31
RM RM
T T
0
0
30
30
RM _C RM _C
T H T H
0
0
29
29
RM _C 7_T RM _C 7_T
T H X_ T H X_
(R/W)
(R/W)
0
0
28
28
RM _C 6_T TH RM _C 6_T TH
Espressif Systems
T H X_ R T H X_ R
0
0
27
27
RM _C 5_T TH _EV RM _C 5_T TH _EV
T H X_ R E T H X_ R E
0
0
26
26
terrupt. (WO)
RM _C 4_T TH _EV NT_ RM _C 4_T TH _EV NT_
T H X_ R E IN T H X_ R E IN
0
0
25
25
RM _C 3_T TH _EV NT_ T_ RM _C 3_T TH _EV NT_ T_
T H X_ R E IN CL T H X_ R E IN EN
0
0
24
24
RM _C 2_T TH _EV NT_ T_ R RM _C 2_T TH _EV NT_ T_ A
15. Remote Control Peripheral
T H X_ R E IN CL T H X_ R E IN EN
0
0
23
RM _C 1_T TH _EV NT_ T_ R 23 RM _C 1_T TH _EV NT_ T_ A
T H X_ R E IN CL T H X_ R E IN EN
0
0
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
RM _C 6_E EN _IN _ CL
RM _C 6_E EN _IN _E
T H R D T_ R T H R D T_ NA
0
0
17
17
NT T_ A
T_ H6 X_E T_ T_C R T
0
0
16
16
RM C _T N C L RM _C 6_T _EN _E EN
T H X_ D LR R T_ H5 X_E D_ NA A
0
0
15
15
RM _C 5_E EN _IN RM C _E N IN
T H R D T_ T H R D T_
406
RMT_CHn_TX_THR_EVENT_INT interrupt. (R/W)
0
0
14
14
0
0
13
13
0
0
12
12
T H R D T_ T H R D T_
0
0
11
11
0
0
10
10
9
9
0
0
8
8
0
0
7
7
0
0
Register 15.5: RMT_INT_ENA_REG (0x00A8)
6
6
0
0
5
5
0
0
4
4
0
0
3
3
0
0
0
0
1
1
0
0
0
0
0_ X_E T_ _C R 0_ X_E T_ _E A
0 Reset
0 Reset
TX N CL LR TX N EN NA
_E D_ R _E D_ A
ND INT ND INT
Hn
CH
_C
H_
W
IG
LO
H
R_
R_
E
E
RI
RI
AR
R
CA
C
T_
T_
RM
RM
31 16 15 0
RMT_CARRIER_HIGH_CHn This field is used to configure the carrier wave’s high-level clock period
for channel n. The clock source can be either REF_TICK or APB_CLK. (R/W)
RMT_CARRIER_LOW_CHn This field is used to configure the carrier wave’s low-level clock period
for channel n. The clock source can be either REF_TICK or APB_CLK. (R/W)
Hn
_C
IM
_L
d)
TX
e
rv
T_
se
RM
(re
31 9 8 0
RMT_TX_LIM_CHn When channel n sends more entries than specified here, it produces a
TX_THR_EVENT interrupt. (R/W)
S_ N
EN
ES P_E
CC RA
_A _W
EM X
M _T
T_ EM
)
ed
RM _M
rv
se
T
RM
(re
31 2 1 0
0x00000000 0 0 Reset
RMT_MEM_TX_WRAP_EN This bit enables wraparound mode: when the transmitter of a channel
has reached the end of its memory block, it will resume sending at the start of its memory region.
(R/W)
16. MCPWM
16.1 Introduction
The Motor Control Pulse Width Modulator (MCPWM) peripheral is intended for motor and power control. It
provides six PWM outputs that can be set up to operate in several topologies. One common topology uses a pair
of PWM outputs driving an H-bridge to control motor rotation speed and rotation direction.
The timing and control resources inside are allocated into two major types of submodules: PWM timers and
PWM operators. Each PWM timer provides timing references that can either run freely or be synced to other
timers or external sources. Each PWM operator has all necessary control resources to generate waveform pairs
for one PWM channel. The MCPWM peripheral also contains a dedicated capture submodule that is used in
systems where accurate timing of external events is important.
ESP32 contains two MCPWM peripherals: MCPWM0 and MCPWM1. Their control registers are located in 4-KB
memory blocks starting at memory locations 0x3FF5E000 and 0x3FF6C000 respectively.
16.2 Features
Each MCPWM peripheral has one clock divider (prescaler), three PWM timers, three PWM operators, and a
capture module. Figure 92 shows the submodules inside and the signals on the interface. PWM timers are used
for generating timing references. The PWM operators generate desired waveform based on the timing
references. Any PWM operator can be configured to use the timing references of any PWM timers. Different
PWM operators can use the same PWM timer’s timing references to produce related PWM signals. PWM
operators can also use different PWM timers’ values to produce the PWM signals that work alone. Different PWM
timers can also be synced together.
– The 16-bit counter in the PWM timer can work in count-up mode, count-down mode or
count-up-down mode.
– A hardware sync can trigger a reload on the PWM timer with a phase register. It will also trigger the
prescaler’ restart, so that the timer’s clock can also be synced. The source of the sync can come from
any GPIO or any other PWM timer’s sync_out.
– Every PWM operator has two PWM outputs: PWMxA and PWMxB. They can work independently, in
symmetric and asymmetric configuration.
– Modulating of PWM output by high-frequency carrier signals, useful when gate drives are insulated
with a transformer.
– Period, time stamps and important control registers have shadow registers with flexible updating
methods.
– Programmable fault handling allocated on fault condition in both cycle-by-cycle mode and one-shot
mode.
– A fault condition can force the PWM output to either high or low logic levels.
• Capture Module
– Speed measurement of rotating machinery (for example, toothed sprockets sensed with Hall sensors)
– Decoding current or voltage amplitude derived from duty-cycle-encoded signals from current/voltage
sensors
– Three individual capture channels, each of which has a time-stamp register (32 bits)
– The capture timer can sync with a PWM timer or external signals.
16.3 Submodules
16.3.1 Overview
This section lists the configuration parameters of key submodules. For information on adjusting a specific
parameter, e.g. synchronization source of PWM timer, please refer to Section 16.3.2 for details.
Configuration parameter:
Configuration parameters:
• Configure the the reloading phase (including the value and the phase) used during software and hardware
synchronization.
• Synchronize the PWM timers with each other. Either hardware or software synchronization may be used.
• Configure the source of the PWM timer’s the synchronization input to one of the seven sources below:
– Three synchronization signals from the GPIO matrix: SYNC0, SYNC1, SYNC2.
• Configure the source of the PWM timer’s synchronization output to one of the four sources below:
The configuration parameters of the operator submodule are shown in Table 69.
• Set up the PWM duty cycle for PWMxA and/or PWMxB out-
put.
• Set up at which time the timing events occur.
• Define what action should be taken on timing events:
– Switch high or low PWMxA and/or PWMxB outputs
PWM Generator – Toggle PWMxA and/or PWMxB outputs
– Take no action on outputs
• Use direct s/w control to force the state of PWM outputs
• Add a dead time to raising and / or failing edge on PWM out-
puts.
• Configure update method for this submodule.
• Configure if and how the PWM module should react the fault
event signals.
• Specify the action taken when a fault event occurs:
– Force PWMxA and/or PWMxB high.
– Force PWMxA and/or PWMxB low.
– Configure PWMxA and/or PWMxB to ignore any fault
event.
Fault Handler • Configure how often the PWM should react to fault events:
– One-shot
– Cycle-by-cycle
• Generate interrupts.
• Bypass the fault handler submodule entirely.
• Set up an option for cycle-by-cycle actions clearing.
• If desired, independently-configured actions can be taken
when time-base counter is counting down or up.
Configuration parameters:
• Enable fault event generation and configure the polarity of fault event generation for every fault signal
Configuration parameters:
Users can configure the following functions of the PWM timer submodule:
• Control how often events occur by specifying the PWM timer frequency or period.
• Configure a particular PWM timer to synchronize with other PWM timers or modules.
• Set one of the following timer counting modes: count-up, count-down, count-up-down.
• Change the rate of the PWM timer clock (PT_clk) with a prescaler. Each timer has its own prescaler
configured with PWM_TIMERx_PRESCALE of register PWM_TIMER0_CFG0_REG. The PWM timer
increments or decrements at a slower pace, depending on the setting of this register.
The PWM timer has three working modes, selected by the PWMx timer mode register:
• Count-Up Mode:
In this mode, the PWM timer increments from zero until reaching the value configured in the period register.
Once done, the PWM timer returns to zero and starts increasing again. PWM period is equal to the period
value configured in register.
• Count-Down Mode:
The PWM timer decrements to zero, starting from the value configured in the period register. After reaching
zero, it is set back to the period value. Then it starts to decrement again. In this case, the PWM period is
also equal to the value configured in the period register.
• Count-Up-Down Mode:
This is a combination of the two modes mentioned above. The PWM timer starts increasing from zero until
the period value is reached. Then, the timer decreases back to zero. This pattern is then repeated. The
PWM period is the result of the value in the period register multiplied by 2.
Figures 98 to 101 show PWM timer waveforms in different modes, including timer behavior during
synchronization events.
When the PWM timer is running, it generates the following timing events periodically and automatically:
• UTEP
The timing event generated when the PWM timer’s value equals to the value of the period register
(PWM_TIMERx_PERIOD) and when the PWM timer is increasing.
• UTEZ
The timing event generated when the PWM timer’s value equals to zero and when the PWM timer is
increasing.
• DTEP
The timing event generated when the PWM timer’s value equals to the value of the period register
(PWM_TIMERx_PERIOD) and when the PWM timer is decreasing.
• DTEZ
The timing event generated when the PWM timer’s value equals to zero and when the PWM timer is
decreasing.
Figures 102 to 104 show the timing waveforms of U/DTEP and U/DTEZ.
The PWM timer’s period register and the PWM timer’s clock prescaler register have shadow registers. The
purpose of a shadow register is to save a copy of the value to be written into the active register at a specific
moment synchronized with the hardware. Both register types are defined as follows:
• Active Register
This register is directly responsible for controlling all actions performed by hardware.
• Shadow Register
It acts as a temporary buffer for a value to be written on the active register. Before this happens, the content
of the shadow register has no direct effect on the controlled hardware. At a specific, user-configured point
in time, the value saved in the shadow register is copied to the active register. This helps to prevent spurious
operation of the hardware, which may happen when a register is asynchronously modified by software.
Both the shadow register and the active register have the same memory address. The software always
writes into, or reads from the shadow register. The moment of updating the active register is determined by
its specific update method register. The update can start when the PWM timer is equal to zero, when the
PWM timer is equal to period,at a synchronization moment, or immediately. Software can trigger a globally
forced update which will prompt all registers in the module to be updated according to shadow registers.
The PWM modules adopt a flexible synchronization method. Each PWM timer has a synchronization input and a
synchronization output. The synchronization input can be selected from three synchronization outputs and three
synchronization signals from the GPIO matrix. The synchronization output can be generated from the
synchronization input signal, or when the PWM timer’s value is equal to period or zero. Thus, the PWM timers
can be chained together with their phase locked. During synchronization, the PWM timer clock prescaler will
reset its counter in order to synchronize the PWM timer clock.
• Generates a PWM signal pair, based on timing references obtained from the corresponding PWM timer.
• Each signal out of the PWM signal pair includes a specific pattern of dead time.
In this submodule, important timing events are generated or imported. The events are then converted into
specific actions to generate the desired waveforms at the PWMxA and PWMxB outputs.
• Generation of timing events based on time stamps configured using the A and B registers. Events happen
when the following conditions are satisfied:
– UTEA: the PWM timer is counting up and its value is equal to register A.
– UTEB: the PWM timer is counting up and its value is equal to register B.
– DTEA: the PWM timer is counting down and its value is equal to register A.
– DTEB: the PWM timer is counting down and its value is equal to register B.
• Qualification and generation of set, clear and toggle actions, based on the timing events.
• Controlling of the PWM duty cycle, depending on configuration of the PWM generator submodule.
• Handling of new time stamp values, using shadow, registers to prevent glitches in the PWM cycle.
The time stamp registers A and B, as well as action configuration registers PWM_GENx_A_REG and
PWM_GENx_B_REG are shadowed. Shadowing provides a way of updating registers in sync with the hardware.
For a description of the shadow registers, please see 16.3.2.3.
Timing Events
For convenience, all timing signals and events are summarized in Table 70.
The purpose of a software-force event is to impose non-continuous or continuous changes on the PWMxA and
PWMxB outputs. The change is done asynchronously. Software-force control is handled by the
PWM_PWM_GENx_FORCE_REG registers.
The selection and configuration of T0/T1 in the PWM generator submodule is independent of the configuration of
fault events in the fault handler submodule. A particular trip event may or may not be configured to cause trip
action in the fault handler submodule, but the same event can be used by the PWM generator to trigger T0/T1
for controlling PWM waveforms.
It is important to know that when the PWM timer is in count-up-down mode, it will always decrement after a TEP
event, and will always increment after a TEZ event. So when the PWM timer is in count-up-down mode, DTEP
and UTEZ events will occur, while the events UTEP and DTEZ will never occur.
The PWM generator can handle multiple events at the same time. Events are prioritized by the hardware and
relevant details are provided in Table 71 and Table 72. Priority levels range from 1 (the highest) to 7 (the lowest).
Please note that the priority of TEP and TEZ events depends on the PWM timer’s direction.
If the value of A or B is set to be greater than the period, then U/DTEA and U/DTEB will never occur.
Notes:
1. UTEP and UTEZ do not happen simultaneously. When the PWM timer is in count-up mode, UTEP will
always happen one cycle earlier than UTEZ, as demonstrated in Figure 102, so their action on PWM signals
will not interrupt each other. When the PWM timer is in count-up-down mode, UTEP will not occur.
2. DTEP and DTEZ do not happen simultaneously. When the PWM timer is in count-down mode, DTEZ will
always happen one cycle earlier than DTEP, as demonstrated in Figure 103, so their action on PWM signals
will not interrupt each other. When the PWM timer is in count-up-down mode, DTEZ will not occur.
The PWM generator submodule controls the behavior of outputs PWMxA and PWMxB when a particular timing
event occurs. The timing events are further qualified by the PWM timer’s counting direction (up or down).
Knowing the counting direction, the submodule may then perform an independent action at each stage of the
PWM timer counting up or down.
• Set High:
Set the output of PWMxA or PWMxB to a high level.
• Clear Low:
Clear the output of PWMxA or PWMxB by setting it to a low level.
• Toggle:
Change the current output level of PWMxA or PWMxB to the opposite value. If it is currently pulled high,
pull it low, or vice versa.
• Do Nothing:
Keep both outputs PWMxA and PWMxB unchanged. In this state, interrupts can still be triggered.
The configuration of actions on outputs is done by using registers PWN_GENx_A_REG and PWN_GENx_B_REG.
So, the action to be taken on each output is set independently. Also there is great flexibility in selecting actions to
be taken on a given output based on events. More specifically, any event listed in Table 70 can operate on either
output PWMxA or PWMxB. To check out registers for particular generator 0, 1 or 2, please refer to register
description in Section 16.4.
Figure 106 presents the symmetric PWM waveform generated when the PWM timer is counting up and down.
DC 0%–100% modulation can be calculated via the formula below:
If A matches the PWM timer value and the PWM timer is incrementing, then the PWM output is pulled up. If A
matches the PWM timer value while the PWM timer is decrementing, then the PWM output is pulled low.
The PWM waveforms in Figures 107 to 110 show some common PWM operator configurations. The following
conventions are used in the figures:
Figure 107: Count-Up, Single Edge Asymmetric Waveform, with Independent Modulation on PWMxA and
PWMxB — Active High
The duty modulation for PWMxA is set by B, active high and proportional to B.
The duty modulation for PWMxB is set by A, active high and proportional to A.
Figure 108: Count-Up, Pulse Placement Asymmetric Waveform with Independent Modulation on PWMxA
Pulses may be generated anywhere within the PWM cycle (zero – period).
PWMxA’s high time duty is proportional to (B – A).
Figure 109: Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA
and PWMxB — Active High
The duty modulation for PWMxA is set by A, active high and proportional to A.
The duty modulation for PWMxB is set by B, active high and proportional to B.
Outputs PWMxA and PWMxB can drive independent switches.
Figure 110: Count-Up-Down, Dual Edge Symmetric Waveform, with Independent Modulation on PWMxA
and PWMxB — Complementary
Software-Force Events
There are two types of software-force events inside the PWM generator:
Figure 111 shows a waveform of NCI software-force events. NCI events are used to force PWMxA output low.
Forcing on PWMxB is disabled in this case.
Figure 112 shows a waveform of CNTU software-force events. UTEZ events are selected as triggers for CNTU
software-force events. CNTU is used to force the PWMxB output low. Forcing on PWMxA is disabled.
Several options to generate signals on PWMxA and PWMxB outputs, with a specific placement of signal edges,
have been discussed in section 16.3.3.1. The required dead time is obtained by altering the edge placement
between signals and by setting the signal’s duty cycle. Another option is to control the dead time using a
specialized submodule – the Dead Time Generator.
The key functions of the dead time generator submodule are as follows:
• Generating signal pairs (PWMxA and PWMxB) with a dead time from a single PWMxA input
• This submodule may also be bypassed, if the dead time is configured directly in the generator submodule.
Delay registers RED and FED are shadowed with registers PWM_DTx_RED_CFG_REG and
PWM_DTx_FED_CFG_REG. For the description of shadow registers, please see section 16.3.2.3.
Options for setting up the dead-time submodule are shown in Figure 113.
Figure 113: Options for Setting up the Dead Time Generator Submodule
S0-8 in the figure above are switches controlled by registers PWM_DTx_CFG_REG shown in Table 73.
Switch Register
S0 PWM_DTx_B_OUTBYPASS
S1 PWM_DTx_A_OUTBYPASS
S2 PWM_DTx_RED_OUTINVERT
S3 PWM_DTx_FED_OUTINVERT
S4 PWM_DTx_RED_INSEL
S5 PWM_DTx_FED_INSEL
S6 PWM_DTx_A_OUTSWAP
S7 PWM_DTx_B_OUTSWAP
S8 PWM_DTx_DEB_MODE
All switch combinations are supported, but not all of them represent the typical modes of use. Table 74
documents some typical dead time configurations. In these configurations the position of S4 and S5 sets
PWMxA as the common source of both falling-edge and rising-edge delay. The modes presented in table 74 may
be categorized as follows:
• Mode 1: Bypass delays on both falling (FED) as well as raising edge (RED)
In this mode the dead time submodule is disabled. Signals PWMxA and PWMxB pass through without any
modifications.
• Modes 6 and 7: Bypass delay on falling edge (FED) or rising edge (RED)
In these modes, either RED (Rising Edge Delay) or FED (Falling Edge Delay) is bypassed. As a result, the
corresponding delay is not applied.
Rising edge (RED) and falling edge (FED) delays may be set up independently. The delay value is programmed
using the 16-bit registers PWM_DTx_RED and PWM_DTx_FED. The register value represents the number of
clock (DT_clk) periods by which a signal edge is delayed. DT_CLK can be selected from PWM_clk or PT_clk
through register PWM_DTx_CLK_SEL.
To calculate the delay on falling edge (FED) and rising edge (RED), use the following formulas:
The coupling of PWM output to a motor driver may need isolation with a transformer. Transformers deliver only
AC signals, while the duty cycle of a PWM signal may range anywhere from 0% to 100%. The PWM carrier
submodule passes such a PWM signal through a transformer by using a high frequency carrier to modulate the
signal.
Function Overview
• Carrier frequency
Operational Highlights
The PWM carrier clock (PC_clk) is derived from PWM_clk. The frequency and duty cycle are configured by the
PWM_CARRIERx_PRESCALE and PWM_CARRIERx_DUTY bits in the PWM_CARRIERx_CFG_REG register. The
purpose of one-shot pulses is to provide high-energy impulse to reliably turn on the power switch. Subsequent
pulses sustain the power-on status. The width of a one-shot pulse is configurable with the
PWM_CARRIERx_OSHTWTH bits. Enabling/disabling of the carrier submodule is done with the
PWM_CARRIERx_EN bit.
Waveform Examples
Figure 118 shows an example of waveforms, where a carrier is superimposed on original PWM pulses. This
figure do not show the first one-shot pulse and the duty-cycle control. Related details are covered in the following
two sections.
One-Shot Pulse
The width of the first pulse is configurable. It may assume one of 16 possible values and is described by the
formula below:
Where:
• (P W M _CARRIERx_OSHT W T H + 1) is the width of the first pulse (whose value ranges from 1 to 16).
The first one-shot pulse and subsequent sustaining pulses are shown in Figure 119.
After issuing the first one-shot pulse, the remaining PWM signal is modulated according to the carrier frequency.
Users can configure the duty cycle of this signal. Tuning of duty may be required, so that the signal passes
through the isolating transformer and can still operate (turn on/off) the motor drive, changing rotation speed and
direction.
The duty cycle may be set to one of seven values, using PWM_CARRIERx_DUTY, or bits [7:5] of register
PWM_CARRIERx_CFG_REG.
Duty = P W M _CARRIERx_DU T Y ÷ 8
Figure 119: Example of the First Pulse and the Subsequent Sustaining Pulses of the PWM Carrier Sub-
module
All seven settings of the duty cycle are shown in Figure 120.
Figure 120: Possible Duty Cycle Settings for Sustaining Pulses in the PWM Carrier Submodule
Each MCPWM peripheral is connected to three fault signals (FAULT0, FAULT1 and FAULT2) which are sourced
from the GPIO matrix. These signals are intended to indicate external fault conditions, and may be preprocessed
by the fault detection submodule to generate fault events. Fault events can then execute the user code to control
MCPWM outputs in response to specific faults.
• Forcing outputs PWMxA and PWMxB, upon detected fault, to one of the following states:
– High
– Low
– Toggle
– No action taken
This section provides the operational tips and set-up options for the fault handler submodule.
Fault signals coming from pads are sampled and synced in the GPIO matrix. In order to guarantee the successful
sampling of fault pulses, each pulse duration must be at least two APB clock cycles. The fault detection
submodule will then sample fault signals by using PWM_clk. So, the duration of fault pulses coming from GPIO
matrix must be at least one PWM_clk cycle. Differently put, regardless of the period relation between APB clock
and PWM_clk, the width of fault signal pulses on pads must be at least equal to the sum of two APB clock cycles
and one PWM_clk cycle.
Each level of fault signals, FAULT0 to FAULT2, can be used by the fault handler submodule to generate fault
events (fault_event0 to fault_event2). Every fault event can be configured individually to provide CBC action, OST
action, or none.
16.3.4.1 Introduction
The capture submodule contains three complete capture channels. Channel inputs CAP0, CAP1 and CAP2 are
sourced from the GPIO matrix. Thanks to the flexibility of the GPIO matrix, CAP0, CAP1 and CAP2 can be
configured from any PAD input. Multiple capture channels can be sourced from the same PAD input, while
prescaling for each channel can be set differently. Also, capture channels are sourced from different PADs. This
provides several options for handling capture signals by hardware in the background, instead of having them
processed directly by the CPU. A capture submodule has the following independent key resources:
• One 32-bit timer (counter) which can be synchronized with the PWM timer, another submodule or software.
• Three capture channels, each equipped with a 32-bit time-stamp and a capture prescaler.
• Independent edge polarity (rising/falling edge) selection for any capture channel.
The capture timer is a 32-bit counter incrementing continuously, once enabled. On the input it has an APB clock
running typically at 80 MHz. At a sync event the counter is loaded with phase stored in register
PWM_CAP_TIMER_PHASE_REG. Sync events can come from PWM timers sync-out, PWM module sync-in or
software. The capture timer provides timing references for all three capture channels.
The capture signal coming to a capture channel will be inverted first, if needed, and then prescaled. Finally,
specified edges of preprocessed capture signal will trigger capture events. When a capture event occurs, the
capture timer’s value is stored in time-stamp register PWM_CAP_CHx_REG. Different interrupts can be
generated for different capture channels at capture events. The edge that triggers a capture event is recorded in
register PWM_CAPx_EDGE. The capture event can be also forced by software.
16.5 Registers
_C
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31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x000 Reset
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PW
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31 5 4 3 2 0
PWM_TIMER0_MOD PWM timer0 working mode. 0: freeze, 1: increase mode, 2: decrease mode,
3: up-down mode. (R/W)
PWM_TIMER0_START PWM timer0 start and stop control. 0: if PWM timer0 starts, then stops at
TEZ; 1: if timer0 starts, then stops at TEP; 2: PWM timer0 starts and runs on; 3: timer0 starts and
stops at the next TEZ; 4: timer0 starts and stops at the next TEP. TEP here and below means the
event that happens when the timer equals to period. (R/W)
0_ NC EL
NC SW
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31 21 20 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_TIMER1_SYNCI_EN When set, timer reloading with phase on sync input event is enabled.
(R/W)
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31 17 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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31 26 25 24 23 8 7 0
PWM_TIMER1_PERIOD_UPMETHOD Updating method for the active register of PWM timer1 pe-
riod. 0: immediately, 1: update at TEZ, 2: update at sync, 3: update at TEZ or sync. (R/W)
T
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1_
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31 5 4 3 2 0
PWM_TIMER1_MOD PWM timer1 working mode. 0: freeze, 1: increase mode, 2: decrease mode,
3: up-down mode. (R/W)
PWM_TIMER1_START PWM timer1 start and stop control. 0: if PWM timer1 starts, then stops at
TEZ; 1: if PWM timer1 starts, then stops at TEP; 2: PWM timer1 starts and runs on; 3: PWM
timer1 starts and stops at the next TEZ; 4: PWM timer1 starts and stops at the next TEP. (R/W)
1_ NC EL
NC SW
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31 21 20 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_TIMER1_SYNCI_EN When set, timer reloading with phase at a sync input event is enabled.
(R/W)
UE
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31 17 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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31 5 4 3 2 0
PWM_TIMER2_MOD PWM timer2 working mode. 0: freeze, 1: increase mode, 2: decrease mode,
3: up-down mode. (R/W)
PWM_TIMER2_START PWM timer2 start and stop control. 0: if PWM timer2 starts, then stops at
TEZ; 1: if PWM timer2 starts, then stops at TEP; 2: PWM timer2 starts and runs on; 3: PWM
timer2 starts and stops at the next TEZ; 4: PWM timer2 starts and stops at the next TEP. (R/W)
2_ NC EL
NC SW
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31 21 20 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_TIMER2_SYNCI_EN When set, timer reloading with phase on sync input event is enabled.
(R/W)
UE
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31 17 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
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PW
PW
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31 12 11 10 9 8 6 5 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_TIMER2_SYNCISEL Select sync input for PWM timer2. 1: PWM timer0 sync_out, 2: PWM
timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO
matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected. (R/W)
PWM_TIMER1_SYNCISEL Select sync input for PWM timer1. 1: PWM timer0 sync_out, 2: PWM
timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO
matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected. (R/W)
PWM_TIMER0_SYNCISEL Select sync input for PWM timer0. 1: PWM timer0 sync_out, 2: PWM
timer1 sync_out, 3: PWM timer2 sync_out, 4: SYNC0 from GPIO matrix, 5: SYNC1 from GPIO
matrix, 6: SYNC2 from GPIO matrix, other values: no sync input selected. (R/W)
L
SE
SE
SE
ER
ER
ER
IM
IM
IM
_T
_T
_T
R2
R1
R0
TO
TO
TO
RA
RA
RA
PE
PE
PE
d)
_O
_O
_O
e
rv
M
se
PW
PW
PW
(re
31 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_OPERATOR2_TIMERSEL Select the PWM timer for PWM operator2’s timing reference. 0:
timer0, 1: timer1, 2: timer2. (R/W)
PWM_OPERATOR1_TIMERSEL Select the PWM timer for PWM operator1’s timing reference. 0:
timer0, 1: timer1, 2: timer2. (R/W)
PWM_OPERATOR0_TIMERSEL Select the PWM timer for PWM operator0’s timing reference. 0:
timer0, 1: timer1, 2: timer2. (R/W)
_F LL
L
D
UL
HO
HO
DW FU
SH W_
ET
ET
M
M
A_ D
0_ _SH
UP
UP
B_
A_
EN _B
0_
0_
_G 0
M EN
EN
EN
)
ed
PW _G
_G
_G
rv
M
se
PW
PW
PW
(re
31 10 9 8 7 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN0_B_SHDW_FULL Set and reset by hardware. If set, PWM generator 0 time stamp B’s
shadow register.ister is filled and to be transferred to time stamp B’s active register. If cleared, time
stamp B’s active register has been updated with Shadow register latest value. (RO)
PWM_GEN0_A_SHDW_FULL Set and reset by hardware. If set, PWM generator 0 time stamp A’s
shadow register.ister is filled and to be transferred to time stamp A’s active register. If cleared, time
stamp A’s active register has been updated with Shadow register latest value. (RO)
PWM_GEN0_B_UPMETHOD Updating method for PWM generator 0 time stamp B’s active register.
When all bits are set to 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP;
when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W)
PWM_GEN0_A_UPMETHOD Updating method for PWM generator 0 time stamp A’s active register.
When all bits are set to 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP;
when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W)
_G
e
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
_G
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
D
HO
ET
PM
EL
EL
_U
_S
_S
G
CF
T1
T0
0_
0_
0_
EN
EN
EN
)
ed
_G
_G
_G
rv
M
se
PW
PW
PW
(re
31 10 9 7 6 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN0_T1_SEL Source selection for PWM generator 0 event_t1, taking effect immediately. 0:
fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W)
PWM_GEN0_T0_SEL Source selection for PWM generator 0 event_t0, taking effect immediately, 0:
fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W)
PWM_GEN0_CFG_UPMETHOD Updating method for PWM generator 0’s active register of config-
uration. When all bits are set to 0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1:
TEP; when bit2 is set to 1: sync; when bit3 is set to 1: disable the update. (R/W)
D
HO
DE
DE
ET
E
NT CE DE
O
RC OD
M
M
_M
O
UP
E_
IF E_M
0_ CIF E_M
CE
RC
E_
E
R
C
RC
O
O
B_ FOR
R
UF
UF
O
FO
FO
T
I
TU
N0 NC
N0 NC
N0 NC
CN
_C
N
CN
_
A_
_G _B
B
_G _A
_G _A
_
0_
0_
N0
EN
EN
EN
)
PW GE
PW E
PW GE
PW E
ed
_G
_G
rv
_
M
M
se
PW
PW
PW
(re
31 16 15 14 13 12 11 10 9 8 7 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x20 Reset
EB
EB
A
EP
EA
EP
Z
EZ
TE
TE
1
T0
DT
DT
DT
DT
UT
UT
UT
UT
UT
_D
_D
_U
A_
A_
A_
A_
A_
A_
A_
A_
A_
A
A
0_
0_
0_
0_
0_
0_
0_
0_
0_
0_
0_
0_
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
)
ed
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
rv
M
se
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
(re
31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN0_A_DT0 Action on PWM0A triggered by event_t0 when the timer decreases. (R/W)
PWM_GEN0_A_DTEB Action on PWM0A triggered by event TEB when the timer decreases. (R/W)
PWM_GEN0_A_DTEA Action on PWM0A triggered by event TEA when the timer decreases. (R/W)
PWM_GEN0_A_DTEP Action on PWM0A triggered by event TEP when the timer decreases. (R/W)
PWM_GEN0_A_DTEZ Action on PWM0A triggered by event TEZ when the timer decreases. (R/W)
PWM_GEN0_A_UT1 Action on PWM0A triggered by event_t1 when the timer increases. (R/W)
PWM_GEN0_A_UT0 Action on PWM0A triggered by event_t0 when the timer increases. (R/W)
PWM_GEN0_A_UTEB Action on PWM0A triggered by event TEB when the timer increases. (R/W)
PWM_GEN0_A_UTEA Action on PWM0A triggered by event TEA when the timer increases. (R/W)
PWM_GEN0_A_UTEP Action on PWM0A triggered by event TEP when the timer increases. (R/W)
PWM_GEN0_A_UTEZ Action on PWM0A triggered by event TEZ when the timer increases. (R/W)
EB
EB
A
EP
EA
EP
Z
EZ
TE
TE
1
T0
DT
DT
DT
DT
UT
UT
UT
UT
UT
_D
_D
_U
B_
B_
B_
B_
B_
B_
B_
B_
B_
B
B
0_
0_
0_
0_
0_
0_
0_
0_
0_
0_
0_
0_
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
)
ed
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
rv
M
se
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
(re
31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN0_B_DT0 Action on PWM0B triggered by event_t0 when the timer decreases. (R/W)
PWM_GEN0_B_DTEB Action on PWM0B triggered by event TEB when the timer decreases. (R/W)
PWM_GEN0_B_DTEA Action on PWM0B triggered by event TEA when the timer decreases. (R/W)
PWM_GEN0_B_DTEP Action on PWM0B triggered by event TEP when the timer decreases. (R/W)
PWM_GEN0_B_DTEZ Action on PWM0B triggered by event TEZ when the timer decreases. (R/W)
PWM_GEN0_B_UT1 Action on PWM0B triggered by event_t1 when the timer increases. (R/W)
PWM_GEN0_B_UT0 Action on PWM0B triggered by event_t0 when the timer increases. (R/W)
PWM_GEN0_B_UTEB Action on PWM0B triggered by event TEB when the timer increases. (R/W)
PWM_GEN0_B_UTEA Action on PWM0B triggered by event TEA when the timer increases. (R/W)
PWM_GEN0_B_UTEP Action on PWM0B triggered by event TEP when the timer increases. (R/W)
PWM_GEN0_B_UTEZ Action on PWM0B triggered by event TEZ when the timer increases. (R/W)
D
T
D
T
PW _D 0_B D_ EL ER
HO
PW _D 0_R D_I TIN ER
HO
PW _D 0_R D_O YP SS
PW _D 0_F D_ TIN S
M T E U AS
M T E S V
EB TS P
O P
M T E U V
ET
M T E TB A
ET
_D U WA
DE
_M WA
_D _A U EL
PW _D 0_F OU YP
PM
PM
PW _D 0_A OU L
M T0 _O NS
M T _ TB
T0 O S
M T _ E
N
O
_U
PW _D 0_B K_S
_U
I
ED
ED
M T L
_
PW _D _C
_R
_F
M T0
T0
T0
d)
PW _D
_D
_D
ve
er
M
s
PW
PW
PW
31 (re 18 17 16 15 14 13 12 11 10 9 8 7 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Reset
PWM_DT0_RED_UPMETHOD Updating method for RED (rising edge delay) active register. 0: im-
mediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when
bit3 is set to 1: disable the update. (R/W)
PWM_DT0_FED_UPMETHOD Updating method for FED (falling edge delay) active register. 0: im-
mediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when
bit3 is set to 1: disable the update. (R/W)
_D
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ED
_R
T0
)
ed
_D
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
T
ER
LE
_I T
TH
UT R
NV
CA
O VE
TY
ES
0_ _IN
SH
DU
PR
EN
ER IN
O
RI 0_
0_
0_
0_
0_
AR IER
ER
ER
ER
ER
RI
RI
RI
RI
_C R
M AR
AR
AR
AR
AR
d)
PW _C
_C
_C
_C
_C
e
rv
M
se
PW
PW
PW
PW
PW
(re
31 14 13 12 11 8 7 5 4 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_CARRIER0_IN_INVERT When set, invert the input of PWM0A and PWM0B for this submodule.
(R/W)
PWM_CARRIER0_OUT_INVERT When set, invert the output of PWM0A and PWM0B for this sub-
module. (R/W)
PWM_CARRIER0_OSHWTH Width of the first pulse�in number of periods of the carrier. (R/W)
PWM_CARRIER0_PRESCALE PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk = pe-
riod of PWM_clk * (PWM_CARRIER0_PRESCALE + 1). (R/W)
PWM_CARRIER0_EN When set, carrier0 function is enabled. When cleared, carrier0 is bypassed.
(R/W)
_U
_U
M H0 0_O D
_U
_D
_U
_D
BC
M H0 0_C ST
C_
PW _F 0_F C_
M H0 1_C C
H0 2_ C
W C
M H 1 T
M H 2 T
M H W T
BC
BC
ST
ST
ST
ST
PW _F _F S
PW _F 0_F _OS
PW _F 0_S _OS
PW _F _F B
_F _F B
_S CB
PW _F 0_F _O
_C
CB
B
_O
_C
_O
_C
PW _F A_C
B_
_
_B
_B
_B
_A
_A
_A
0_
_
H0
H0
H0
H0
H0
H0
PW FH0
)
M H
ed
_F
_F
_F
_F
_F
_F
_F
rv
_
M
M
se
PW
PW
PW
PW
PW
PW
PW
PW
(re
31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_FH0_B_OST_U One-shot mode action on PWM0B when a fault event occurs and the timer is
increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH0_B_OST_D One-shot mode action on PWM0B when a fault event occurs and the timer is
decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH0_B_CBC_U Cycle-by-cycle mode action on PWM0B when a fault event occurs and the
timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH0_B_CBC_D Cycle-by-cycle mode action on PWM0B when a fault event occurs and the
timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH0_A_OST_U One-shot mode action on PWM0A when a fault event occurs and the timer is
increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH0_A_OST_D One-shot mode action on PWM0A when a fault event occurs and the timer is
decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH0_A_CBC_U Cycle-by-cycle mode action on PWM0A when a fault event occurs and the
timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH0_A_CBC_D Cycle-by-cycle mode action on PWM0A when a fault event occurs and the
timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH0_F0_OST event_f0 will trigger one-shot mode action. 0: disable, 1: enable. (R/W)
PWM_FH0_F1_OST event_f1 will trigger one-shot mode action. 0: disable, 1: enable. (R/W)
PWM_FH0_F2_OST event_f2 will trigger one-shot mode action. 0: disable, 1: enable. (R/W)
PWM_FH0_SW_OST Enable register for software-forced one-shot mode action. 0: disable, 1: en-
able. (R/W)
PWM_FH0_F0_CBC event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W)
PWM_FH0_F1_CBC event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W)
PWM_FH0_F2_CBC event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W)
H0 CP BC
E_ T
LR SE
PW FH0 RC OS
C
ST
_C UL
O E_
_O
_F RC
_F CB
PW FH0 FO
_ _
_
M H0
)
ed
PW _F
rv
_
M
M
se
PW
(re
31 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_FH0_FORCE_OST A toggle (software negation of this bit’s value) triggers a one-shot mode
action. (R/W)
PWM_FH0_CBCPULSE The cycle-by-cycle mode action refresh moment selection. When bit0 is set
to 1: TEZ; when bit1 is set to 1: TEP. (R/W)
N
BC N
_O
_C T_O
H0 S
_F _O
M H0
d)
ve
PW _F
r
M
se
PW
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_FH0_OST_ON Set and reset by hardware. If set, a one-shot mode action is on-going. (RO)
PWM_FH0_CBC_ON Set and reset by hardware. If set, a cycle-by-cycle mode action is on-going.
(RO)
_F LL
L
D
UL
HO
HO
DW FU
SH W_
ET
ET
M
M
A_ D
1_ _SH
UP
UP
B_
A_
EN _B
1_
1_
_G 1
M EN
EN
EN
)
ed
PW _G
_G
_G
rv
M
se
PW
PW
PW
(re
31 10 9 8 7 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN1_B_SHDW_FULL Set and reset by hardware. If set, PWM generator 1 time stamp B’s
shadow register is filled and to be transferred to time stamp B’s active register. If cleared, time
stamp B’s active register has been updated with shadow register’s latest value. (RO)
PWM_GEN1_A_SHDW_FULL Set and reset by hardware. If set, PWM generator 1 time stamp A’s
shadow register is filled and to be transferred to time stamp A’s active register. If cleared, time
stamp A’s active register has been updated with shadow register latest value. (RO)
PWM_GEN1_B_UPMETHOD Updating method for PWM generator 1 time stamp B’s active register.
0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync;
when bit3 is set to 1: disable the update. (R/W)
PWM_GEN1_A_UPMETHOD Updating method for PWM generator 1 time stamp A’s active register.
0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync;
when bit3 is set to 1: disable the update. (R/W)
_G
e
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
_G
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
D
HO
ET
PM
EL
EL
_U
_S
_S
G
CF
T1
T0
1_
1_
1_
EN
EN
EN
)
ed
_G
_G
_G
rv
M
se
PW
PW
PW
(re
31 10 9 7 6 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN1_T1_SEL Source selection for PWM generator1 event_t1, taking effect immediately, 0:
fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W)
PWM_GEN1_T0_SEL Source selection for PWM generator1 event_t0, taking effect immediately, 0:
fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W)
D
HO
DE
DE
ET
E
NT CE DE
O
RC OD
M
M
_M
O
UP
E_
IF E_M
1_ CIF E_M
CE
RC
E_
E
R
C
RC
O
O
B_ FOR
R
UF
UF
O
FO
FO
T
I
TU
N1 NC
N1 NC
N1 NC
CN
_C
N
CN
_
A_
_G _B
B
_G _A
_G _A
_
1_
1_
N1
EN
EN
EN
)
PW GE
PW E
PW GE
PW E
ed
_G
_G
rv
_
M
M
se
PW
PW
PW
(re
31 16 15 14 13 12 11 10 9 8 7 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x20 Reset
EB
EB
A
EP
EA
EP
Z
EZ
TE
TE
1
T0
DT
DT
DT
DT
UT
UT
UT
UT
UT
_D
_D
_U
A_
A_
A_
A_
A_
A_
A_
A_
A_
A
A
1_
1_
1_
1_
1_
1_
1_
1_
1_
1_
1_
1_
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
)
ed
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
rv
M
se
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
(re
31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN1_A_DT0 Action on PWM1A triggered by event_t0 when the timer decreases. (R/W)
PWM_GEN1_A_DTEB Action on PWM1A triggered by event TEB when the timer decreases. (R/W)
PWM_GEN1_A_DTEA Action on PWM1A triggered by event TEA when the timer decreases. (R/W)
PWM_GEN1_A_DTEP Action on PWM1A triggered by event TEP when the timer decreases. (R/W)
PWM_GEN1_A_DTEZ Action on PWM1A triggered by event TEZ when the timer decreases. (R/W)
PWM_GEN1_A_UT1 Action on PWM1A triggered by event_t1 when the timer increases. (R/W)
PWM_GEN1_A_UT0 Action on PWM1A triggered by event_t0 when the timer increases. (R/W)
PWM_GEN1_A_UTEB Action on PWM1A triggered by event TEB when the timer increases. (R/W)
PWM_GEN1_A_UTEA Action on PWM1A triggered by event TEA when the timer increases. (R/W)
PWM_GEN1_A_UTEP Action on PWM1A triggered by event TEP when the timer increases. (R/W)
PWM_GEN1_A_UTEZ Action on PWM1A triggered by event TEZ when the timer increases. (R/W)
EB
EB
A
EP
EA
EP
Z
EZ
TE
TE
1
T0
DT
DT
DT
DT
UT
UT
UT
UT
UT
_D
_D
_U
B_
B_
B_
B_
B_
B_
B_
B_
B_
B
B
1_
1_
1_
1_
1_
1_
1_
1_
1_
1_
1_
1_
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
)
ed
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
rv
M
se
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
(re
31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN1_B_DT0 Action on PWM1B triggered by event_t0 when the timer decreases. (R/W)
PWM_GEN1_B_DTEB Action on PWM1B triggered by event TEB when the timer decreases. (R/W)
PWM_GEN1_B_DTEA Action on PWM1B triggered by event TEA when the timer decreases. (R/W)
PWM_GEN1_B_DTEP Action on PWM1B triggered by event TEP when the timer decreases. (R/W)
PWM_GEN1_B_DTEZ Action on PWM1B triggered by event TEZ when the timer decreases. (R/W)
PWM_GEN1_B_UT1 Action on PWM1B triggered by event_t1 when the timer increases. (R/W)
PWM_GEN1_B_UT0 Action on PWM1B triggered by event_t0 when the timer increases. (R/W)
PWM_GEN1_B_UTEB Action on PWM1B triggered by event TEB when the timer increases. (R/W)
PWM_GEN1_B_UTEA Action on PWM1B triggered by event TEA when the timer increases. (R/W)
PWM_GEN1_B_UTEP Action on PWM1B triggered by event TEP when the timer increases. (R/W)
PWM_GEN1_B_UTEZ Action on PWM1B triggered by event TEZ when the timer increases. (R/W)
D
T
D
T
PW _D 1_B D_ EL ER
HO
PW _D 1_R D_I TIN ER
HO
PW _D 1_R D_O YP SS
PW _D 1_F D_ TIN S
M T E U AS
M T E S V
EB TS P
O P
M T E U V
ET
M T E TB A
ET
_D U WA
DE
_M WA
_D _A U EL
PW _D 1_F OU YP
PM
PM
PW _D 1_A OU L
M T1 _O NS
M T _ TB
T1 O S
M T _ E
N
O
_U
PW _D 1_B K_S
_U
I
ED
ED
M T L
_
PW _D _C
_R
_F
M T1
T1
T1
d)
PW _D
_D
_D
ve
er
M
s
PW
PW
PW
31 (re 18 17 16 15 14 13 12 11 10 9 8 7 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Reset
PWM_DT1_RED_UPMETHOD Updating method for RED active register. 0: immediately; when bit0
is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1:
disable the update. (R/W)
PWM_DT1_FED_UPMETHOD Updating method for FED active register. 0: immediately; when bit0
is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when bit3 is set to 1:
disable the update. (R/W)
_D
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ED
_R
T1
)
ed
_D
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
T
ER
LE
_I T
TH
UT R
NV
CA
O VE
TY
ES
1_ _IN
SH
DU
PR
EN
ER IN
O
RI 1_
1_
1_
1_
1_
AR IER
ER
ER
ER
ER
RI
RI
RI
RI
_C R
M AR
AR
AR
AR
AR
d)
PW _C
_C
_C
_C
_C
e
rv
M
se
PW
PW
PW
PW
PW
(re
31 14 13 12 11 8 7 5 4 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_CARRIER1_IN_INVERT When set, invert the input of PWM1A and PWM1B for this submodule.
(R/W)
PWM_CARRIER1_OUT_INVERT When set, invert the output of PWM1A and PWM1B for this sub-
module. (R/W)
PWM_CARRIER1_OSHWTH Width of the first pulse in number of periods of the carrier. (R/W)
PWM_CARRIER1_PRESCALE PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk = pe-
riod of PWM_clk * (PWM_CARRIER1_PRESCALE + 1). (R/W)
PWM_CARRIER1_EN When set, carrier1 function is enabled. When cleared, carrier1 is bypassed.
(R/W)
_U
_U
M H1 0_O D
_U
_D
_U
_D
BC
M H1 0_C ST
C_
PW _F 1_F C_
M H1 1_C C
H1 2_ C
W C
M H 1 T
M H 2 T
M H W T
BC
BC
ST
ST
ST
ST
PW _F _F S
PW _F 1_F _OS
PW _F 1_S _OS
PW _F _F B
_F _F B
_S CB
PW _F 1_F _O
_C
CB
B
_O
_C
_O
_C
PW _F A_C
B_
_
_B
_B
_B
_A
_A
_A
1_
_
H1
H1
H1
H1
H1
H1
PW FH1
)
M H
ed
_F
_F
_F
_F
_F
_F
_F
rv
_
M
M
se
PW
PW
PW
PW
PW
PW
PW
PW
(re
31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_FH1_B_OST_U One-shot mode action on PWM1B when a fault event occurs and the timer is
increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH1_B_OST_D One-shot mode action on PWM1B when a fault event occurs and the timer is
decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH1_B_CBC_U Cycle-by-cycle mode action on PWM1B when a fault event occurs and the
timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH1_B_CBC_D Cycle-by-cycle mode action on PWM1B when a fault event occurs and the
timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH1_A_OST_U One-shot mode action on PWM1A when a fault event occurs and the timer is
increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH1_A_OST_D One-shot mode action on PWM1A when a fault event occurs and the timer is
decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH1_A_CBC_U Cycle-by-cycle mode action on PWM1A when a fault event occurs and the
timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH1_A_CBC_D Cycle-by-cycle mode action on PWM1A when a fault event occurs and the
timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH1_F0_OST Enable event_f0 to trigger one-shot mode action. 0: disable, 1: enable. (R/W)
PWM_FH1_F1_OST Enable event_f1 to trigger one-shot mode action. 0: disable, 1: enable. (R/W)
PWM_FH1_F2_OST Enable event_f2 to trigger one-shot mode action. 0: disable, 1: enable. (R/W)
PWM_FH1_SW_OST Enable the register for software-forced one-shot mode action. 0: disable, 1:
enable. (R/W)
PWM_FH1_F2_CBC Enable event_f2 to will trigger cycle-by-cycle mode action. 0: disable, 1: en-
able. (R/W)
PWM_FH1_SW_CBC Enable the register for software-forced cycle-by-cycle mode action. 0: disable,
1: enable. (R/W)
H1 CP BC
E_ T
LR SE
PW FH1 RC OS
C
ST
_C UL
O E_
_O
_F RC
_F CB
PW FH1 FO
_ _
_
M H1
)
ed
PW _F
rv
_
M
M
se
PW
(re
31 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_FH1_FORCE_OST A toggle (software negation of this bit’s value) triggers a one-shot mode
action. (R/W)
PWM_FH1_CBCPULSE The cycle-by-cycle mode action refresh moment selection. When bit0 is set
to 1: TEZ; when bit1 is set to 1: TEP. (R/W)
N
BC N
_O
_C T_O
H1 S
_F _O
M H1
d)
ve
PW _F
r
M
se
PW
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_FH1_OST_ON Set and reset by hardware. If set, a one-shot mode action is on-going. (RO)
PWM_FH1_CBC_ON Set and reset by hardware. If set, a cycle-by-cycle mode action is on-going.
(RO)
_F LL
L
D
UL
HO
HO
DW FU
SH W_
ET
ET
M
M
A_ D
2_ _SH
UP
UP
B_
A_
EN _B
2_
2_
_G 2
M EN
EN
EN
)
ed
PW _G
_G
_G
rv
M
se
PW
PW
PW
(re
31 10 9 8 7 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN2_B_SHDW_FULL Set and reset by hardware. If set, PWM generator 2 time stamp B’s
shadow register is filled and to be transferred to time stamp B’s active register. If cleared, time
stamp B’s active register has been updated with shadow register’s latest value. (RO)
PWM_GEN2_A_SHDW_FULL Set and reset by hardware. If set, PWM generator 2 time stamp A’s
shadow register is filled and to be transferred to time stamp A’s active register. If cleared, time
stamp A’s active register has been updated with shadow register’s latest value. (RO)
PWM_GEN2_B_UPMETHOD Updating method for PWM generator 2 time stamp B’s active register.
0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync;
when bit3 is set to 1: disable the update. (R/W)
PWM_GEN2_A_UPMETHOD Updating method for PWM generator 2 time stamp A’s active register.
0: immediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync;
when bit3 is set to 1: disable the update. (R/W)
_G
e
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
_G
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
D
HO
ET
PM
EL
EL
_U
_S
_S
G
CF
T1
T0
2_
2_
2_
EN
EN
EN
)
ed
_G
_G
_G
rv
M
se
PW
PW
PW
(re
31 10 9 7 6 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN2_T1_SEL Source selection for PWM generator2 event_t1, take effect immediately, 0:
fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W)
PWM_GEN2_T0_SEL Source selection for PWM generator2 event_t0, take effect immediately, 0:
fault_event0, 1: fault_event1, 2: fault_event2, 3: sync_taken, 4: none. (R/W)
D
HO
DE
DE
ET
E
NT CE DE
O
RC OD
M
M
_M
O
UP
E_
IF E_M
2_ CIF E_M
CE
RC
E_
E
R
C
RC
O
O
B_ FOR
R
UF
UF
O
FO
FO
T
I
TU
N2 NC
N2 NC
N2 NC
CN
_C
N
CN
_
A_
_G _B
B
_G _A
_G _A
_
2_
2_
N2
EN
EN
EN
)
PW GE
PW E
PW GE
PW E
ed
_G
_G
rv
_
M
M
se
PW
PW
PW
(re
31 16 15 14 13 12 11 10 9 8 7 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x20 Reset
EB
EB
A
EP
EA
EP
Z
EZ
TE
TE
1
T0
DT
DT
DT
DT
UT
UT
UT
UT
UT
_D
_D
_U
A_
A_
A_
A_
A_
A_
A_
A_
A_
A
A
2_
2_
2_
2_
2_
2_
2_
2_
2_
2_
2_
2_
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
)
ed
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
rv
M
se
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
(re
31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN2_A_DT0 Action on PWM2A triggered by event_t0 when the timer decreases. (R/W)
PWM_GEN2_A_DTEB Action on PWM2A triggered by event TEB when the timer decreases. (R/W)
PWM_GEN2_A_DTEA Action on PWM2A triggered by event TEA when the timer decreases. (R/W)
PWM_GEN2_A_DTEP Action on PWM2A triggered by event TEP when the timer decreases. (R/W)
PWM_GEN2_A_DTEZ Action on PWM2A triggered by event TEZ when the timer decreases. (R/W)
PWM_GEN2_A_UT1 Action on PWM2A triggered by event_t1 when the timer increases. (R/W)
PWM_GEN2_A_UT0 Action on PWM2A triggered by event_t0 when the timer increases. (R/W)
PWM_GEN2_A_UTEB Action on PWM2A triggered by event TEB when the timer increases. (R/W)
PWM_GEN2_A_UTEA Action on PWM2A triggered by event TEA when the timer increases. (R/W)
PWM_GEN2_A_UTEP Action on PWM2A triggered by event TEP when the timer increases. (R/W)
PWM_GEN2_A_UTEZ Action on PWM2A triggered by event TEZ when the timer increases. (R/W)
EB
EB
A
EP
EA
EP
Z
EZ
TE
TE
1
T0
DT
DT
DT
DT
UT
UT
UT
UT
UT
_D
_D
_U
B_
B_
B_
B_
B_
B_
B_
B_
B_
B
B
2_
2_
2_
2_
2_
2_
2_
2_
2_
2_
2_
2_
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
EN
)
ed
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
_G
rv
M
se
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
PW
(re
31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_GEN2_B_DT0 Action on PWM2B triggered by event_t0 when the timer decreases. (R/W)
PWM_GEN2_B_DTEB Action on PWM2B triggered by event TEB when the timer decreases. (R/W)
PWM_GEN2_B_DTEA Action on PWM2B triggered by event TEA when the timer decreases. (R/W)
PWM_GEN2_B_DTEP Action on PWM2B triggered by event TEP when the timer decreases. (R/W)
PWM_GEN2_B_DTEZ Action on PWM2B triggered by event TEZ when the timer decreases. (R/W)
PWM_GEN2_B_UT1 Action on PWM2B triggered by event_t1 when the timer increases. (R/W)
PWM_GEN2_B_UT0 Action on PWM2B triggered by event_t0 when the timer increases. (R/W)
PWM_GEN2_B_UTEB Action on PWM2B triggered by event TEB when the timer increases. (R/W)
PWM_GEN2_B_UTEA Action on PWM2B triggered by event TEA when the timer increases. (R/W)
PWM_GEN2_B_UTEP Action on PWM2B triggered by event TEP when the timer increases. (R/W)
PWM_GEN2_B_UTEZ Action on PWM2B triggered by event TEZ when the timer increases. (R/W)
D
T
D
T
PW _D 2_B D_ EL ER
HO
PW _D 2_R D_I TIN ER
HO
PW _D 2_R D_O YP SS
PW _D 2_F D_ TIN S
M T E U AS
M T E S V
EB TS P
O P
M T E U V
ET
M T E TB A
ET
_D U WA
DE
_M WA
_D _A U EL
PW _D 2_F OU YP
PM
PM
PW _D 2_A OU L
M T2 _O NS
M T _ TB
T2 O S
M T _ E
N
O
_U
PW _D 2_B K_S
_U
I
ED
ED
M T L
_
PW _D _C
_R
_F
M T2
T2
T2
d)
PW _D
_D
_D
ve
er
M
s
PW
PW
PW
31 (re 18 17 16 15 14 13 12 11 10 9 8 7 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 Reset
PWM_DT2_DEB_MODE S8 in Table 73, dual-edge B mode, 0: FED/RED take effect on different path
separately, 1: FED/RED take effect on B path. (R/W)
PWM_DT2_RED_UPMETHOD Updating method for RED (rising edge delay) active register. 0: im-
mediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when
bit3 is set to 1: disable the update. (R/W)
PWM_DT2_FED_UPMETHOD Updating method for FED (falling edge delay) active register. 0: im-
mediately; when bit0 is set to 1: TEZ; when bit1 is set to 1: TEP; when bit2 is set to 1: sync; when
bit3 is set to 1: disable the update. (R/W)
_D
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
ED
_R
T2
)
ed
_D
rv
M
se
PW
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
T
ER
LE
_I T
TH
UT R
NV
CA
O VE
TY
ES
2_ _IN
SH
DU
PR
EN
ER IN
O
RI 2_
2_
2_
2_
2_
AR IER
ER
ER
ER
ER
RI
RI
RI
RI
_C R
M AR
AR
AR
AR
AR
d)
PW _C
_C
_C
_C
_C
e
rv
M
se
PW
PW
PW
PW
PW
(re
31 14 13 12 11 8 7 5 4 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_CARRIER2_IN_INVERT When set, invert the input of PWM2A and PWM2B for this submodule.
(R/W)
PWM_CARRIER2_OUT_INVERT When set, invert the output of PWM2A and PWM2B for this sub-
module. (R/W)
PWM_CARRIER2_OSHWTH Width of the first pulse in number of periods of the carrier. (R/W)
PWM_CARRIER2_PRESCALE PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk = pe-
riod of PWM_clk * (PWM_CARRIER2_PRESCALE + 1). (R/W)
PWM_CARRIER2_EN When set, carrier2 function is enabled. When cleared, carrier2 is bypassed.
(R/W)
_U
_U
M H2 0_O D
_U
_D
_U
_D
BC
M H2 0_C ST
C_
PW _F 2_F C_
M H2 1_C C
H2 2_ C
W C
M H 1 T
M H 2 T
M H W T
BC
BC
ST
ST
ST
ST
PW _F _F S
PW _F 2_F _OS
PW _F 2_S _OS
PW _F _F B
_F _F B
_S CB
PW _F 2_F _O
_C
CB
B
_O
_C
_O
_C
PW _F A_C
B_
_
_B
_B
_B
_A
_A
_A
2_
_
H2
H2
H2
H2
H2
H2
PW FH2
)
M H
ed
_F
_F
_F
_F
_F
_F
_F
rv
_
M
M
se
PW
PW
PW
PW
PW
PW
PW
PW
(re
31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_FH2_B_OST_U One-shot mode action on PWM2B when a fault event occurs and the timer is
increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH2_B_OST_D One-shot mode action on PWM2B when a fault event occurs and the timer is
decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH2_B_CBC_U Cycle-by-cycle mode action on PWM2B when a fault event occurs and the
timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH2_B_CBC_D Cycle-by-cycle mode action on PWM2B when a fault event occurs and the
timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH2_A_OST_U One-shot mode action on PWM2A when a fault event occurs and the timer is
increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH2_A_OST_D One-shot mode action on PWM2A when a fault event occurs and the timer is
decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH2_A_CBC_U Cycle-by-cycle mode action on PWM2A when a fault event occurs and the
timer is increasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH2_A_CBC_D Cycle-by-cycle mode action on PWM2A when a fault event occurs and the
timer is decreasing. 0: do nothing, 1: force low, 2: force high, 3: toggle. (R/W)
PWM_FH2_F0_OST event_f0 will trigger one-shot mode action. 0: disable, 1: enable. (R/W)
PWM_FH2_F1_OST event_f1 will trigger one-shot mode action. 0: disable, 1: enable. (R/W)
PWM_FH2_F2_OST event_f2 will trigger one-shot mode action. 0: disable, 1: enable. (R/W)
PWM_FH2_SW_OST Enable register for software-forced one-shot mode action. 0: disable, 1: en-
able. (R/W)
PWM_FH2_F0_CBC event_f0 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W)
PWM_FH2_F1_CBC event_f1 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W)
PWM_FH2_F2_CBC event_f2 will trigger cycle-by-cycle mode action. 0: disable, 1: enable. (R/W)
H2 CP BC
E_ T
LR SE
PW FH2 RC OS
C
ST
_C UL
O E_
_O
_F RC
_F CB
PW FH2 FO
_ _
_
M H2
)
ed
PW _F
rv
_
M
M
se
PW
(re
31 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_FH2_FORCE_OST A toggle (software negation of this bit’s value) triggers a one-shot mode
action. (R/W)
PWM_FH2_CBCPULSE The cycle-by-cycle mode action refresh moment selection. When bit0 is set
to 1: TEZ; when bit1 is set to 1:TEP. (R/W)
N
BC N
_O
_C T_O
H2 S
_F _O
M H2
d)
ve
PW _F
r
M
se
PW
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_FH2_OST_ON Set and reset by hardware. If set, a one-shot mode action is on-going. (RO)
PWM_FH2_CBC_ON Set and reset by hardware. If set, a cycle-by-cycle mode action is on-going.
(RO)
PW _E EN F2
PW _F EN F1
PW _F _PO F0
PW _F _PO E
PW _F _PO E
M 2 _E LE
M V _
M V _
M 2 _
L
M 0 L
T
T
T
PW _F N
_F N
EN
PW _E EN
M 1_E
0_
d)
M V
1
PW _E
ve
r
M
se
PW
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_F2_POLE Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
level high. (R/W)
PWM_F1_POLE Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
level high. (R/W)
PWM_F0_POLE Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low, 1:
level high. (R/W)
EL
SW
ER N
N
_S
IM I_E
_E
C_
CI
_T C
YN
YN
AP YN
_S
_S
_C _S
AP
AP
M AP
)
ed
_C
_C
PW _C
rv
M
se
PW
PW
PW
(re
31 6 5 4 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_CAP_SYNC_SW Set this bit to force a capture timer sync; the capture timer is loaded with the
value in the phase register. (WO)
PWM_CAP_TIMER_EN When set, the capture timer incrementing under APB_clk is enabled. (R/W)
31 0
0 Reset
PWM_CAP_TIMER_PHASE_REG Phase value for the capture timer sync operation. (R/W)
LE
T
ER
CA
NV
E
ES
AP OD
_I
AP _SW
PR
EN
IN
_C _M
0_
0_
0_
_C 0
P0
M AP
AP
)
PW CA
ed
PW _C
_C
rv
_
M
M
se
PW
PW
PW
(re
31 13 12 11 10 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_CAP0_IN_INVERT When set, CAP0 form GPIO matrix is inverted before prescaling. (R/W)
PWM_CAP0_MODE Edge of capture on channel 0 after prescaling. When bit0 is set to 1: enable
capture on the negative edge; When bit1 is set to 1: enable capture on the positive edge. (R/W)
CA
VE
E
ES
N
AP OD
_I
AP _SW
PR
EN
IN
_C _M
1_
1_
1_
_C 1
P1
M AP
AP
)
PW CA
ed
PW _C
_C
rv
_
M
M
se
PW
PW
PW
(re
31 13 12 11 10 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_CAP1_IN_INVERT When set, CAP1 form GPIO matrix is inverted before prescaling. (R/W)
PWM_CAP1_MODE Edge of capture on channel 1 after prescaling. When bit0 is set to 1: enable
capture on the negative edge; When bit1 is set to 1: enable capture on the positive edge. (R/W)
LE
T
ER
CA
NV
E
ES
AP OD
_I
AP _SW
PR
EN
IN
_C _M
2_
2_
2_
_C 2
P2
M AP
AP
d)
PW CA
PW _C
_C
ve
_
er
M
s
PW
PW
PW
(re
31 13 12 11 10 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_CAP2_IN_INVERT When set, CAP2 form GPIO matrix is inverted before prescaling. (R/W)
PWM_CAP2_MODE Edge of capture on channel 2 after prescaling. When bit0 is set to 1: enable
capture on the negative edge; when bit1 is set to 1: enable capture on the positive edge. (R/W)
31 0
0 Reset
31 0
0 Reset
31 0
0 Reset
AP _ED E
ED E
E
_C 1 G
0_ G
G
M AP ED
_
PW _C 2
M AP
d)
PW _C
ver
M
se
PW
(re
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PWM_CAP2_EDGE Edge of the last capture trigger on channel 2. 0: posedge; 1: negedge. (RO)
PWM_CAP1_EDGE Edge of the last capture trigger on channel 1. 0: posedge; 1: negedge. (RO)
PWM_CAP0_EDGE Edge of the last capture trigger on channel 0. 0: posedge; 1: negedge. (RO)
N P
_E _U
UP E
PW _O 1_F _E _UP
PW _O 0_F _E _UP
_G B E P
L_ RC
M LO P_ E_U
M P P E
M P P E
BA _FO
N
LO AL N
PW _O 2_U RC
PW _O 1_U RC
PW _G 0_U RC
M P O
M P O
M P O
PW _O 2_F
M P
)
ed
PW _O
rv
M
se
PW
(re
31 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 Reset
PWM_OP2_FORCE_UP A toggle (software negation of this bit’s value) will trigger a forced update of
active registers in PWM operator 2. (R/W)
PWM_OP2_UP_EN When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM
operator 2 are enabled (R/W)
PWM_OP1_FORCE_UP A toggle (software negation of this bit’s value) will trigger a forced update of
active registers in PWM operator 1. (R/W)
PWM_OP1_UP_EN When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM
operator 1 are enabled. (R/W)
PWM_OP0_FORCE_UP A toggle (software negation of this bit’s value) will trigger a forced update of
active registers in PWM operator 0. (R/W)
PWM_OP0_UP_EN When set and PWM_GLOBAL_UP_EN is set, update of active registers in PWM
operator 0 are enabled. (R/W)
PWM_GLOBAL_FORCE_UP A toggle (software negation of this bit’s value) will trigger a forced update
of all active registers in the MCPWM module. (R/W)
PWM_GLOBAL_UP_EN The global enable of update of all active registers in the MCPWM module.
(R/W)
O INT NA
T_ A
A
IN EN
EN
IN FA T2 LR T_ NA
IN FA T1 T_ T_ NA
IN TIM T0 T_ A NA
IN TIM R2 EP T_ A
IN TIM R1 EZ T_ A
IN TIM R0 EZ T_ A
IN TIM R2 EZ T_ A
TI R1 TO T A
0_ OP INT A
ST _ _E
T_ E _T _IN EN
T_ E _T _IN EN
T_ E _T _IN EN
T_ E _T _IN EN
T_ E _S _IN EN
ER ST _ N
P_ _
T_ UL _C _IN E
T_ UL _IN _IN E
T_ UL _IN EN E
T_ 2_ C T_ A
T_ 1 B T_ A
T_ 0 B T_ A
M _ P _E
T_ 2_ B T_ A
T_ 1 A T_ A
T_ 0 A T_ A
T_ 2_ T T_ A
T_ 1_ C T_ A
T_ 0_ C T_ A
T_ UL A T_ A
T_ UL _C T_ A
T_ UL _C _IN A
IN FA T0 LR T_
IN TIM R0 EP T_
IN OP CB _IN EN
IN OP TE _IN EN
IN OP _TE _IN EN
IN OP _TE _IN EN
IN OP TE _IN EN
IN OP _TE _IN EN
IN FH OS IN EN
IN FH CB _IN EN
IN FH CB _IN EN
IN FA _TE _IN EN
IN FA T2 _IN EN
IN FA T1 LR EN
IN TIM R2 T_ A
IN TIM R1 EP A
T_ E _IN EN
T_ E _T EN
T_ E _T _IN
T_ P T A
T_ 2_ T A
T_ 1_ T A
T_ 0_ T_ T_
IN CA 1_IN _EN
IN FH 0_IN _EN
IN FH OS _EN
IN FH OS _IN
T_ P T
IN CA 2_IN
T_ )
d
T_ P
ve
IN AC
er
s
(re
IN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
INT_CAP2_INT_ENA The enable bit for the interrupt triggered by capture on channel 2. (R/W)
INT_CAP1_INT_ENA The enable bit for the interrupt triggered by capture on channel 1. (R/W)
INT_CAP0_INT_ENA The enable bit for the interrupt triggered by capture on channel 0. (R/W)
INT_FH2_OST_INT_ENA The enable bit for the interrupt triggered by a one-shot mode action on
PWM2. (R/W)
INT_FH1_OST_INT_ENA The enable bit for the interrupt triggered by a one-shot mode action on
PWM0. (R/W)
INT_FH0_OST_INT_ENA The enable bit for the interrupt triggered by a one-shot mode action on
PWM0. (R/W)
INT_FH2_CBC_INT_ENA The enable bit for the interrupt triggered by a cycle-by-cycle mode action
on PWM2. (R/W)
INT_FH1_CBC_INT_ENA The enable bit for the interrupt triggered by a cycle-by-cycle mode action
on PWM1. (R/W)
INT_FH0_CBC_INT_ENA The enable bit for the interrupt triggered by a cycle-by-cycle mode action
on PWM0. (R/W)
INT_OP2_TEB_INT_ENA The enable bit for the interrupt triggered by a PWM operator 2 TEB event
(R/W)
INT_OP1_TEB_INT_ENA The enable bit for the interrupt triggered by a PWM operator 1 TEB event
(R/W)
INT_OP0_TEB_INT_ENA The enable bit for the interrupt triggered by a PWM operator 0 TEB event
(R/W)
INT_OP2_TEA_INT_ENA The enable bit for the interrupt triggered by a PWM operator 2 TEA event
(R/W)
INT_OP1_TEA_INT_ENA The enable bit for the interrupt triggered by a PWM operator 1 TEA event
(R/W)
INT_OP0_TEA_INT_ENA The enable bit for the interrupt triggered by a PWM operator 0 TEA event
(R/W)
INT_FAULT2_CLR_INT_ENA The enable bit for the interrupt triggered when event_f2 ends. (R/W)
INT_FAULT1_CLR_INT_ENA The enable bit for the interrupt triggered when event_f1 ends. (R/W)
INT_FAULT0_CLR_INT_ENA The enable bit for the interrupt triggered when event_f0 ends. (R/W)
INT_FAULT2_INT_ENA The enable bit for the interrupt triggered when event_f2 starts. (R/W)
INT_FAULT1_INT_ENA The enable bit for the interrupt triggered when event_f1 starts. (R/W)
INT_FAULT0_INT_ENA The enable bit for the interrupt triggered when event_f0 starts. (R/W)
INT_TIMER2_TEP_INT_ENA The enable bit for the interrupt triggered by a PWM timer 2 TEP event.
(R/W)
INT_TIMER1_TEP_INT_ENA The enable bit for the interrupt triggered by a PWM timer 1 TEP event.
(R/W)
Continued on the next page...
INT_TIMER0_TEP_INT_ENA The enable bit for the interrupt triggered by a PWM timer 0 TEP event.
(R/W)
INT_TIMER2_TEZ_INT_ENA The enable bit for the interrupt triggered by a PWM timer 2 TEZ event.
(R/W)
INT_TIMER1_TEZ_INT_ENA The enable bit for the interrupt triggered by a PWM timer 1 TEZ event.
(R/W)
INT_TIMER0_TEZ_INT_ENA The enable bit for the interrupt triggered by a PWM timer 0 TEZ event.
(R/W)
INT_TIMER2_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 2 stops. (R/W)
INT_TIMER1_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 1 stops. (R/W)
INT_TIMER0_STOP_INT_ENA The enable bit for the interrupt triggered when the timer 0 stops. (R/W)
O INT AW
T_ W
W
IN FA T2 LR T_ AW
IN FA T1 T_ T_ AW
IN TIM T0 T_ AW AW
IN TIM R2 EP T_ AW
IN TIM R1 EZ T_ AW
IN TIM R0 EZ T_ AW
IN TIM R2 EZ T_ W
TI R1 TO T W
0_ OP INT W
IN RA
RA
ST _ _R
T_ E _T _IN RA
T_ E _S _IN RA
ER ST _ A
T_ 2_ C T_ W
T_ 1 B T_ W
T_ 0 B T_ W
P_ _
T_ 2_ B T_ W
T_ 1 A T_ W
T_ 0 A T_ W
T_ UL _C _IN R
T_ UL _IN _IN R
T_ UL _IN R R
T_ 2_ T T_ W
T_ 1_ C T_ W
T_ 0_ C T_ W
T_ UL A T_ W
T_ UL _C T_ W
T_ UL _C _IN W
T_ E _T _IN R
T_ E _T _IN R
T_ E _T _IN R
M _ P _R
IN FA T0 LR T_
IN TIM R0 EP T_
IN OP CB _IN RA
IN OP TE _IN RA
IN OP _TE _IN RA
IN TIM R2 T_ W
IN TIM R1 EP AW
IN OP _TE _IN RA
IN OP TE _IN RA
IN OP _TE _IN RA
IN FH OS IN RA
IN FH CB _IN RA
IN FH CB _IN RA
IN FA _TE _IN RA
IN FA T2 _IN RA
IN FA T1 LR RA
T_ P T AW
T_ 2_ T AW
T_ 1_ T AW
T_ E _IN RA
T_ E _T _IN
T_ 0_ T_ T_
T_ E _T R
IN CA 1_IN _R
IN FH 0_IN _R
IN FH OS _R
IN FH OS _IN
T_ P T
IN CA 2_IN
IN ed)
T_ P
IN CA
rv
se
T_
(re
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
INT_CAP2_INT_RAW The raw status bit for the interrupt triggered by capture on channel 2. (RO)
INT_CAP1_INT_RAW The raw status bit for the interrupt triggered by capture on channel 1. (RO)
INT_CAP0_INT_RAW The raw status bit for the interrupt triggered by capture on channel 0. (RO)
INT_FH2_OST_INT_RAW The raw status bit for the interrupt triggered by a one-shot mode action on
PWM2. (RO)
INT_FH1_OST_INT_RAW The raw status bit for the interrupt triggered by a one-shot mode action on
PWM0. (RO)
INT_FH0_OST_INT_RAW The raw status bit for the interrupt triggered by a one-shot mode action on
PWM0. (RO)
INT_FH2_CBC_INT_RAW The raw status bit for the interrupt triggered by a cycle-by-cycle mode
action on PWM2. (RO)
INT_FH1_CBC_INT_RAW The raw status bit for the interrupt triggered by a cycle-by-cycle mode
action on PWM1. (RO)
INT_FH0_CBC_INT_RAW The raw status bit for the interrupt triggered by a cycle-by-cycle mode
action on PWM0. (RO)
INT_OP2_TEB_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 2 TEB
event. (RO)
INT_OP1_TEB_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 1 TEB
event. (RO)
INT_OP0_TEB_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 0 TEB
event. (RO)
INT_OP2_TEA_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 2 TEA
event. (RO)
INT_OP1_TEA_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 1 TEA
event. (RO)
INT_OP0_TEA_INT_RAW The raw status bit for the interrupt triggered by a PWM operator 0 TEA
event. (RO)
INT_FAULT2_CLR_INT_RAW The raw status bit for the interrupt triggered when event_f2 ends. (RO)
INT_FAULT1_CLR_INT_RAW The raw status bit for the interrupt triggered when event_f1 ends. (RO)
INT_FAULT0_CLR_INT_RAW The raw status bit for the interrupt triggered when event_f0 ends. (RO)
INT_FAULT2_INT_RAW The raw status bit for the interrupt triggered when event_f2 starts. (RO)
INT_FAULT1_INT_RAW The raw status bit for the interrupt triggered when event_f1 starts. (RO)
INT_FAULT0_INT_RAW The raw status bit for the interrupt triggered when event_f0 starts. (RO)
INT_TIMER2_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 2 TEP
event. (RO)
INT_TIMER1_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 1 TEP
event. (RO)
Continued on the next page...
INT_TIMER0_TEP_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 0 TEP
event. (RO)
INT_TIMER2_TEZ_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 2 TEZ
event. (RO)
INT_TIMER1_TEZ_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 1 TEZ
event. (RO)
INT_TIMER0_TEZ_INT_RAW The raw status bit for the interrupt triggered by a PWM timer 0 TEZ
event. (RO)
INT_TIMER2_STOP_INT_RAW The raw status bit for the interrupt triggered when the timer 2 stops.
(RO)
INT_TIMER1_STOP_INT_RAW The raw status bit for the interrupt triggered when the timer 1 stops.
(RO)
INT_TIMER0_STOP_INT_RAW The raw status bit for the interrupt triggered when the timer 0 stops.
(RO)
O INT T
IN ST
ST
ST _ _S
IN FA T2 LR T_ T
IN FA T1 T_ T_ T
T
IN TIM R2 EP T_ T
T_ E _T _IN ST
IN TIM R0 EZ T_ T
T_ E _T _IN ST
T_ E _S _IN ST
ER ST _ T
P_ _
T_
T_ UL _C _IN S
T_ UL _IN _IN S
T_ UL _IN ST S
T_ E _T _IN S
T_ E _T _IN S
M _ P _S
0_ OP INT
IN FA T0 LR T_
IN TIM R0 EP T_
IN TIM R1 EZ T_
IN TIM R2 EZ T_
IN OP CB _IN ST
IN OP TE _IN ST
IN OP _TE _IN ST
IN OP _TE _IN ST
IN OP TE _IN ST
IN OP _TE _IN ST
IN FH OS IN ST
IN FH CB _IN ST
IN FH CB _IN ST
IN FA _TE _IN ST
IN FA T2 _IN ST
IN FA T1 LR ST
TI R1 TO T
T_ UL _C _IN
T_ E _T _IN
T_ E _IN ST
T_ E _T ST
T_ 0_ C T_
T_ 2_ C T_
T_ 1 B T_
T_ 0 B T_
T_ 2_ B T_
T_ 1 A T_
T_ 0_ T_ T_
T_ 2_ T T_
T_ 1_ C T_
T_ 0 A T_
T_ UL A T_
T_ UL _C T_
T_ P T T
T_ 2_ T T
T_ 1_ T T
IN TIM T0 T_
IN TIM 2 T_
IN TIM R1 EP
IN FH OS _IN
IN CA 1_IN _S
IN FH 0_IN _S
IN FH OS _S
T_ P T
IN CA 2_IN
R
T_ )
ed
T_ P
IN A
rv
C
se
(re
IN
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
INT_CAP2_INT_ST The masked status bit for the interrupt triggered by capture on channel 2. (RO)
INT_CAP1_INT_ST The masked status bit for the interrupt triggered by capture on channel 1. (RO)
INT_CAP0_INT_ST The masked status bit for the interrupt triggered by capture on channel 0. (RO)
INT_FH2_OST_INT_ST The masked status bit for the interrupt triggered by a one-shot mode action
on PWM2. (RO)
INT_FH1_OST_INT_ST The masked status bit for the interrupt triggered by a one-shot mode action
on PWM1. (RO)
INT_FH0_OST_INT_ST The masked status bit for the interrupt triggered by a one-shot mode action
on PWM0. (RO)
INT_FH2_CBC_INT_ST The masked status bit for the interrupt triggered by a cycle-by-cycle mode
action on PWM2. (RO)
INT_FH1_CBC_INT_ST The masked status bit for the interrupt triggered by a cycle-by-cycle mode
action on PWM1. (RO)
INT_FH0_CBC_INT_ST The masked status bit for the interrupt triggered by a cycle-by-cycle mode
action on PWM0. (RO)
INT_OP2_TEB_INT_ST The masked status bit for the interrupt triggered by a PWM operator 2 TEB
event. (RO)
INT_OP1_TEB_INT_ST The masked status bit for the interrupt triggered by a PWM operator 1 TEB
event. (RO)
INT_OP0_TEB_INT_ST The masked status bit for the interrupt triggered by a PWM operator 0 TEB
event. (RO)
INT_OP2_TEA_INT_ST The masked status bit for the interrupt triggered by a PWM operator 2 TEA
event. (RO)
INT_OP1_TEA_INT_ST The masked status bit for the interrupt triggered by a PWM operator 1 TEA
event. (RO)
INT_OP0_TEA_INT_ST The masked status bit for the interrupt triggered by a PWM operator 0 TEA
event. (RO)
INT_FAULT2_CLR_INT_ST The masked status bit for the interrupt triggered when event_f2 ends.
(RO)
INT_FAULT1_CLR_INT_ST The masked status bit for the interrupt triggered when event_f1 ends.
(RO)
INT_FAULT0_CLR_INT_ST The masked status bit for the interrupt triggered when event_f0 ends.
(RO)
INT_FAULT2_INT_ST The masked status bit for the interrupt triggered when event_f2 starts. (RO)
Continued on the next page...
INT_FAULT1_INT_ST The masked status bit for the interrupt triggered when event_f1 starts. (RO)
INT_FAULT0_INT_ST The masked status bit for the interrupt triggered when event_f0 starts. (RO)
INT_TIMER2_TEP_INT_ST The masked status bit for the interrupt triggered by a PWM timer 2 TEP
event. (RO)
INT_TIMER1_TEP_INT_ST The masked status bit for the interrupt triggered by a PWM timer 1 TEP
event. (RO)
INT_TIMER0_TEP_INT_ST The masked status bit for the interrupt triggered by a PWM timer 0 TEP
event. (RO)
INT_TIMER2_TEZ_INT_ST The masked status bit for the interrupt triggered by a PWM timer 2 TEZ
event. (RO)
INT_TIMER1_TEZ_INT_ST The masked status bit for the interrupt triggered by a PWM timer 1 TEZ
event. (RO)
INT_TIMER0_TEZ_INT_ST The masked status bit for the interrupt triggered by a PWM timer 0 TEZ
event. (RO)
INT_TIMER2_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 2 stops.
(RO)
INT_TIMER1_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 1 stops.
(RO)
INT_TIMER0_STOP_INT_ST The masked status bit for the interrupt triggered when the timer 0 stops.
(RO)
O INT LR
T_ R
R
IN CL
CL
IN FA T2 LR T_ LR
IN FA T1 T_ T_ LR
IN TIM T0 T_ LR LR
IN TIM R2 EP T_ LR
IN TIM R1 EZ T_ LR
IN TIM R0 EZ T_ LR
IN TIM R2 EZ T_ LR
TI R1 TO T LR
0_ OP INT R
ST _ _C
ER ST _ L
P_ _
T_ UL _C _IN C
T_ UL _IN _IN C
T_ UL _IN C C
T_ E _T _IN C
T_ E _T _IN C
T_ E _T _IN C
T_ E _T _IN C
T_ E _S _IN C
M _ P _C
T_ 2 C T_ R
T_ 1_ B T_ R
T_ 0 B T_ R
T_ 2_ B T_ R
T_ 1 A T_ R
T_ 0 A T_ R
T_ 2_ T T_ R
T_ 1_ C T_ R
T_ 0_ C T_ R
T_ UL A T_ R
T_ UL _C T_ R
T_ UL _C _IN R
IN FA T0 LR T_
IN TIM R0 EP T_
IN OP CB _IN CL
IN OP _TE _IN CL
IN OP TE _IN CL
IN OP _TE _IN CL
IN OP TE _IN CL
IN OP _TE _IN CL
IN FH OS _IN CL
IN FH CB _IN CL
IN FH CB _IN CL
IN FA _TE _IN CL
IN FA T2 _IN CL
IN FA T1 LR CL
IN TIM R2 T_ LR
IN TIM R1 EP LR
T_ E _T _IN
T_ P T LR
T_ 2_ T LR
T_ 1_ T_ LR
T_ 0_ T T_
T_ E _IN C
T_ E _T C
IN CA 1_IN _C
IN FH 0_IN _C
IN FH OS _C
IN FH OS IN
T_ P T
IN CA 2_IN
IN ed)
T_ P
IN CA
v
er
T_
s
(re
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
INT_CAP2_INT_CLR Set this bit to clear interrupt triggered by capture on channel 2. (WO)
INT_CAP1_INT_CLR Set this bit to clear interrupt triggered by capture on channel 1. (WO)
INT_CAP0_INT_CLR Set this bit to clear interrupt triggered by capture on channel 0. (WO)
INT_FH2_OST_INT_CLR Set this bit to clear interrupt triggered by a one-shot mode action on PWM2.
(WO)
INT_FH1_OST_INT_CLR Set this bit to clear interrupt triggered by a one-shot mode action on PWM1.
(WO)
INT_FH0_OST_INT_CLR Set this bit to clear interrupt triggered by a one-shot mode action on PWM0.
(WO)
INT_FH2_CBC_INT_CLR Set this bit to clear interrupt triggered by a cycle-by-cycle mode action on
PWM2. (WO)
INT_FH1_CBC_INT_CLR Set this bit to clear interrupt triggered by a cycle-by-cycle mode action on
PWM1. (WO)
INT_FH0_CBC_INT_CLR Set this bit to clear interrupt triggered by a cycle-by-cycle mode action on
PWM0. (WO)
INT_OP2_TEB_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 2 TEB event.
(WO)
INT_OP1_TEB_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 1 TEB event.
(WO)
INT_OP0_TEB_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 0 TEB event.
(WO)
INT_OP2_TEA_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 2 TEA event.
(WO)
INT_OP1_TEA_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 1 TEA event.
(WO)
INT_OP0_TEA_INT_CLR Set this bit to clear interrupt triggered by a PWM operator 0 TEA event.
(WO)
INT_FAULT2_CLR_INT_CLR Set this bit to clear interrupt triggered when event_f2 ends. (WO)
INT_FAULT1_CLR_INT_CLR Set this bit to clear interrupt triggered when event_f1 ends. (WO)
INT_FAULT0_CLR_INT_CLR Set this bit to clear interrupt triggered when event_f0 ends. (WO)
INT_FAULT2_INT_CLR Set this bit to clear interrupt triggered when event_f2 starts. (WO)
INT_FAULT1_INT_CLR Set this bit to clear interrupt triggered when event_f1 starts. (WO)
INT_FAULT0_INT_CLR Set this bit to clear interrupt triggered when event_f0 starts. (WO)
INT_TIMER2_TEP_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 2 TEP event.
(WO)
Continued on the next page...
INT_TIMER1_TEP_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 1 TEP event.
(WO)
INT_TIMER0_TEP_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 0 TEP event.
(WO)
INT_TIMER2_TEZ_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 2 TEZ event.
(WO)
INT_TIMER1_TEZ_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 1 TEZ event.
(WO)
INT_TIMER0_TEZ_INT_CLR Set this bit to clear interrupt triggered by a PWM timer 0 TEZ event.
(WO)
INT_TIMER2_STOP_INT_CLR Set this bit to clear interrupt triggered when the timer 2 stops. (WO)
INT_TIMER1_STOP_INT_CLR Set this bit to clear interrupt triggered when the timer 1 stops. (WO)
INT_TIMER0_STOP_INT_CLR Set this bit to clear interrupt triggered when the timer 0 stops. (WO)
17. PULSE_CNT
17.1 Overview
The pulse counter module is designed to count the number of rising and/or falling edges of an input signal. Each
pulse counter unit has a 16-bit signed counter register and two channels that can be configured to either
increment or decrement the counter. Each channel has a signal input that accepts signal edges to be detected,
as well as a control input that can be used to enable or disable the signal input. The inputs have optional filters
that can be used to discard unwanted glitches in the signal.
The architecture of a pulse counter unit is illustrated in Figure 121. Each unit has two channels: ch0 and ch1,
which are functionally equivalent. Each channel has a signal input, as well as a control input, which can both be
connected to I/O pads. The counting behavior on both the positive and negative edge can be configured
separately to increase, decrease, or do nothing to the counter value. Separately, for both control signal levels, the
hardware can be configured to modify the edge action: invert it, disable it, or do nothing. The counter itself is a
16-bit signed up/down counter. Its value can be read by software directly, but is also monitored by a set of
comparators which can trigger an interrupt.
To summarize, a few examples have been considered. In this table, the effect on the counter for a rising edge is
shown for both a low and a high control signal, as well as various other configuration options. For clarity, a short
description in brackets is added after the values. Note: x denotes ’do not care’.
POS_ MODE LCTRL_ MODE HCTRL_ MODE sig l→h when ctrl=0 sig l→h when ctrl=1
1 (inc) 0 (-) 0 (-) Inc ctr Inc ctr
2 (dec) 0 (-) 0 (-) Dec ctr Dec ctr
0 (-) x x No action No action
1 (inc) 0 (-) 1 (inv) Inc ctr Dec ctr
1 (inc) 1 (inv) 0 (-) Dec ctr Inc ctr
2 (dec) 0 (-) 1 (inv) Dec ctr Inc ctr
1 (inc) 0 (-) 2 (dis) Inc ctr No action
1 (inc) 2 (dis) 0 (-) No action Inc ctr
This table is also valid for negative edges (sig h→l) on substituting NEG_MODE for POS_MODE.
Each pulse counter unit also features a filter on each of the four inputs, adding the option to ignore short glitches
in the signals. If a PCNT_FILTER_EN_Un can be set to filter the four input signals of the unit. If this filter is
enabled, any pulses shorter than REG_FILTER_THRES_Un number of APB_CLK clock cycles will be filtered out
and will have no effect on the counter. With the filter disabled, in theory infinitely small glitches could possibly
trigger pulse counter action. However, in practice the signal inputs are sampled on APB_CLK edges and even
with the filter disabled, pulse widths lasting shorter than one APB_CLK cycle may be missed.
Apart from the input channels, software also has some control over the counter. In particular, the counter value
can be frozen to the current value by configuring PCNT_CNT_PAUSE_Un. It can also be reset to 0 by configuring
PCNT_PLUS_CNT_RST_Un.
17.2.3 Watchpoints
The pulse counters have five watchpoints that share one interrupt. Interrupt generation can be enabled or
disabled for each individual watchpoint. The watchpoints are:
• Maximum count value: Triggered when PULSE_CNT >= PCNT_CNT_H_LIM_Un. Additionally, this will reset
the counter to 0. PCNT_CNT_H_LIM_Un should be a positive number.
• Minimum count value: Triggered when PULSE_CNT <= PCNT_CNT_L_LIM_Un. Additionally, this will reset
the counter to 0. PCNT_CNT_L_LIM_Un should be a negative number.
17.2.4 Examples
Figure 122 shows channel 0 being used as an up-counter. The configuration of channel 0 is shown below.
Figure 123 shows channel 0 decrementing the counter. The configuration of channel 0 differs from that in Figure
122 in the following two aspects:
• PCNT_CNT_H_LIM_Un = –5: PULSE_CNT resets to 0 when the count value decreases to –5.
17.2.5 Interrupts
PCNT_CNT_THR_EVENT_Un_INT: This interrupt gets triggered when one of the five channel comparators
detects a match.
17.4 Registers
n
n
n
_U
_U
_U
_U
NT TH H_ _E N_ n
_F R_Z LIM N_ Un
n
PC T_ R_ RE 1_E n
n
Un
PC T_ R_ LIM 0_E _U
_U
U
_U
DE
DE
DE
DE
_E _E Un
ILT E _E Un
Un Un
Un
PC _ R_ RE DE_
E_
N
DE
DE
O
O
O
ER RO N_
N_ N_
D
S_
_M
M
M
M
O
O
O
O
_
RE
L_
_
_M
PC T_ R_ _M
M
M
RL
RL
N TH TH S
S
RL
S_
S_
TR
TH
EG
G
CT
CT
CT
O
NE
LC
NT TH TH
R_
N H _
_H
_N
_H
_P
_P
_L
L
1_
E
H1
H1
H1
H0
H0
H0
LT
CH
PC CH
N H
FI
_C
_C
_C
_C
_C
_C
T
_
PC _
_
NT
NT
NT
NT
NT
NT
NT
NT
NT
NT
PC
PC
PC
PC
PC
PC
PC
PC
PC
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0
0 0 0 0 0 0 0 0 0 0 1 1 1 1 0x010 Reset
PCNT_CH1_POS_MODE_Un This register sets the behaviour when the signal input of channel 1
detects a positive edge. (R/W) 1: Increment the counter; 2: Decrement the counter; 0, 3: No
effect on counter
PCNT_CH1_NEG_MODE_Un This register sets the behaviour when the signal input of channel 1
detects a negative edge. (R/W) 1: Increment the counter; 2: Decrement the counter; 0, 3: No
effect on counter
PCNT_CH0_POS_MODE_Un This register sets the behaviour when the signal input of channel 0
detects a positive edge. (R/W) 1: Increase the counter; 2: Decrease the counter; 0, 3: No effect
on counter
PCNT_CH0_NEG_MODE_Un This register sets the behaviour when the signal input of channel 0
detects a negative edge. (R/W) 1: Increase the counter; 2: Decrease the counter; 0, 3: No effect
on counter
PCNT_THR_THRES1_EN_Un This is the enable bit for unit n’s thres1 comparator. (R/W)
PCNT_THR_THRES0_EN_Un This is the enable bit for unit n’s thres0 comparator. (R/W)
PCNT_THR_L_LIM_EN_Un This is the enable bit for unit n’s thr_l_lim comparator. (R/W)
PCNT_THR_H_LIM_EN_Un This is the enable bit for unit n’s thr_h_lim comparator. (R/W)
PCNT_THR_ZERO_EN_Un This is the enable bit for unit n’s zero comparator. (R/W)
PCNT_FILTER_EN_Un This is the enable bit for unit n’s input filter. (R/W)
PCNT_FILTER_THRES_Un This sets the maximum threshold, in APB_CLK cycles, for the filter. Any
pulses lasting shorter than this will be ignored when the filter is enabled. (R/W)
Un
1_
0_
ES
ES
HR
HR
_T
_T
NT
NT
_C
_C
NT
NT
PC
PC
31 16 15 0
PCNT_CNT_THRES1_Un This register is used to configure the thres1 value for unit n. (R/W)
PCNT_CNT_THRES0_Un This register is used to configure the thres0 value for unit n. (R/W)
_U
_U
IM
IM
_L
_L
_H
_L
NT
NT
_C
_C
NT
NT
PC
PC
31 16 15 0
PCNT_CNT_L_LIM_Un This register is used to configure the thr_l_lim value for unit n. (R/W)
PCNT_CNT_H_LIM_Un This register is used to configure the thr_h_lim value for unit n. (R/W)
31
31
31
0
0
0
17. PULSE_CNT
Espressif Systems
0
0
0
0
(re
0
se
rv
ed
0
)
0
0
(re (re
0
se se
rv rv
0x0000000
0x0000000
e ed
0
d) )
0
PCNT_CNT_THR_EVENT_Un_INT_ST The
0
16
PCNT_CNT_THR_EVENT_Un_INT_RAW The
15
493
PCNT_CNT_THR_EVENT_Un_INT interrupt. (RO)
PCNT_CNT_THR_EVENT_Un_INT interrupt. (RO)
raw
masked
interrupt
8
8
PC
7
7
0
0
PC PC
Register 17.5: PCNT_INT_RAW_REG (0x0080)
NT
0x00000
N N _
6
6
0
0
PC T_ PC T_ PL
N CN status N CN US
5
5
status
0
0
PC T_ T_ PC T_ T_ _C
Register 17.4: PCNT_Un_CNT_REG (n: 0-7) (0x28+0x0C*n)
N CN TH N CN TH NT
4
4
0
0
PC T_ T_ R_ PC T_ T_ R_ _U
N CN TH E N CN TH E n
3
3
bit
0
0
bit
PC T_ T_ R_ VEN PC T_ T_ R_ VEN
N CN TH E T N CN TH E T
PCNT_PLUS_CNT_Un This register stores the current pulse count value for unit n. (RO)
2
2
0
0
PC T_ T_ R_ VEN _U PC T_ T_ R_ VEN _U
N CN TH E T 7_ N CN TH E T 7_
1
1
0
0
for
N CN TH E T 6_ _S N CN TH E T 6_ _R
0
0
0
the
the
NT H EV T_ _IN ST NT H EV T_ _IN RA
0 Reset
0 Reset
Reset
_T R_E EN U3 T_ _T R_E EN U3 T_ W
HR V T_ _IN ST HR V T_ _IN RA
_E ENT U2_ T_ _E ENT U2_ T_ W
Espressif Systems
interrupt. (WO)
(re
se
0x0000
rv
ed
)
(re (re
se s
r er
0x0000000
0x0000000
ve ve
d) d)
17
PCNT_CNT_THR_EVENT_Un_INT_ENA The
0
16
(re
se
0
15
PC rve
N d
494
1
14
PC T_ )
PCNT_CNT_THR_EVENT_Un_INT interrupt. (R/W)
N CN
0
13
PC T_ T_
N PL PA
1
12
PC T_ US US
N CN _C E
interrupt
0
11
PC T_ T_ NT _U7
N PL PA _
1
10
0
PC T_ T_ NT _U6 U7
1
8
8
PC T_ US US RST
7
7
7
0
0
0
enable
PC T_ T_ NT _U5 U6 PC PC
N PL PA _ N N
6
6
6
1
0
0
PC T_ US US RST PC T_ PC T_
N CN _C E _ N CN N CN
5
5
5
0
0
0
PC T_ T_ NT _U4 U5 PC T_ T_ PC T_ T_
N PL PA _ N CN TH N CN TH
bit
4
4
4
1
0
0
PC T_ US US RST PC T_ T_ R_ PC T_ T_ R_
N CN _C E _ N CN TH E N CN TH E
3
3
3
0
0
0
2
2
2
1
0
0
1
1
1
0
0
0
0
0
0
NT H EV T_ _IN CL NT H EV T_ _IN EN
1 Reset
0 Reset
0 Reset
S_ US ST _T R_E EN U3 T_ R _T R_E EN U3 T_ A
CN E_ _U HR V T_ _IN CL HR V T_ _IN EN
T_ U0 1 _E ENT U2_ T_ R _E ENT U2_ T_ A
18.1 Introduction
There are four general-purpose timers embedded in the ESP32. They are all 64-bit generic timers based on
16-bit prescalers and 64-bit auto-reload-capable up/downcounters.
The ESP32 contains two timer modules, each containing two timers. The two timers in a block are indicated by
an x in TIMGn_Tx; the blocks themselves are indicated by an n.
• Auto-reload at alarm
Counting can be enabled and disabled by setting and clearing TIMGn_Tx_EN. Clearing this bit essentially freezes
the counter, causing it to neither count up nor count down; instead, it retains its value until TIMGn_Tx_EN is set
again. Reloading the counter when TIMGn_Tx_EN is cleared will change its value, but counting will not be
resumed until TIMGn_Tx_EN is set.
Software can set a new counter value by setting registers TIMGn_Tx_LOAD_LO and TIMGn_Tx_LOAD_HI to the
intended new value. The hardware will ignore these register settings until a reload; a reload will cause the
contents of these registers to be copied to the counter itself. A reload event can be triggered by an alarm
(auto-reload at alarm) or by software (software instant reload). To enable auto-reload at alarm, the register
TIMGn_Tx_AUTORELOAD should be set. If auto-reload at alarm is not enabled, the time-base counter will
continue incrementing or decrementing after the alarm. To trigger a software instant reload, any value can be
written to the register TIMGn_Tx_LOAD_REG; this will cause the counter value to change instantly. Software can
also change the direction of the time-base counter instantly by changing the value of
TIMGn_Tx_INCREASE.
The time-base counter can also be read by software, but because the counter is 64-bit, the CPU can only get the
value as two 32-bit values, the counter value needs to be latched onto TIMGn_TxLO_REG and TIMGn_TxHI_REG
first. This is done by writing any value to TIMGn_TxUPDATE_REG; this will instantly latch the 64-bit timer value
onto the two registers. Software can then read them at any point in time. This approach stops the timer value
being read erroneously when a carry-over happens between reading the low and high word of the timer
value.
18.2.4 MWDT
Each timer module also contains a Main System Watchdog Timer and its associated registers. While these
registers are described here, their functional description can be found in the chapter entitled Watchdog
Timer.
18.2.5 Interrupts
• TIMGn_Tx_INT_WDT_INT: Generated when a watchdog timer interrupt stage times out.
18.4 Registers
_E E N
AD
LA _IN EN
_
LO
_A EL T_
N
RM T
O E
UT AS
Tx EV IN
RE
n_ L _
DE
_A RE
G x_ GE
VI
Tx C
M T N
M T D
n_ IN
DI
TI Gn_ x_E
TI Gn_ x_E
G x_
_
Tx
M T
M T
TI Gn_
n_
TI Gn_
G
M
M
TI
TI
TI
31 30 29 28 13 12 11 10
0 1 1 0x00001 0 0 0 Reset
TIMGn_Tx_INCREASE When set, the timer x time-base counter will increment every clock tick. When
cleared, the timer x time-base counter will decrement. (R/W)
TIMGn_Tx_EDGE_INT_EN When set, an alarm will generate an edge type interrupt. (R/W)
TIMGn_Tx_LEVEL_INT_EN When set, an alarm will generate a level type interrupt. (R/W)
TIMGn_Tx_ALARM_EN When set, the alarm is enabled. This bit is automatically cleared once an
alarm occurs. (R/W)
31 0
0x000000000 Reset
TIMGn_TxLO_REG After writing to TIMGn_TxUPDATE_REG, the low 32 bits of the time-base counter
of timer x can be read here. (RO)
31 0
0x000000000 Reset
TIMGn_TxHI_REG After writing to TIMGn_TxUPDATE_REG, the high 32 bits of the time-base counter
of timer x can be read here. (RO)
31 0
0x000000000 Reset
TIMGn_TxUPDATE_REG Write any value to trigger a timer x time-base counter value update (timer x
current value will be stored in registers above). (WO)
31 0
0x000000000 Reset
TIMGn_TxALARMLO_REG Timer x alarm trigger time-base counter value, low 32 bits. (R/W)
31 0
0x000000000 Reset
TIMGn_TxALARMHI_REG Timer x alarm trigger time-base counter value, high 32 bits. (R/W)
31 0
0x000000000 Reset
TIMGn_TxLOADLO_REG Low 32 bits of the value that a reload will load onto timer x time-base
counter. (R/W)
31 0
0x000000000 Reset
TIMGn_TxLOADHI_REG High 32 bits of the value that a reload will load onto timer x time-base
counter. (R/W)
31 0
0x000000000 Reset
TIMGn_TxLOAD_REG Write any value to trigger a timer x time-base counter reload. (WO)
EN
TH
TH
D_
G
G
EN
O
EN
M
N
_L
_L
_I EN
T_
_E
ET
ET
O
EL T_
NT
BO
ES
ES
EV _IN
_R
_R
SH
_L GE
0
_W T_ 3
U
TG
TG
TG
YS
LA
CP
N
DT D
ST
_S
_S
_S
_S
Tx T_E
_F
T_
_
DT
DT
DT
DT
DT
DT
G _WD
Tx D
_W
_W
_W
_W
n_ W
_W
_W
G x_
_
Tx
Tx
Tx
Tx
Tx
Tx
Tx
M T
n_
n_
n_
n_
n_
TI Gn_
n_
n_
n_
G
G
M
M
TI
TI
TI
TI
TI
TI
TI
TI
TI
31 30 29 28 27 26 25 24 23 22 21 20 18 17 15 14
TIMGn_Tx_WDT_EDGE_INT_EN When set, an edge type interrupt will occur at the timeout of a stage
configured to generate an interrupt. (R/W)
TIMGn_Tx_WDT_LEVEL_INT_EN When set, a level type interrupt will occur at the timeout of a stage
configured to generate an interrupt. (R/W)
TIMGn_Tx_WDT_CPU_RESET_LENGTH CPU reset signal length selection. 0: 100 ns, 1: 200 ns,
2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W)
TIMGn_Tx_WDT_SYS_RESET_LENGTH System reset signal length selection. 0: 100 ns, 1: 200 ns,
2: 300 ns, 3: 400 ns, 4: 500 ns, 5: 800 ns, 6: 1.6 µs, 7: 3.2 µs. (R/W)
E
L
SCA
RE
_P
LK
_C
DT
W_
Tx
n_
G
M
TI
31 16
0x00001 Reset
31 0
26000000 Reset
31 0
0x007FFFFFF Reset
31 0
0x0000FFFFF Reset
31 0
0x0000FFFFF Reset
31 0
0x000000000 Reset
31 0
0x050D83AA1 Reset
TIMGn_Tx_WDTWPROTECT_REG If the register contains a different value than its reset value, write
protection is enabled. (R/W)
IN EN A
0_ T_ N
T_ A
A
_T IN T_E
EN
NT 1_ N
_I T _I
Tx T_ DT
G x_ _W
M T T
TI Gn_ x_IN
n_ IN
d)
M T
ve
TI Gn_
r
se
M
(re
TI
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMGn_Tx_INT_T1_INT_ENA The interrupt enable bit for the TIMGn_Tx_INT_T1_INT interrupt. (R/W)
(R/W)
TIMGn_Tx_INT_T0_INT_ENA The interrupt enable bit for the TIMGn_Tx_INT_T0_INT interrupt. (R/W)
(R/W)
IN RA W
0_ T_ A
T_ W
W
_T IN T_R
RA
NT 1_ N
_ I T _I
T x T_ DT
G x_ _W
M T T
TI Gn_ x_IN
n_ IN
d)
M T
ve
TI Gn_
er
M
s
(re
TI
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMGn_Tx_INT_WDT_INT_RAW The raw interrupt status bit for the TIMGn_Tx_INT_WDT_INT inter-
rupt. (RO)
TIMGn_Tx_INT_T1_INT_RAW The raw interrupt status bit for the TIMGn_Tx_INT_T1_INT interrupt.
(RO)
TIMGn_Tx_INT_T0_INT_RAW The raw interrupt status bit for the TIMGn_Tx_INT_T0_INT interrupt.
(RO)
0_ T_ T
_T IN T_S
IN ST
ST
T_
NT 1_ N
_I T _I
Tx T_ DT
G x_ _W
M T T
TI Gn_ x_IN
n_ IN
d )
M T
ve
TI Gn_
er
M
s
(re
31 3
TI
2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TIMGn_Tx_INT_WDT_INT_ST The masked interrupt status bit for the TIMGn_Tx_INT_WDT_INT in-
terrupt. (RO)
TIMGn_Tx_INT_T1_INT_ST The masked interrupt status bit for the TIMGn_Tx_INT_T1_INT interrupt.
(RO)
TIMGn_Tx_INT_T0_INT_ST The masked interrupt status bit for the TIMGn_Tx_INT_T0_INT interrupt.
(RO)
IN CL R
0_ T_ L
T_ R
R
_T IN T_C
CL
NT 1_ N
_ I T _I
Tx T_ DT
G x_ _W
M T T
TI Gn_ x_IN
n_ IN
d)
M T
ve
TI Gn_
er
M
s
(re
TI
31 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
19.1 Introduction
The ESP32 has three watchdog timers: one in each of the two timer modules (called Main System Watchdog
Timer, or MWDT) and one in the RTC module (which is called the RTC Watchdog Timer, or RWDT). These
watchdog timers are intended to recover from an unforeseen fault, causing the application program to abandon
its normal sequence. A watchdog timer has four stages. Each stage may take one out of three or four actions
upon the expiry of a programmed period of time for this stage, unless the watchdog is fed or disabled. The
actions are: interrupt, CPU reset, core reset and system reset. Only the RWDT can trigger the system reset, and
is able to reset the entire chip and the main system including the RTC itself. A timeout value can be set for each
stage individually.
During flash boot, the RWDT and the first MWDT start automatically in order to detect and recover from booting
problems.
19.2 Features
• Four stages, each of which can be configured or disabled separately
• One out of three or four possible actions (interrupt, CPU reset, core reset and system reset) upon the expiry
of each stage
• Write protection, to prevent the RWDT and MWDT configuration from being inadvertently altered.
When a watchdog timer is enabled, it will proceed in loops from stage 0 to stage 3, then back to stage 0 and
start again. The expiry action and time period for each stage can be configured individually.
Every stage can be configured for one of the following actions when the expiry timer reaches the stage’s timeout
value:
• Trigger an interrupt
When the stage expires an interrupt is triggered.
• Disabled
This stage will have no effects on the system.
When software feeds the watchdog timer, it returns to stage 0 and its expiry counter restarts from 0.
Both the MWDTs, as well as the RWDT, can be protected from accidental writing. To accomplish this, they have
a write-key register (TIMERS_WDT_WKEY for the MWDT, RTC_CNTL_WDT_WKEY for the RWDT.) On reset,
these registers are initialized to the value 0x50D83AA1. When the value in this register is changed from
0x50D83AA1, write protection is enabled. Writes to any WDT register, including the feeding register (but
excluding the write-key register itself), are ignored. The recommended procedure for accessing a WDT is:
During flash booting, the MWDT in timer group 0 (TIMG0), as well as the RWDT, are automatically enabled. Stage
0 for the enabled MWDT is automatically configured to reset the system upon expiry; stage 0 for the RWDT resets
the RTC when it expires. After booting, the register TIMERS_WDT_FLASHBOOT_MOD_EN should be cleared to
stop the flash boot protection procedure for the MWDT, and RTC_CNTL_WDT_FLASHBOOT_MOD_EN should
be cleared to do the same for the RWDT. After this, the MWDT and RWDT can be configured by software.
19.3.1.4 Registers
The MWDT registers are part of the timer submodule and are described in the Timer Registers section. The
RWDT registers are part of the RTC submodule and are described in the RTC Registers section.
20.1 Introduction
The ESP32 has a number of eFuses which store system parameters. Fundamentally, an eFuse is a single bit of
non-volatile memory with the restriction that once an eFuse bit is programmed to 1, it can never be reverted to 0.
Software can instruct the eFuse Controller to program each bit for each system parameter as needed.
Some of these system parameters can be read by software using the eFuse Controller. Some of the system
parameters are also directly used by hardware modules.
20.2 Features
• Configuration of 34 system parameters
• Optional write-protection
• Optional software-read-protection
Program Software-Read
Name Bit width -Protection by -Protection by Description
efuse_wr_disable efuse_rd_disable
efuse_wr_disable 16 1 - controls the eFuse Controller
efuse_rd_disable 4 0 - controls the eFuse Controller
governs the flash encryption/
flash_crypt_cnt 7 2 -
decryption
WIFI_MAC_Address 56 3 - Wi-Fi MAC address and CRC
configures the SPI I/O to a cer-
SPI_pad_config_hd 5 3 -
tain pad
XPD_SDIO_REG 1 5 - powers up the flash regulator
configures the flash regulator
SDIO_TIEH 1 5 - voltage: set to 1 for 3.3 V
and set to 0 for 1.8 V
determines whether
XPD_SDIO_REG
sdio_force 1 5 -
and SDIO_TIEH can
control the flash regulator
Program Software-Read
Name Bit width -Protection by -Protection by Description
efuse_wr_disable efuse_rd_disable
BLK3_part_reserve 2 10 3 controls the eFuse controller
configures the SPI I/O to a cer-
SPI_pad_config_clk 5 6 -
tain pad
configures the SPI I/O to a cer-
SPI_pad_config_q 5 6 -
tain pad
configures the SPI I/O to a cer-
SPI_pad_config_d 5 6 -
tain pad
configures the SPI I/O to a cer-
SPI_pad_config_cs0 5 6 -
tain pad
governs flash encryption/
flash_crypt_config 4 10 3
decryption
coding_scheme* 2 10 3 controls the eFuse Controller
disables the ROM BASIC
console_debug_disable 1 15 - debug console fallback
mode when set to 1
determines the status of
abstract_done_0 1 12 -
Secure Boot
determines the status of
abstract_done_1 1 13 -
Secure Boot
disables access to the
JTAG controllers so as to
JTAG_disable 1 14 -
effectively disable external
use of JTAG
governs flash encryption/
download_dis_encrypt 1 15 -
decryption
governs flash encryption/
download_dis_decrypt 1 15 -
decryption
disables cache when boot
download_dis_cache 1 15 -
mode is the Download Mode
determines whether BLOCK3
key_status 1 10 3
is deployed for user purposes
governs flash encryption/
BLOCK1* 256/192/128 7 0
decryption
BLOCK2* 256/192/128 8 1 key for Secure Boot
BLOCK3* 256/192/128 9 2 key for user purposes
disable_app_cpu 1 3 - disables APP CPU
disable_bt 1 3 - disables Bluetooth
32pad 1 3 - 32 pad packaging
disable_cache 1 3 - disables cache
chip_version 3 3 - chip version
CK8M Frequency 8 4 - RTC8M_CLK frequency
Program Software-Read
Name Bit width -Protection by -Protection by Description
efuse_wr_disable efuse_rd_disable
stores the voltage level for
vol_level_hp_inv 2 3 - CPU to run at 240 MHz, or for
flash/PSRAM to run at 80 MHz
stores the difference between
dig_vol_l6 4 11 - the digital regulator voltage at
level 6 and 1.2 V.
The system parameter efuse_wr_disable determines whether all of the system parameters are write-protected.
Since efuse_wr_disable is a system parameter as well, it also determines whether itself is write-protected.
If a system parameter is not write-protected, its unprogrammed bits can be programmed from 0 to 1. The bits
previously programmed to 1 will remain 1. When a system parameter is write-protected, none of its bits can be
programmed: The unprogrammed bits will always remain 0 and the programmed bits will always remain 1.
The write-protection status of each system parameter corresponds to a bit in efuse_wr_disable. When the
corresponding bit is set to 0, the system parameter is not write-protected. When the corresponding bit is set to
1, the system parameter is write-protected. If a system parameter is already write-protected, it will remain
write-protected. The column entitled “Program-Protection by efuse_wr_disable” in Table 79 lists the
corresponding bits that determine the write-protection status of each system parameter.
Of the 34 system parameters, 28 are not constrained by software-read-protection. These are marked by “-” in
the column entitled “Software-Read-Protection by efuse_rd_disable” in Table 79. Those system parameters,
some of which are used by software and hardware modules at the same time, can be read by software via the
eFuse Controller at any time.
When not software-read-protected, the other six system parameters can both be read by software and used by
hardware modules. When they are software-read-protected, they can only be used by the hardware
modules.
As Table 79 shows, only three system parameters, BLOCK1, BLOCK2, and BLOCK3, have variable bit widths.
Their bit widths are controlled by another system parameter, coding_scheme. Despite their variable bit widths,
BLOCK1, BLOCK2, and BLOCK3 are assigned a fixed number of bits in eFuse. There is an encoding mapping
between these three system parameters and their corresponding stored values in eFuse. For details please see
Table 80.
• BLOCKN represents any of the following three system parameters: BLOCK1, BLOCK2 or BLOCK3.
• BLOCKN [255 : 0], BLOCKN [191 : 0], and BLOCKN [127 : 0] represent each bit of the three system
parameters in the three encoding schemes.
e
• BLOCKN [255 : 0] represents each corresponding bit of those system parameters in eFuse after being
encoded.
None
e
BLOCKN [255 : 0] = BLOCKN [255 : 0]
3/4
Repeat
e e
BLOCKN [255 : 128] = BLOCKN [127 : 0] = BLOCKN [127 : 0]
20.3.1.4 BLK3_part_reserve
System parameters coding_scheme, BLOCK1, BLOCK2, and BLOCK3 are controlled by the parameter
BLK3_part_reserve.
When the value of BLK3_part_reserve is 0, coding_scheme, BLOCK1, BLOCK2, and BLOCK3 can be set to any
value.
Each bit of the 31 fixed-length system parameters and the three encoded variable-length system parameters
corresponds to a program register bit, as shown in Table 81. The register bits will be used when programming
system parameters.
EFUSE_BLK0_WDATA6_REG
Espressif Systems 512 ESP32 Technical Reference Manual V4.1
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20. eFuse Controller
2. Set the corresponding register bit of the system parameter bit to be programmed to 1.
The configuration values of the EFUSE_CLK_SEL0 bit, EFUSE_CLK_SEL1 bit of register EFUSE_CLK, and the
EFUSE_DAC_CLK_DIV bit of register EFUSE_DAC_CONF are based on the current APB_CLK frequency, as is
shown in Table 82.
The two methods to identify the generation of program/read-done interrupts are as follows:
Method One:
1. Poll bit 1/0 in register EFUSE_INT_RAW until bit 1/0 is 1, which represents the generation of an
program/read-done interrupt.
2. Set the bit 1/0 in register EFUSE_INT_CLR to 1 to clear the program/read-done interrupts.
Method Two:
1. Set bit 1/0 in register EFUSE_INT_ENA to 1 to enable eFuse Controller to post a program/read-done
interrupt.
4. Read bit 1/0 in register EFUSE_INT_ST to identify the generation of the program/read-done interrupt.
The programming of different system parameters and even the programming of different bits of the same system
parameter can be completed separately in multiple programmings. It is, however, recommended that users
minimize programming cycles, and program all the bits that need to be programmed in a system parameter in
one programming action. In addition, after all system parameters controlled by a certain bit of efuse_wr_disable
are programmed, that bit should be immediately programmed. The programming of system parameters
controlled by a certain bit of efuse_wr_disable, and the programming of that bit can even be completed at the
same time. Repeated programming of programmed bits is strictly forbidden.
The bit width of system parameters BLOCK1, BLOCK2, and BLOCK3 is variable. Although 256 register bits have
been assigned to each of the three parameters, as shown in Table 83, some of the 256 register bits are useless in
the 3/4 coding and the Repeat coding scheme. In the None coding scheme, the corresponding register bit of
each bit of BLOCKN [255 : 0] is used. In the 3/4 coding scheme, only the corresponding register bits of
BLOCKN [191 : 0] are useful. In Repeat coding scheme, only the corresponding bits of BLOCKN [127 : 0] are
useful. In different coding schemes, the values of useless register bits read by software are invalid. The values of
useful register bits read by software are the system parameters BLOCK1, BLOCK2, and BLOCK3
themselves instead of their values after being encoded.
20.3.5 Interrupts
• EFUSE_PGM_DONE_INT: Triggered when eFuse programming has finished.
20.5 Registers
T
CN
T_
S
S
DI
DI
YP
R_
D_
CR
_W
_R
H_
SE
SE
S
FU
FU
LA
E
F
D_
D_
D_
)
_R
_R
_R
ed
E
rv
US
US
US
se
EF
EF
EF
(re
31 27 26 20 19 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_BLK0_RDATA1_REG This field returns the value of the lower 32 bits of WIFI_MAC_Address.
(RO)
_R
ed
SE
rv
se
U
EF
(re
31 24 23 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
U
CP
VE D D E
D
P_ R_ PA CH
P_
_H
HI VE 32 CA
AP
DI BT
IG
_C IP_ R_ IS_
R_ IS_
S_
G
NF
K
CO
RD H VE D
_P
E_ _C IP_ R_
ER
D_
E
_V
US _R CH _V
PA
P
EF SE D_ IP
I_
HI
U R H
SP
_C
C
D_
EF E D_
RD
D
)
_R
US _R
ed
E_
_
E
EF E
rv
US
US
US
se
EF
EF
EF
(re
31 12 11 9 8 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Q
PD TIE E
RE
_X IO_ RC
_S H
O
_F
RD D FO
DI
8M
E_ D_S IO_
CK
US _R SD
D_
EF SE D_
_R
)
)
U _R
ed
ed
SE
EF SE
rv
rv
FU
se
se
U
ES
EF
(re
(re
31 17 16 15 14 13 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IG
S0
LK
NF
_Q
_C
_C
_D
NV
CO
IG
IG
IG
IG
_I
T_
HP
NF
NF
NF
NF
P
O
L_
L6
RY
_C
_C
_C
_C
VE
L_
_C
AD
AD
AD
LE
O
PA
SH
_V
_P
_P
_P
L_
I_
LA
PI
PI
PI
O
P
DI
_S
_S
S
_V
_F
D_
D_
D_
RD
RD
RD
RD
d)
_R
_R
_R
E_
E_
E_
E_
ve
E
E
US
US
US
US
US
US
US
er
s
EF
EF
EF
EF
EF
EF
EF
(re
31 28 27 24 23 22 21 20 19 15 14 10 9 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_RD_DIG_VOL_L6 This field stores the difference between the digital regulator voltage at level
6 and 1.2 V. (RO)
EFUSE_RD_VOL_LEVEL_HP_INV This field stores the voltage level for CPU to run at 240 MHz, or
for flash/PSRAM to run at 80 MHz. 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)
LE
AB
PT
US d) AB DO TA C PT
EM IS
CH G_D
(re SE D_ SAB E_D _D HE
S_ N G RY
EF rve D_ S_ E_J _EN RY
E
U _R DI L L AC
se _R AB L L EC
U
NG DEB
EF SE D_ SAB E_D _C
NE 1
_0
U _R DI L US
U _R DI L L
DO E_
EF SE D_ SAB E_D
E_
_S
EF SE D_ SAB AT
_C OL
U _R DI ST
RD NS
EF SE D_ Y_
DI
E_ CO
O
U _R KE
EF E D_
US D_
d)
US _R
EF _R
ve
EF SE
E
er
U
s
EF
(re
31 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
S
H_
IS
DI
_D
AS
R_
RD
FL
_W
)
ed
E_
E_
SE
rv
US
US
se
U
EF
EF
EF
(re
31 27 26 20 19 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
H
IG
_H
RC
_C
AC
M
I_
IF
W
)
ed
E_
rv
US
se
EF
(re
31 24 23 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
U
P
E
_C
D
_V _D AD H
_H
IP ER 2P AC
PP
T
IG
CH _V _3 _C
_D _B
_A
G
NF
E_ HIP ER IS
ER IS
IS
PK
CO
US _C _V _D
R_
EF E HIP ER
D_
VE
US _C _V
PA
P_
EF SE HIP
I_
HI
SP
_C
U C
)
ed
E_
_
SE
EF E
rv
US
US
se
U
EF
EF
EF
(re
31 12 11 9 8 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
Q
D_ IEH E
RE
XP _T C
E_ DIO OR
IO
_F
SD
M
US _S _F
K8
EF SE DIO
_C
d)
)
U _S
ed
SE
ve
EF SE
rv
FU
er
se
U
s
ES
EF
(re
(re
31 17 16 15 14 13 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
S0
LK
NF
_Q
_C
_C
_D
V
O
IG
IG
IG
IG
C
_I
T_
HP
NF
NF
NF
NF
YP
O
L_
L6
_C
_C
_C
_C
CR
VE
L_
D
H_
LE
O
PA
PA
PA
PA
_V
L_
AS
I_
I_
I_
I_
G
VO
SP
SP
SP
SP
FL
DI
)
ed
E_
E_
E_
E_
E_
E_
E_
rv
US
US
US
US
US
US
US
se
EF
EF
EF
EF
EF
EF
EF
(re
31 28 27 24 23 22 21 20 19 15 14 10 9 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_DIG_VOL_L6 This field stores the difference between the digital regulator voltage at level 6
and 1.2 V. (R/W)
EFUSE_VOL_LEVEL_HP_INV These bits store the voltage level for CPU to run at 240 MHz, or for
flash/PSRAM to run at 80 MHz. 0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (R/W)
L E
AB
T
EF rve BS ON AG CR T
EM IS
YP
se _A _D JT N YP
CH G_D
U _A B D E E
EF SE ISA LE_ L_D CH
(re SE BS LE_ L_E CR
E
U
U _D B D A
NG DEB
EF SE ISA LE_ L_C
O 1
0
EF SE ISA LE_ S
US d) _D E_
E_
U _D B U
U _D B D
_
_S
CO OLE
EF SE ISA TAT
N
U _D _S
S
DI
US ON
EF E EY
C
d)
US _K
E_
E_
ve
EF SE
er
U
s
EF
EF
(re
31 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
31 0
0x000000000 Reset
L0
SE
SE
K_
K_
CL
CL
d)
E_
E_
ve
US
US
r
se
EF
EF
(re
31 16 15 8 7 0
DE
CO
P_
O
)
ed
E_
rv
US
se
EF
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 Reset
D
AD MD
M
_C
RE _C
E_ GM
d)
US _P
ve
EF SE
r
se
U
EF
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_PGM_CMD Set this to 1 to start a program operation. Reverts to 0 when the program op-
eration is done. (R/W)
EFUSE_READ_CMD Set this to 1 to start a read operation. Reverts to 0 when the read operation is
done. (R/W)
AW
NT W
_I RA
_R
NE T_
O IN
_D E_
AD ON
RE _D
E_ GM
d)
US _P
e
EF SE
rv
se
U
EF
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_PGM_DONE_INT_RAW The raw interrupt status bit for the EFUSE_PGM_DONE_INT inter-
rupt. (RO)
EFUSE_READ_DONE_INT_RAW The raw interrupt status bit for the EFUSE_READ_DONE_INT in-
terrupt. (RO)
T
_I ST
_S
NE T_
NT
O IN
_D E _
AD ON
RE _D
E_ GM
d)
US _P
ve
EF SE
r
se
U
EF
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_PGM_DONE_INT_ST The masked interrupt status bit for the EFUSE_PGM_DONE_INT in-
terrupt. (RO)
EFUSE_READ_DONE_INT_ST The masked interrupt status bit for the EFUSE_READ_DONE_INT in-
terrupt. (RO)
NA
NT A
_I EN
_E
NE T_
O IN
_D E_
AD ON
RE _D
E_ GM
d)
US _P
e
EF SE
rv
se
U
EF
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
US _P
e
EF SE
rv
se
U
EF
(re
31 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
IV
_D
LK
_C
AC
d)
_D
ve
E
US
ser
EF
(re
31 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40 Reset
S
NG
NI
AR
W
C_
DE
)
ed
E_
rv
US
se
EF
(re
31 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EFUSE_DEC_WARNINGS If a bit is set in this register, it means some errors were corrected while
decoding the 3/4 encoding scheme. (RO)
21.1 Introduction
The AES Accelerator speeds up AES operations significantly, compared to AES algorithms implemented solely in
software. The AES Accelerator supports six algorithms of FIPS PUB 197, specifically AES-128, AES-192 and
AES-256 encryption and decryption.
21.2 Features
• Supports AES-128 encryption and decryption
• Supports four variations of key endianness and four variations of text endianness
AES_MODE_REG[2:0] Operation
0 AES-128 Encryption
1 AES-192 Encryption
2 AES-256 Encryption
4 AES-128 Decryption
5 AES-192 Decryption
6 AES-256 Decryption
Plaintext and ciphertext is stored in the AES_TEXT_m_REG registers. There are four 32-bit registers. To enable
AES-128/192/256 encryption, initialize the AES_TEXT_m_REG registers with plaintext before encryption. When
encryption is finished, the AES Accelerator will store back the resulting ciphertext in the AES_TEXT_m_REG
registers. To enable AES-128/192/256 decryption, initialize the AES_TEXT_m_REG registers with ciphertext
before decryption. When decryption is finished, the AES Accelerator will store back the resulting plaintext in the
AES_TEXT_m_REG registers.
21.3.3 Endianness
Key Endianness
Bit 0 and bit 1 in AES_ENDIAN_REG define the key endianness. For detailed information, please see Table 87,
Table 88 and Table 89. w[0] ~ w[3] in Table 87, w[0] ~ w[5] in Table 88 and w[0] ~ w[7] in Table 89 are “the first Nk
words of the expanded key” as specified in “5.2: Key Expansion” of FIPS PUB 197. “Column Bit” specifies the
bytes in the word from w[0] to w[7]. The bytes of AES_KEY_n_REG comprise “the first Nk words of the expanded
key”.
Text Endianness
Bit 2 and bit 3 in AES_ENDIAN_REG define the endianness of input text, while Bit 4 and Bit 5 define the
endianness of output text. The input text refers to the plaintext in AES-128/192/256 encryption and the
ciphertext in decryption. The output text refers to the ciphertext in AES-128/192/256 encryption and the plaintext
in decryption. For details, please see Table 86. “State” in Table 86 is defined as that in “3.4: The State” of FIPS
PUB 197: “The AES algorithm operations are performed on a two-dimensional array of bytes called the State”.
The ciphertext or plaintexts stored in each byte of AES_TEXT_m_REG comprise the State.
Table 86: AES Text Endianness
AES_ENDIAN_REG[1] AES_ENDIAN_REG[0] Bit w[0] w[1] w[2] w[3] w[4] w[5] w[6] w[7]
[31:24] AES_KEY_7_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24]
[23:16] AES_KEY_7_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16]
0 0
[15:8] AES_KEY_7_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8]
[7:0] AES_KEY_7_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0]
[31:24] AES_KEY_7_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_0_REG[7:0]
[23:16] AES_KEY_7_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_0_REG[15:8]
0 1
[15:8] AES_KEY_7_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_0_REG[23:16]
[7:0] AES_KEY_7_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_0_REG[31:24]
[31:24] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_7_REG[31:24]
[23:16] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_7_REG[23:16]
1 0
[15:8] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_7_REG[15:8]
[7:0] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_7_REG[7:0]
[31:24] AES_KEY_0_REG[7:0] AES_KEY_1_REG[7:0] AES_KEY_2_REG[7:0] AES_KEY_3_REG[7:0] AES_KEY_4_REG[7:0] AES_KEY_5_REG[7:0] AES_KEY_6_REG[7:0] AES_KEY_7_REG[7:0]
[23:16] AES_KEY_0_REG[15:8] AES_KEY_1_REG[15:8] AES_KEY_2_REG[15:8] AES_KEY_3_REG[15:8] AES_KEY_4_REG[15:8] AES_KEY_5_REG[15:8] AES_KEY_6_REG[15:8] AES_KEY_7_REG[15:8]
1 1
[15:8] AES_KEY_0_REG[23:16] AES_KEY_1_REG[23:16] AES_KEY_2_REG[23:16] AES_KEY_3_REG[23:16] AES_KEY_4_REG[23:16] AES_KEY_5_REG[23:16] AES_KEY_6_REG[23:16] AES_KEY_7_REG[23:16]
[7:0] AES_KEY_0_REG[31:24] AES_KEY_1_REG[31:24] AES_KEY_2_REG[31:24] AES_KEY_3_REG[31:24] AES_KEY_4_REG[31:24] AES_KEY_5_REG[31:24] AES_KEY_6_REG[31:24] AES_KEY_7_REG[31:24]
21. AES Accelerator
2. Write 1 to AES_START_REG.
Consecutive Operations
Every time an operation is completed, only AES_TEXT_m_REG is modified by the AES Accelerator. Initialization
can, therefore, be simplified in a series of consecutive operations.
2. Load AES_TEXT_m_REG.
3. Write 1 to AES_START_REG.
21.3.5 Speed
The AES Accelerator requires 11 to 15 clock cycles to encrypt a message block, and 21 or 22 clock cycles to
decrypt a message block.
21.5 Registers
T
AR
d)
ST
ve
er
S_
s
AE
(re
31 1 0
0x00000000 x Reset
LE
d)
e
ID
rv
S_
se
AE
(re
31 1 0
0x00000000 1 Reset
AES_IDLE AES Idle register. Reads ’zero’ while the AES Accelerator is busy processing; reads ’one’
otherwise. (RO)
DE
d)
O
ve
M
r
S_
se
AE
(re
31 3 2 0
0x00000000 0 Reset
AES_MODE Selects the AES accelerator mode of operation. See Table 85 for details. (R/W)
31 0
0x000000000 Reset
31 0
0x000000000 Reset
A N
DI
)
ed
EN
rv
S_
se
AE
(re
31 6 5 0
0x0000000 1 1 1 1 1 1 Reset
22.1 Introduction
The SHA Accelerator is included to speed up SHA hashing operations significantly, compared to SHA hashing
algorithms implemented solely in software. The SHA Accelerator supports four algorithms of FIPS PUB 180-4,
specifically SHA-1, SHA-256, SHA-384 and SHA-512.
22.2 Features
Hardware support for popular secure hashing algorithms:
• SHA-1
• SHA-256
• SHA-384
• SHA-512
The SHA Accelerator is unable to perform the padding operation of “5.1 Padding the Message” in FIPS PUB
180-4; Note that the user software is expected to pad the message before feeding it into the accelerator.
(i) (i)
As described in “2.2.1: Parameters” in FIPS PUB 180-4, “M0 is the leftmost word of message block i”. M0 is
stored in SHA_TEXT_0_REG. In the same fashion, the SHA_TEXT_1_REG register stores the second left-most
(N )
word of a message block M1 , etc.
As described in “2.2.1 Parameters” in FIPS PUB 180-4, “H (N ) is the final hash value, and is used to determine
(i) (N )
the message digest”, while “H0 is the leftmost word of hash value i”, so the leftmost word H0 in the message
(N )
digest is stored in SHA_TEXT_0_REG. In the same fashion, the second leftmost word H1 in the message
digest is stored in SHA_TEXT_1_REG, etc.
(c) Wait for SHA_X_BUSY_REG to read 0, indicating that the operation is completed.
(c) Wait for SHA_X_BUSY_REG to read 0, indicating that the operation is completed.
22.3.4 Speed
The SHA Accelerator requires 60 to 100 clock cycles to process a message block and 8 to 20 clock cycles to
calculate the final digest.
22.5 Registers
31 0
0x000000000 Reset
SHA_TEXT_n_REG (n: 0-31) SHA Message block and hash result register. (R/W)
RT
TA
_S
A1
)
ed
SH
rv
A_
se
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA1_START Write 1 to start an SHA-1 operation on the first message block. (WO)
UE
IN
NT
O
_C
A1
d)
SH
ve
A_
r
se
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA1_CONTINUE Write 1 to continue the SHA-1 operation with subsequent blocks. (WO)
SH
e
rv
A_
se
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA1_LOAD Write 1 to finish the SHA-1 operation to calculate the final message hash. (WO)
Y
US
_B
A1
d)
SH
ve
A_
r
se
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA1_BUSY SHA-1 operation status: 1 if the SHA accelerator is processing data, 0 if it is idle.
(RO)
R T
TA
_S
56
A2
d )
SH
ve
A_
r
se
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA256_START Write 1 to start an SHA-256 operation on the first message block. (WO)
UE
IN
NT
O
_C
56
A2
)
ed
H
_S
rv
se
A
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA256_CONTINUE Write 1 to continue the SHA-256 operation with subsequent blocks. (WO)
AD
O
_L
56
A2
d)
SH
ve
A_
er
s
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA256_LOAD Write 1 to finish the SHA-256 operation to calculate the final message hash.
(WO)
USY
_B
56
A2
d)
SH
ve
A_
r
se
SH
(re
31 1 0
0x00000000 0 Reset
RT
TA
_S
84
A3
d)
SH
e
rv
A_
se
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA384_START Write 1 to start an SHA-384 operation on the first message block. (WO)
E
NU
I
NT
O
_C
84
A3
d)
SH
ve
A_
er
s
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA384_CONTINUE Write 1 to continue the SHA-384 operation with subsequent blocks. (WO)
AD
O
_L
84
A3
d)
SH
ve
A_
r
se
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA384_LOAD Write 1 to finish the SHA-384 operation to calculate the final message hash.
(WO)
USY
_B
84
A3
)
ed
SH
rv
A_
se
SH
(re
31 1 0
0x00000000 0 Reset
RT
TA
_S
12
A5
d)
SH
ve
A_
er
s
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA512_START Write 1 to start an SHA-512 operation on the first message block. (WO)
UE
IN
NT
O
_C
12
A5
)d
SH
ve
A_
r
se
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA512_CONTINUE Write 1 to continue the SHA-512 operation with subsequent blocks. (WO)
AD
O
_L
12
A5
d)
SH
ve
A_
r
se
SH
(re
31 1 0
0x00000000 0 Reset
SHA_SHA512_LOAD Write 1 to finish the SHA-512 operation to calculate the final message hash.
(WO)
Y
US
_B
12
A5
d)
SH
ve
A_
er
s
SH
(re
31 1 0
0x00000000 0 Reset
23.1 Introduction
The RSA Accelerator provides hardware support for multiple precision arithmetic operations used in RSA
asymmetric cipher algorithms.
Sometimes, multiple precision arithmetic is also called ”bignum arithmetic”, ”bigint arithmetic” or ”arbitrary
precision arithmetic”.
23.2 Features
• Support for large-number modular exponentiation
When the RSA Accelerator is released from reset, the register RSA_CLEAN_REG reads 0 and an initialization
process begins. Hardware initializes the four memory blocks by setting them to 0. After initialization is complete,
RSA_CLEAN_REG reads 1. For this reason, software should query RSA_CLEAN_REG after being released from
reset, and before writing to any RSA Accelerator memory blocks or registers for the first time.
The RSA Accelerator supports operand lengths of N ∈ {512, 1024, 1536, 2048, 2560, 3072, 3584, 4096} bits. The
bit length of arguments Z, X, Y , M , and r can be any one from the N set, but all numbers in a calculation must
be of the same length. The bit length of M ′ is always 32.
To represent the numbers used as operands, define a base-b positional notation, as follows:
b = 232
In this notation, each number is represented by a sequence of base-b digits, where each base-b digit is a 32-bit
word. Representing an N -bit number requires n base-b digits (all of the possible N lengths are multiples of
32).
N
n=
32
Z = (Zn−1 Zn−2 · · · Z0 )b
X = (Xn−1 Xn−2 · · · X0 )b
Y = (Yn−1 Yn−2 · · · Y0 )b
M = (Mn−1 Mn−2 · · · M0 )b
r = (rn−1 rn−2 · · · r0 )b
Each of the n values in Zn−1 ~ Z0 , Xn−1 ~ X0 , Yn−1 ~ Y0 , Mn−1 ~ M0 , rn−1 ~ r0 represents one base-b digit (a
32-bit word).
Zn−1 , Xn−1 , Yn−1 , Mn−1 and rn−1 are the most significant bits of Z, X, Y , M , while Z0 , X0 , Y0 , M0 and r0 are
the least significant bits.
If we define
R = bn
r = R2 mod M (1)
M ′′ × M + 1 = R × R−1
(2)
M ′ = M ′′ mod b
(Equation 2 is written in a form suitable for calculations using the extended binary GCD algorithm.)
Users need to write data to each memory block only according to the length of the number; data beyond
this length are ignored.
3. Write M ′ to RSA_M_PRIME_REG.
4. Write 1 to RSA_MODEXP_START_REG.
5. Wait for the operation to be completed. Poll RSA_INTERRUPT_REG until it reads 1, or until the RSA_INTR
interrupt is generated.
After the operation, the RSA_MODEXP_MODE_REG register, memory blocks RSA_Y_MEM and RSA_M_MEM,
as well as the RSA_M_PRIME_REG will not have changed. However, Xi in RSA_X_MEM and ri in RSA_Z_MEM
will have been overwritten. In order to perform another operation, refresh the registers and memory blocks, as
required.
The RSA Accelerator supports large-number modular multiplication with eight different operand lengths, which
are the same as in the large-number modular exponentiation. The operation is performed by a combination of
software and hardware. The software performs two hardware operations in sequence.
2. Write Xi , Mi and ri (i ∈ [0, n) ∩ N) to registers RSA_X_MEM, RSA_M_MEM and RSA_Z_MEM. Write data
to each memory block only according to the length of the number. Data beyond this length are ignored.
3. Write M ′ to RSA_M_PRIME_REG.
4. Write 1 to RSA_MULT_START_REG.
5. Wait for the first round of the operation to be completed. Poll RSA_INTERRUPT_REG until it reads 1, or
until the RSA_INTR interrupt is generated.
Users need to write to the memory block only according to the length of the number. Data beyond this
length are ignored.
8. Write 1 to RSA_MULT_START_REG.
9. Wait for the second round of the operation to be completed. Poll RSA_INTERRUPT_REG until it reads 1, or
until the RSA_INTR interrupt is generated.
After the operation, the RSA_MULT_MODE_REG register, and memory blocks RSA_M_MEM and
RSA_M_PRIME_REG remain unchanged. Users do not need to refresh these registers or memory blocks if the
values remain the same.
Operands X and Y need to be extended to form arguments X̂ and Ŷ which have the same length (N̂ bits) as
the result Z. X is left-extended and Y is right-extended, and defined as follows:
N
n=
32
N̂ = 2 × N
N̂
n̂ = = 2n
32
X̂ = (X̂n̂−1 X̂n̂−2 · · · X̂0 )b = (00 · · · 0} X)b = (00
| {z · · · 0} Xn−1 Xn−2 · · · X0 )b
| {z
n n
2. Write X̂i and Ŷi (i ∈ [0, n̂) ∩ N) to RSA_X_MEM and RSA_Z_MEM, respectively.
Write the valid data into each number’s memory block, according to their lengths. Values beyond this
length are ignored. Half of the base-b positional notations written to the memory are zero (using the
derivations shown above). These zero values are indispensable.
3. Write 1 to RSA_MULT_START_REG.
4. Wait for the operation to be completed. Poll RSA_INTERRUPT_REG until it reads 1, or until the RSA_INTR
interrupt is generated.
23.5 Registers
31 0
0x000000000 Reset
DE
O
_M
XP
DE
)
O
d
ve
M
er
A_
s
RS
(re
31 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
T
AR
_ST
XP
DE
d)
O
ve
M
r
A_
se
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
M
rv
A_
se
RS
(re
31 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_MULT_MODE This register contains the mode of modular multiplication and multiplication.
(R/W)
T
AR
ST
T_
UL
d)
ve
M
r
A_
se
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
T
UP
RR
TE
d )
ve
IN
r
A_
se
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_INTERRUPT RSA interrupt status register. Will read 1 once an operation has completed. (R/W)
N
EA
)
ed
CL
rv
A_
se
RS
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RSA_CLEAN This bit will read 1 once the memory initialization is completed. (RO)
24.1 Introduction
The ESP32 contains a true random number generator, whose values can be used as a basis for cryptographical
operations, among other things.
24.2 Feature
It can generate true random numbers.
When Wi-Fi or BT is enabled, the random number generator is fed two bits of entropy every APB clock cycle
(normally 80 MHz). Thus, for the maximum amount of entropy, it is advisable to read the random register at a
maximum rate of 5 MHz.
A data sample of 2 GB, read from the random number generator with Wi-Fi enabled and the random register
read at 5 MHz, has been tested using the Dieharder Random Number Testsuite (version 3.31.1). The sample
passed all tests.
24.5 Register
31 0
0x000000000 Reset
25.1 Overview
Many variants of the ESP32 must store programs and data in external flash memory. The external flash memory
chip is likely to contain proprietary firmware and sensitive user data, such as credentials for gaining access to a
private network. The Flash Encryption block can encrypt code and write encrypted code to off-chip flash
memory for enhanced hardware security. When the CPU reads off-chip flash through the cache, the Flash
Decryption block can automatically decrypt instructions and data read from the off-chip flash, thus providing
hardware-based security for application code.
25.2 Features
• Various key generation methods
• Software-based encryption
• Register configuration, system parameters and boot mode jointly determine the flash encryption/decryption
function.
The Flash Encryption/Decryption module consists of three parts, namely the Key Generator, Flash Encryption
block and Flash Decryption block. The structure of these parts is shown in Figure 124. The Key Generator is
shared by both the Flash Encryption block and the Flash Decryption block, which can function
simultaneously.
Then, according to system parameter flash_crypt_config, and off-chip flash physical addresses Addre and Addrd
accessed by the Flash Encryption block and the Flash Decryption block, the Key Generator will respectively figure
out that:
Keye = g(Keyo , f lash_crypt_conf ig, Addre ),
Keyd = g(Keyo , f lash_crypt_conf ig, Addrd ).
When all values of system parameter flash_crypt_config are 0, Keye and Keyd are not relevant to the physical
address of the off-chip flash. When all values of system parameter flash_crypt_config are not 0, every 8-word
block on the off-chip flash has a dedicated Keye and Keyd .
The Flash Encryption block requires software intervention during operation. The steps are as follows:
2. Write the physical address prepared for the off-chip flash on register FLASH_ENCRYPT_ADDRESS_REG.
The address must be 8-word boundary aligned.
3. The Flash Encryption block must encrypt 8-word long code segments. Write the lowest word to register
FLASH_ENCRYPT_BUFFER_0_REG, the second-lowest word into FLASH_ENCRYPT_BUFFER_1_REG,
and so on, up to FLASH_ENCRYPT_BUFFER_7_REG.
6. Use this function and write any 8-word code to the 8-word aligned address on the off-chip flash via the
peripheral SPI0.
In Steps 1 to 5, the Flash Encryption block encrypts 8-word long codes. The key encryption algorithm uses
Keye . The encryption result will also be 8-word long. In Step 6, the peripheral SPI0 writes encrypted results of
the Flash Encryption block to the off-chip flash. One parameter of the function used in Step 6 will be the physical
address of the off-chip flash. The physical address must be 8-word boundary aligned. Also, the value must be
the same as the value written into register FLASH_ENCRYPT_ADDRESS_REG during Step 2. Even though the
function used in Step 6 still has a parameter with an 8-word long code, the parameter will be meaningless if
Steps 1 to 5 are executed. The Peripheral SPI0 will use the encrypted result instead. If the Flash Encryption
block is not operating, or has not executed Steps 1 to 5, Step 6 will not use the encrypted result. Instead, the
function parameter will be used.
Even though software participates in the whole process, it cannot directly read the encrypted codes. Instead, the
encrypted codes are integrated into the off-chip flash. Even though the CPU can skip the cache and get the
encrypted code directly by reading the off-chip flash, the software can by no means access Keye .
When the Flash Decryption block is operating, the CPU will read instructions and data from the off-chip flash via
the cache. The Flash Decryption block automatically decrypts the instructions and data in the cache. The entire
decryption process does not need software intervention and is transparent to the cache. The decryption
algorithm can decrypt the code that has been encrypted by the Flash Encryption block. Software cannot access
the key algorithm Keyd used.
When the Flash Encryption block is not operating, it does not have any effect on the contents stored in the
off-chip flash, be they encrypted or unencrypted. What the CPU reads via the cache is the original information
stored in the off-chip flash.
In the efuse system parameter flash_crypt_cnt (7 bits wide), if the number of bits with value 1 is odd, the
Flash Decryption block is operational. Otherwise, it is not.
25.5 Register
31 0
0x000000000 Reset
T
AR
ST
d )
H_
ve
r
AS
se
(re
FL
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
FLASH_START Set this bit to start encryption operation on data buffer. (WO)
31 0
0x000000000 Reset
H_
rv
AS
se
(re
FL
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
26. PID/MPU/MMU
26.1 Introduction
Every peripheral and memory section in the ESP32 is accessed through either an MMU (Memory Management
Unit) or an MPU (Memory Protection Unit). An MPU can allow or disallow the access of an application to a
memory range or peripheral, depending on what kind of permission the OS has given to that particular
application. An MMU can perform the same operation, as well as a virtual-to-physical memory address
translation. This can be used to map an internal or external memory range to a certain virtual memory area.
These mappings can be application-specific. Therefore, each application can be adjusted and have the memory
configuration that is necessary for it to run properly. To differentiate between the OS and applications, there are
eight Process Identifiers (or PIDs) that each application, or OS, can run. Furthermore, each application, or OS, is
equipped with their own sets of mappings and rights.
26.2 Features
• Eight processes in each of the PRO_CPU and APP_CPU
• MPU/MMU management of on-chip memories, off-chip memories, and peripherals, based on process ID
There are two peripheral PID controllers in the system, one for each of the two CPUs in the ESP32. Having a PID
controller per CPU allows running different processes on different CPUs, if so desired.
26.3.2 MPU/MMU
The MPU and MMU manage on-chip memories, off-chip memories, and peripherals. To do this they are based
on the process of accessing the peripheral or memory region. More specifically, when a code tries to access a
MMU/MPU-protected memory region or peripheral, the MMU or MPU will receive the PID from the PID generator
that is associated with the CPU on which the process is running.
For on-chip memory and peripherals, the decisions the MMU and MPU make are only based on this PID,
whereas the specific CPU the code is running on is not taken into account. Subsequently, the MMU/MPU
configuration for the internal memory and peripherals allows entries only for the eight different PIDs. In contrast,
the MMU moderating access to the external memory takes not only the PID into account, but also the CPU the
request is coming from. This means that MMUs have configuration options for every PID when running on the
APP_CPU, as well as every PID when running on the PRO_CPU. While, in practice, accesses from both CPUs
will be configured to have the same result for a specific process, doing so is not a hardware requirement.
The decision an MPU can make, based on this information, is to allow or deny a process to access the memory
region or peripheral. An MMU has the same function, but additionally it redirects the virtual memory access, which
the process acquired, into a physical memory access that can possibly reach out an entirely different physical
memory region. This way, MMU-governed memory can be remapped on a process-by-process basis.
The on-chip memory is governed by fixed-function MPUs, configurable MPUs, and MMUs:
Address range
Name Size Governed by
From To
ROM0 384 KB 0x4000_0000 0x4005_FFFF Static MPU
ROM1 64 KB 0x3FF9_0000 0x3FF9_FFFF Static MPU
64 KB 0x4007_0000 0x4007_FFFF Static MPU
SRAM0
128 KB 0x4008_0000 0x4009_FFFF SRAM0 MMU
128 KB 0x3FFE_0000 0x3FFF_FFFF Static MPU
SRAM1 (aliases) 128 KB 0x400A_0000 0x400B_FFFF Static MPU
32 KB 0x4000_0000 0x4000_7FFF Static MPU
72 KB 0x3FFA_E000 0x3FFB_FFFF Static MPU
SRAM2
128 KB 0x3FFC_0000 0x3FFD_FFFF SRAM2 MMU
8 KB 0x3FF8_0000 0x3FF8_1FFF RTC FAST MPU
RTC FAST (aliases)
8 KB 0x400C_0000 0x400C_1FFF RTC FAST MPU
RTC SLOW 8 KB 0x5000_0000 0x5000_1FFF RTC SLOW MPU
Static MPUs
ROM0, ROM1, the lower 64 KB of SRAM0, SRAM1 and the lower 72 KB of SRAM2 are governed by a static
MPU. The behaviour of these MPUs are hardwired and cannot be configured by software. They moderate access
to the memory region solely through the PID of the current process. When the PID of the process is 0 or 1, the
memory can be read (and written when it is RAM) using the addresses specified in Table 95. When it is 2 ~ 7, the
memory cannot be accessed.
The 8 KB RTC FAST Memory as well as the 8 KB of RTC SLOW Memory are governed by two configurable
MPUs. The MPUs can be configured to allow or deny access to each individual PID, using the
RTC_CNTL_RTC_PID_CONFIG_REG and DPORT_AHBLITE_MPU_TABLE_RTC_REG registers. Setting a bit in
these registers will allow the corresponding PID to read or write from the memory; clearing the bit disallows
access. Access for PID 0 and 1 to RTC SLOW memory cannot be configured and is always enabled. Table 96
and 97 define the bit-to-PID mappings of the registers.
Register RTC_CNTL_RTC_PID_CONFIG_REG is part of the RTC peripheral and can only be modified by
processes with a PID of 0; register DPORT_AHBLITE_MPU_TABLE_RTC_REG is a Dport register and can be
changed by processes with a PID of 0 or 1.
Both the upper 128 KB of SRAM0 and the upper 128 KB of SRAM2 are governed by an MMU. Not only can
these MMUs allow or deny access to the memory they govern (just like the MPUs do), but they are also capable
of translating the address a CPU reads from or writes to (which is a virtual address) to a possibly different address
in memory (the physical address).
In order to accomplish this, the internal RAM MMUs divide the memory range they govern into 16 pages. The
page size is configurable as 8 KB, 4 KB and 2 KB. When the page size is 8 KB, the 16 pages span the entire 128
KB memory region; when the page size is 4 KB or 2 KB, a non-MMU-covered region of 64 or 96 KB,
respectively, will exist at the end of the memory space. Similar to the virtual and physical addresses, it is also
possible to imagine the pages as having a virtual and physical component. The MMU can convert an address
within a virtual page to an address within a physical page.
For PID 0 and 1, this mapping is 1-to-1, meaning that a read from or write to a certain virtual page will always be
converted to a read from or write to the exact same physical page. This allows an operating system, running
under PID 0 and/or 1, to always have access to the entire physical memory range.
For PID 2 to 7, however, every virtual page can be reconfigured, on a per-PID basis, to map to a different physical
page. This way, reads and writes to an offset within a virtual page get translated into reads and writes to the
same offset within a different physical page. This is illustrated in Figure 125: the CPU (running a process with a
PID between 2 to 7) tries to access memory address 0x3FFC_2345. This address is within the virtual Page 1
memory region, at offset 0x0345. The MMU is instructed that for this particular PID, it should translate an access
to virtual page 1 into physical Page 2. This causes the memory access to be redirected to the same offset as the
virtual memory access, yet in Page 2, which results in the effective access of physical memory address
0x3FFC_4345. The page size in this example is 8 KB.
3FFC_0000 3FFC_0000
PAGE 0 PAGE 0
3FFC_2000 3FFC_2000
3FFC_2345 PAGE 1 PAGE 1
3FFC_4000 3FFC_4000
3FFC_4345
PAGE 2 PAGE 2
3FFC_6000 3FFC_6000
3FFD_E000 3FFD_E000
PAGE 15 PAGE 15
3FFE_0000 3FFE_0000
Table 98: Page Mode of MMU for the Remaining 128 KB of Internal SRAM0 and SRAM2
For the MMU-managed region of SRAM0 and SRAM2, the page size is configurable as 8 KB, 4 KB and 2 KB.
The configuration is done by setting the DPORT_IMMU_PAGE_MODE (for SRAM0) and
DPORT_DMMU_PAGE_MODE (for SRAM2) bits in registers DPORT_IMMU_PAGE_MODE_REG and
DPORT_DMMU_PAGE_MODE_REG, as detailed in Table 98. Because the number of pages for either region is
fixed at 16, the total amount of memory covered by these pages is 128 KB when 8 KB pages are selected, 64
KB when 4 KB pages are selected, and 32 KB when 2 KB pages are selected. This implies that for 8 KB pages,
the entire MMU-managed range is used, but for the other page sizes there will be a part of the 128 KB memory
that will not be governed by the MMU settings. Concretely, for a page size of 4 KB, these regions are
0x4009_0000 to 0x4009_FFFF and 0x3FFD_0000 to 0x3FFD_FFFF; for a page size of 2 KB, the regions are
0x4008_8000 to 0x4009_FFFF and 0x3FFC_8000 to 0x3FFD_FFFF. These ranges are readable and writable by
processes with a PID of 0 or 1; processes with other PIDs cannot access this memory.
The layout of the pages in memory space is linear, namely, an SRAM0 MMU page n covers address space
0x40080000 + (pagesize ∗ n) to 0x40080000 + (pagesize ∗ (n + 1) − 1); similarily, an SRAM2 MMU page n covers
0x3F F C0000 + (pagesize ∗ n) to 0x3F F C0000 + (pagesize ∗ (n + 1) − 1). Tables 99 and 100 show the resulting
addresses in full.
MMU Mapping
For each of the SRAM0 and SRAM2 MMUs, access rights and virtual to physical page mapping are done by a
set of 16 registers. In contrast to most of the other MMUs, each register controls a physical page, not a virtual
one. These registers control which of the PIDs have access to the physical memory, as well as which virtual page
maps to this physical page. The bits in the register are described in Table 101. Keep in mind that these registers
only govern accesses from processes with PID 2 to 7; PID 0 and 1 always have full read and write access to all
pages and no virtual-to-physical mapping is done. In other words, if a process with a PID of 0 or 1 accesses
virtual page x, the access will always go to physical page x, regardless of these register settings. These registers,
as well as the page size selection registers DPORT_IMMU_PAGE_MODE_REG and
DPORT_DMMU_PAGE_MODE_REG, are only writable from a process with PID 0 or 1.
The memory governed by the SRAM0 MMU is accessed through the processors I-bus, while the processor
accesses the memory governed by the SRAM2 MMU through the D-bus. Thus, the normal envisioned use is for
the code to be stored in the SRAM0 MMU pages and data in the MMU pages of SRAM2. In general, applications
running under a PID of 2 to 7 are not expected to modify their own code, because for these PIDs access to the
MMU pages of SRAM0 is read-only. These applications must, however, be able to modify their data section, so
that they are allowed to read as well as write MMU pages located in SRAM2. As stated before, processes
running under PID 0 or 1 always have full read-and-write access to both memory ranges.
DMA MPU
Applications may want to configure the DMA to send data straight from or to the peripherals they can control.
With access to DMA, a malicious process may also be able to copy data from or to a region it cannot normally
access. In order to be secure against that scenario, there is a DMA MPU which can be used to disallow DMA
transfers from memory regions with sensitive data in them.
For each 8 KB region in the SRAM1 and SRAM2 regions, there is a bit in the DPORT_AHB_MPU_TABLE_n_REG
registers which tells the MPU to either allow or disallow DMA access to this region. The DMA MPU uses only
these bits to decide if a DMA transfer can be started; the PID of the process is not a factor. This means that
when the OS wants to restrict its processes in a heterogenous fashion, it will need to re-load these registers with
the values applicable to the process to be run on every context switch.
The register bits that govern access to the 8 KB regions are detailed in Table 102. When a register bit is set, DMA
can read/write the corresponding 8 KB memory range. When the bit is cleared, access to that memory range is
denied.
Note:
In hardware, there are three instruction buses corresponding to V Addr1 , V Addr2 , and V Addr3 , respectively. These
three buses can initiate load or fetch accesses simultaneously, but only one access is true. If more than one unmasked
instruction buses are present, then bit8 of all MMU entries should be set to zero. Otherwise, when an invalid MMU entry
is used by an access, the cache will be stalled even if there is no program at this access.
Accesses to the external flash and external SPI RAM are done through a cache and are also handled by an
MMU. This Cache MMU can apply different mappings, depending on the PID of the process as well as the CPU
the process is running on. The MMU does this in a way that is similar to the internal memory MMU, that is, for
every page of virtual memory, it has a register detailing which physical page this virtual page should map to.
There are differences between the MMUs governing the internal memory and the Cache MMU, though. First of
all, the Cache MMU has a fixed page size (which is 64 KB for external flash and 32 KB for external RAM) and
secondly, instead of specifying access rights in the MMU entries, the Cache MMU has explicit mapping tables for
each PID and processor core. The MMU mapping configuration registers will be referred to as ’entries’ in the rest
of this chapter. These registers are only accessible from processes with a PID of 0 or 1; processes with a PID of 2
to 7 will have to delegate to one of the above-mentioned processes to change their MMU settings.
The MMU entries, as stated before, are used for mapping a virtual memory page access to a physical memory
page access. The MMU controls five regions of virtual address space, detailed in Table 103. V Addr1 to V Addr4
are used for accessing external flash, whereas V AddrRAM is used for accessing external RAM. Note that
V Addr4 is a subset of V Addr0 .
Boundary address
Name Size Page quantity
Low High
V Addr0 4 MB 0x3F40_0000 0x3F7F_FFFF 64
V Addr1 4 MB 0x4000_0000 0x403F_FFFF 64*
V Addr2 4 MB 0x4040_0000 0x407F_FFFF 64
V Addr3 4 MB 0x4080_0000 0x40BF_FFFF 64
V Addr4 1 MB 0x3F40_0000 0x3F4F_FFFF 16
V AddrRAM 4 MB 0x3F80_0000 0x3FBF_FFFF 128
* The configuration entries for address range 0x4000_0000 ~ 0x403F_FFFF are implemented and docu-
mented as if it were a full 4 MB address range, but it is not accessible as such. Instead, the address range
0x4000_0000 ~ 0x400C_1FFF accesses on-chip memory. This means that some of the configuration entries for
V Addr1 will not be used.
External Flash
For flash, the relationships among entry numbers, virtual memory ranges, and PIDs are detailed in Tables 104 and
105, which for every memory region and PID combination specify the first MMU entry governing the mapping.
This number refers to the MMU entry governing the very first page; the entire region is described by the amount
of pages specified in the ’count’ column.
These two tables are essentially the same, with the sole difference being that the APP_CPU entry numbers are
2048 higher than the corresponding PRO_CPU numbers. Note that memory regions V Addr0 and V Addr1 are
only accessible using PID 0 and 1, while V Addr4 can only be accessed by PID 2 ~ 7.
As these tables show, virtual address V Addr1 can only be used by processes with a PID of 0 or 1. There is a
special mode to allow processes with a PID of 2 to 7 to read the External Flash via address V Addr1 . When the
DPORT_PRO_SINGLE_IRAM_ENA bit of register DPORT_PRO_CACHE_CTRL_REG is 1, the MMU enters this
special mode for PRO_CPU memory accesses. Similarily, when the DPORT_APP_SINGLE_IRAM_ENA bit of
register DPORT_APP_CACHE_CTRL_REG is 1, the APP_CPU accesses memory using this special mode. In this
mode, the process and virtual address page supported by each configuration entry of MMU are different. For
details please see Table 106 and 107. As shown in these tables, in this special mode V Addr2 and V Addr3
cannot be used to access External Flash.
Every configuration entry of MMU maps a virtual address page of a CPU process to a physical address page. An
entry is 32 bits wide. Of these, bits 0~7 indicate the physical page the virtual page is mapped to. Bit 8 should be
cleared to indicate that the MMU entry is valid; entries with this bit set will not map any physical address to the
virtual address. Bits 10 to 32 are unused and should be written as zero. Because there are eight address bits in
an MMU entry, and the page size for external flash is 64 KB, a maximum of 256 * 64 KB = 16 MB of external flash
is supported.
Examples
Example 1. A PRO_CPU process, with a PID of 1, needs to read external flash address 0x07_2375 via virtual
address 0x3F70_2375. The MMU is not in the special mode.
• According to Table 103, virtual address 0x3F70_2375 resides in the 0x30’th page of V Addr0 .
• According to Table 104, the MMU entry for V Addr0 for PID 0/1 for the PRO_CPU starts at 0.
• The modified MMU entry is 0 + 0x30 = 0x30.
• Address 0x07_2375 resides in the 7’th 64 KB-sized page.
• MMU entry 0x30 needs to be set to 7 and marked as valid by setting the 8’th bit to 0. Thus, 0x007 is
written to MMU entry 0x30.
Example 2. An APP_CPU process, with a PID of 4, needs to read external flash address 0x44_048C via virtual
address 0x4044_048C. The MMU is not in special mode.
• According to Table 103, virtual address 0x4044_048C resides in the 0x4’th page of V Addr2 .
• According to Table 105, the MMU entry for V Addr2 for PID 4 for the APP_CPU starts at 2560.
• The modified MMU entry is 2560 + 0x4 = 2564.
• Address 0x44_048C resides in the 0x44’th 64 KB-sized page.
• MMU entry 2564 needs to be set to 0x44 and marked as valid by setting the 8’th bit to 0. Thus, 0x044 is
written to MMU entry 2564.
External RAM
Processes running on PRO_CPU and APP_CPU can read and write External SRAM via the Cache at virtual
address range V AddrRAM , which is 0x3F80_0000 ~ 0x3FBF_FFFF. As with the flash MMU, the address space
and the physical memory are divided into pages. For the External RAM MMU, the page size is 32 KB and the
MMU is able to map 256 physical pages into the virtual address space, allowing for 32 KB * 256 = 8 MB of
physical external RAM to be mapped.
The mapping of virtual pages into this memory range depends on the mode this MMU is in: Low-High mode,
Even-Odd mode, or Normal mode. In all cases, the DPORT_PRO_DRAM_HL bit and
DPORT_PRO_DRAM_SPLIT bit in register DPORT_PRO_CACHE_CTRL_REG, the DPORT_APP_DRAM_HL bit
and DPORT_APP_DRAM_SPLIT bit in register DPORT_APP_CACHE_CTRL_REG determine the virtual address
mode for External SRAM. For details, please see Table 108. If a different mapping for the PRO_CPU and
APP_CPU is required, the Normal Mode should be selected, as it is the only mode that can provide this. If it is
allowable for the PRO_CPU and the APP_CPU to share the same mapping, using either High-Low or Even-Odd
mode can give a speed gain when both CPUs access memory frequently.
In case the APP_CPU cache is disabled, which renders the region of 0x4007_8000 to 0x4007_FFFF usable as
normal internal RAM, the usability of the various cache modes changes. Normal mode will allow PRO_CPU
access to external RAM to keep functioning, but the APP_CPU will be unable to access the external RAM.
High-Low mode allows both CPUs to use external RAM, but only for the 2 MB virtual memory addresses from
0x3F80_0000 to 0x3F9F_FFFF. It is not advised to use Even-Odd mode with the APP_CPU cache region
disabled.
DPORT_PRO_DRAM_HL DPORT_PRO_DRAM_SPLIT
Mode
DPORT_APP_DRAM_HL DPORT_APP_DRAM_SPLIT
Low-High 1 0
Even-Odd 0 1
Normal 0 0
In normal mode, the virtual-to-physical page mapping can be different for both CPUs. Page mappings for
PRO_CPU are set using the MMU entries for L V AddrRAM , and page mappings for the APP_CPU can be
configured using the MMU entries for R V AddrRAM . In this mode, all 128 pages of both L V Addr and R V Addr
are fully used, allowing a maximum of 8 MB of memory to be mapped; 4 MB into PRO_CPU address space and
a possibly different 4 MB into the APP_CPU address space, as can be seen in Table 109.
PRO_CPU address
Virtual address Size
Low High
L
V AddrRAM 4 MB 0x3F80_0000 0x3FBF_FFFF
APP_CPU address
Virtual address Size
Low High
R
V AddrRAM 4 MB 0x3F80_0000 0x3FBF_FFFF
In Low-High mode, both the PRO_CPU and the APP_CPU use the same mapping entries. In this mode
L
V AddrRAM is used for the lower 2 MB of the virtual address space, while R V AddrRAM is used for the upper 2
MB. This also means that the upper 64 MMU entries for L V AddrRAM , as well as the lower 64 entries for
R
V AddrRAM , are unused. Table 110 details these address ranges.
PRO_CPU/APP_CPU address
Virtual address Size
Low High
L
V AddrRAM 2 MB 0x3F80_0000 0x3F9F_FFFF
R
V AddrRAM 2 MB 0x3FA0_0000 0x3FBF_FFFF
In Even-Odd memory, the VRAM is split into 32-byte chunks. The even chunks are resolved through the MMU
entries for L V AddrRAM , the odd chunks through the entries for R V AddrRAM . Generally, the MMU entries for
L
V AddrRAM and R V AddrRAM are set to the same values, so that the virtual pages map to a contiguous region
of physical memory. Table 111 details this mode.
PRO_CPU/APP_CPU address
Virtual address Size
Low High
L
V AddrRAM 32 Bytes 0x3F80_0000 0x3F80_001F
R
V AddrRAM 32 Bytes 0x3F80_0020 0x3F80_003F
L
V AddrRAM 32 Bytes 0x3F80_0040 0x3F80_005F
R
V AddrRAM 32 Bytes 0x3F80_0060 0x3F80_007F
···
L
V AddrRAM 32 Bytes 0x3FBF_FFC0 0x3FBF_FFDF
R
V AddrRAM 32 Bytes 0x3FBF_FFE0 0x3FBF_FFFF
The bit configuration of the External RAM MMU entries is the same as for the flash memory: the entries are 32-bit
registers, with the lower nine bits being used. Bits 0~7 contain the physical page the entry should map its
associate virtual page address to, while bit 8 is cleared when the entry is valid and set when it is not. Table 112
details the first MMU entry number for L V AddrRAM and R V AddrRAM for all PIDs.
Examples
Example 1. A PRO_CPU process, with a PID of 7, needs to read or write external RAM address 0x7F_A375 via
virtual address 0x3FA7_2375. The MMU is in Low-High mode.
• According to Table 103, virtual address 0x3FA7_2375 resides in the 0x4E’th 32-KB-page of V AddrRAM .
• According to Table 110, virtual address 0x3FA7_2375 is governed by R V AddrRAM .
• According to Table 112, the MMU entry for R V AddrRAM for PID 7 for the PRO_CPU starts at 3968.
• The modified MMU entry is 3968 + 0x4E = 4046.
• Address 0x7F_A375 resides in the 255’th 32 KB-sized page.
• MMU entry 4046 needs to be set to 255 and marked as valid by clearing the 8’th bit. Thus, 0x0FF is written
to MMU entry 4046.
Example 2. An APP_CPU process, with a PID of 5, needs to read or write external RAM address 0x55_5805 up
to 0x55_5823 starting at virtual address 0x3F85_5805. The MMU is in Even-Odd mode.
• According to Table 103, virtual address 0x3F85_5805 resides in the 0x0A’th 32-KB-page of V AddrRAM .
• According to Table 111, the range to be read/written spans both a 32-byte region in R V AddrRAM and
L
V AddrRAM .
• According to Table 112, the MMU entry for L V AddrRAM for PID 5 starts at 1664.
• According to Table 112, the MMU entry for R V AddrRAM for PID 5 starts at 3712.
• The modified MMU entries are 1664 + 0x0A = 1674 and 3712 + 0x0A = 3722.
• The addresses 0x55_5805 to 0x55_5823 reside in the 0xAA’th 32 KB-sized page.
• MMU entries 1674 and 3722 need to be set to 0xAA and marked as valid by setting the 8’th bit to 0. Thus,
0x0AA is written to MMU entries 1674 and 3722. This mapping applies to both the PRO_CPU and the
APP_CPU.
Example 3. A PRO_CPU process, with a PID of 1, and an APP_CPU process whose PID is also 1, need to read
or write external RAM using virtual address 0x3F80_0876. The PRO_CPU needs this region to access physical
address 0x10_0876, while the APP_CPU wants to access physical address 0x20_0876 through this virtual
address. The MMU is in Normal mode.
• According to Table 103, virtual address 0x3F80_0876 resides in the 0’th 32-KB-page of V AddrRAM .
• According to Table 112, the MMU entry for PID 1 for the PRO_CPU starts at 1152.
• According to Table 112, the MMU entry for PID 1 for the APP_CPU starts at 3200.
• The MMU entries that are modified are 1152 + 0 = 1152 for the PRO_CPU and 3200 + 0 = 3200 for the
APP_CPU.
• Address 0x10_0876 resides in the 0x20’th 32 KB-sized page.
• Address 0x20_0876 resides in the 0x40’th 32 KB-sized page.
• For the PRO_CPU, MMU entry 1152 needs to be set to 0x20 and marked as valid by clearing the 8’th bit.
Thus, 0x020 is written to MMU entry 1152.
• For the APP_CPU, MMU entry 3200 needs to be set to 0x40 and marked as valid by clearing the 8’th bit.
Thus, 0x040 is written to MMU entry 3200.
• Now, the PRO_CPU and the APP_CPU can access different physical memory regions through the same
virtual address.
26.3.2.3 Peripheral
The Peripheral MPU manages the 41 peripheral modules. This MMU can be configured per peripheral to only
allow access from a process with a certain PID. The registers to configure this are detailed in Table 113.
Authority
Peripheral
PID = 0/1 PID = 2 ~ 7
DPort Register Access Forbidden
AES Accelerator Access Forbidden
RSA Accelerator Access Forbidden
SHA Accelerator Access Forbidden
Secure Boot Access Forbidden
Cache MMU Table Access Forbidden
PID Controller Access Forbidden
UART0 Access DPORT_AHBLITE_MPU_TABLE_UART_REG
SPI1 Access DPORT_AHBLITE_MPU_TABLE_SPI1_REG
SPI0 Access DPORT_AHBLITE_MPU_TABLE_SPI0_REG
GPIO Access DPORT_AHBLITE_MPU_TABLE_GPIO_REG
RTC Access DPORT_AHBLITE_MPU_TABLE_RTC_REG
IO MUX Access DPORT_AHBLITE_MPU_TABLE_IO_MUX_REG
SDIO Slave Access DPORT_AHBLITE_MPU_TABLE_HINF_REG
UDMA1 Access DPORT_AHBLITE_MPU_TABLE_UHCI1_REG
I2S0 Access DPORT_AHBLITE_MPU_TABLE_I2S0_REG
UART1 Access DPORT_AHBLITE_MPU_TABLE_UART1_REG
I2C0 Access DPORT_AHBLITE_MPU_TABLE_I2C_EXT0_REG
UDMA0 Access DPORT_AHBLITE_MPU_TABLE_UHCI0_REG
SDIO Slave Access DPORT_AHBLITE_MPU_TABLE_SLCHOST_REG
RMT Access DPORT_AHBLITE_MPU_TABLE_RMT_REG
PCNT Access DPORT_AHBLITE_MPU_TABLE_PCNT_REG
SDIO Slave Access DPORT_AHBLITE_MPU_TABLE_SLC_REG
LED PWM Access DPORT_AHBLITE_MPU_TABLE_LEDC_REG
Efuse Controller Access DPORT_AHBLITE_MPU_TABLE_EFUSE_REG
Flash Encryption Access DPORT_AHBLITE_MPU_TABLE_SPI_ENCRYPT_REG
PWM0 Access DPORT_AHBLITE_MPU_TABLE_PWM0_REG
TIMG0 Access DPORT_AHBLITE_MPU_TABLE_TIMERGROUP_REG
TIMG1 Access DPORT_AHBLITE_MPU_TABLE_TIMERGROUP1_REG
Authority
Peripheral
PID = 0/1 PID = 2 ~ 7
SPI2 Access DPORT_AHBLITE_MPU_TABLE_SPI2_REG
SPI3 Access DPORT_AHBLITE_MPU_TABLE_SPI3_REG
SYSCON Access DPORT_AHBLITE_MPU_TABLE_APB_CTRL_REG
I2C1 Access DPORT_AHBLITE_MPU_TABLE_I2C_EXT1_REG
SDMMC Access DPORT_AHBLITE_MPU_TABLE_SDIO_HOST_REG
EMAC Access DPORT_AHBLITE_MPU_TABLE_EMAC_REG
PWM1 Access DPORT_AHBLITE_MPU_TABLE_PWM1_REG
I2S1 Access DPORT_AHBLITE_MPU_TABLE_I2S1_REG
UART2 Access DPORT_AHBLITE_MPU_TABLE_UART2_REG
PWM2 Access DPORT_AHBLITE_MPU_TABLE_PWM2_REG
PWM3 Access DPORT_AHBLITE_MPU_TABLE_PWM3_REG
RNG Access DPORT_AHBLITE_MPU_TABLE_PWR_REG
Each bit of register DPORT_AHBLITE_MPU_TABLE_X_REG determines whether each process can access the
peripherals managed by the register. For details please see Table 114. When a bit of register
DPORT_AHBLITE_MPU_TABLE_X_REG is 1, it means that a process with the corresponding PID can access the
corresponding peripheral of the register. Otherwise, the process cannot access the corresponding
peripheral.
PID 234567
DPORT_AHBLITE_MPU_TABLE_X_REG bit 012345
All the DPORT_AHBLITE_MPU_TABLE_X_REG registers are in peripheral DPort Register. Only processes with
PID 0/1 can modify these registers.
27.1 Overview
The ESP32 is a dual core device and is capable of running and managing multiple processes. The PID Controller
supports switching of PID when a process switch occurs. In addition to PID management, the PID Controller also
facilitates management of nested interrupts by recording execution status just before an interrupt service routine
is executed. This enables the user application to manage process switches and nested interrupts more
efficiently.
27.2 Features
The PID Controller features:
• An interrupt occurs and the CPU fetches an instruction from the interrupt vector. Instruction fetch or
execution from interrupt vector is always treated as a process with PID of 0, irrespective of which process
was being executed on the CPU when the interrupt occurred.
• A currently active process explicitly performs a process switch. Only elevated processes with PID of 0 or 1
may perform a process switch.
PIDCTRL_INTERRUPT_ENABLE_REG determines whether the PID Controller identifies and registers an interrupt
of certain priority. When a bit of register PIDCTRL_INTERRUPT_ENABLE_REG is 1, PID Controller will take action
when CPU fetches instruction from the interrupt vector entry address of the corresponding interrupt. Otherwise,
PID Controller performs no action. The registers PIDCTRL_INTERRUPT_ADDR_1_REG ~
PIDCTRL_INTERRUPT_ADDR_7_REG define the interrupt vector entry address for all the interrupt priority levels.
For details please refer to Table 115.
PIDCTRL_INTERRUPT_ENABLE_REG bit
Priority level Interrupt vector entry address
controlling interrupt identification
Level 1 1 PIDCTRL_INTERRUPT_ADDR_1_REG
Level 2 2 PIDCTRL_INTERRUPT_ADDR_2_REG
Level 3 3 PIDCTRL_INTERRUPT_ADDR_3_REG
Level 4 4 PIDCTRL_INTERRUPT_ADDR_4_REG
Level 5 5 PIDCTRL_INTERRUPT_ADDR_5_REG
Level 6 ( Debug ) 6 PIDCTRL_INTERRUPT_ADDR_6_REG
NMI 7 PIDCTRL_INTERRUPT_ADDR_7_REG
PID Controller records the priority level of the current interrupt in register PIDCTRL_LEVEL_REG. For details
please refer to Table 116.
PID Controller also records in register PIDCTRL_FROM_n_REG the status of the system before the interrupt
occurred. The bit width of register PIDCTRL_FROM_n_REG is 7. The highest four bits represent the interrupt
status of the system before the interrupt indicated by the register occurred. The lowest three bits represent the
process running on the CPU before the interrupt indicated by the register occurred. For details please refer to
Table 117.
Level 2 interrupt
occurs. PID = 0
PIDCTRL_LEVEL_REG = 2
PIDCTRL_FROM_1_REG = XXXX XXX
PIDCTRL_FROM_2_REG = 0000 100
PIDCTRL_FROM_3_REG = XXXX XXX
PIDCTRL_FROM_4_REG = XXXX XXX
PIDCTRL_FROM_5_REG = XXXX XXX
PIDCTRL_FROM_6_REG = XXXX XXX
PIDCTRL_FROM_7_REG = XXXX XXX
Level 5 interrupt
occurs. PID = 0
PIDCTRL_LEVEL_REG = 5
PIDCTRL_FROM_1_REG = XXXX XXX
PIDCTRL_FROM_2_REG = 0000 100
PIDCTRL_FROM_3_REG = XXXX XXX
PIDCTRL_FROM_4_REG = XXXX XXX
PIDCTRL_FROM_5_REG = 0010 000
PIDCTRL_FROM_6_REG = XXXX XXX
PIDCTRL_FROM_7_REG = XXXX XXX
PID = 0
NMI interrupt PIDCTRL_LEVEL_REG = 7
occurs.
PIDCTRL_FROM_1_REG = XXXX XXX
PIDCTRL_FROM_2_REG = 0000 100
PIDCTRL_FROM_3_REG = XXXX XXX
PIDCTRL_FROM_4_REG = XXXX XXX
PIDCTRL_FROM_5_REG = 0010 000
PIDCTRL_FROM_6_REG = XXXX XXX
PIDCTRL_FROM_7_REG = 0101 000
when the last command of the current process switches to the first command of the new process, PID should
switch from 0/1 to that of the new process.
Though we can deal with interrupt nesting, an elevated process should not be interrupted during the process
switching, and therefore the interrupts have been masked in step 1 and step 2.
In step 4, the configured value of register PIDCTRL_PID_NEW_REG will be the new PID after step 6.
If the system is currently in a nested interrupt and needs to revert to the previous interrupt, register
PIDCTRL_LEVEL_REG must be restored based on the information recorded in register PIDCTRL_FROM_n_REG
in step 5.
In step 7, other tasks can be implemented as well. To do this, the cost of those tasks should be included when
configuring registers PIDCTRL_PID_DELAY_REG and PIDCTRL_NMI_DELAY_REG in step 3.
27.5 Registers
LE
B
NA
_E
PT
RU
ER
T
IN
L_
)
)
ed
ed
TR
rv
rv
DC
se
se
(re
(re
PI
31 8 7 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PIDCTRL_INTERRUPT_ENABLE These bits are used to enable interrupt identification and process-
ing. (R/W)
31 0
0x040000340 Reset
31 0
0x040000180 Reset
31 0
0x0400001C0 Reset
31 0
0x040000200 Reset
31 0
0x040000240 Reset
31 0
0x040000280 Reset
31 0
0x0400002C0 Reset
Y
LA
DE
D_
PI
L_
d)
TR
ve
r
DC
se
(re
PI
31 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 Reset
TR
rv
DC
se
(re
PI
31 12 11 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 Reset
PIDCTRL_NMI_DELAY Delay for disabling CPU NMI interrupt mask signal. (R/W)
US
AT
_ ST
E NT
RR
CU
L_
)
ed
TR
rv
DC
se
(re
PI
31 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
n
S_
TU
TA
_S
US
IO
EV
PR
L_
d)
TR
rve
DC
se
(re
PI
31 7 6 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
W
NE
D_
PI
L_
d)
TR
e
rv
DC
se
(re
PI
31 3 2 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
M
IR
NF
O
_C
ID
P
L_
d)
TR
ve
r
DC
se
(re
PI
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LE
AB
EN
K_
AS
M
I_
M
N
L_
d)
TR
e
rv
DC
se
(re
PI
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PIDCTRL_NMI_MASK_ENABLE This bit is used to enable CPU NMI interrupt mask signal. (WO)
E
BL
SA
DI
K_
AS
M
I_
MN
L_
d)
TR
e
rv
DC
se
(re
PI
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
PIDCTRL_NMI_MASK_DISABLE This bit is used to disable CPU NMI interrupt mask signal. (WO)
28.1 Introduction
ESP32 has three types of built-in sensors for various applications: a capacitive touch sensor with up to 10 inputs,
and a Hall effect sensor.
The processing of analog signals is done by two successive approximation ADCs (SAR ADC). There are five
controllers dedicated to operating ADCs. This provides flexibility when it comes to converting analog inputs in
both high-performance and low-power modes, with minimum processor overhead.
ESP32 is also capable of generating analog signals, using two independent DACs and a cosine waveform
generator.
28.2.2 Features
• Up to 10 capacitive touch pads / GPIOs
• The sensing pads can be arranged in different combinations, so that a larger area or more points can be
detected.
• The touch pad sensing process is under the control of a hardware-implemented finite-state machine (FSM)
which is initiated by software or a dedicated hardware timer.
– CPU waiting in deep sleep and saving power until touch detection and subsequent wake up
The capacitance of a touch pad is periodically charged and discharged. The chart ”Pad Voltage” shows the
charge/discharge voltage that swings from DREFH (reference voltage high) to DREFL (reference voltage low).
During each swing, the touch sensor generates an output pulse, shown in the chart as ”OUT”. The swing slope is
different when the pad is touched (high capacitance) and when it is not (low capacitance). By comparing the
difference between the output pulse counts during the same time interval, we can conclude whether the touch
pad has been touched. TIE_OPT is used to establish the initial voltage level that starts the charge/discharge
cycle.
The Touch FSM can be active in sleep mode. The SENS_SAR_TOUCH_SLEEP_CYCLES register can be
used to set the cycles. The sensor is operated by FAST_CLK, which normally runs at 8 MHz. More
information on that can be found in chapter Reset and Clock.
The SAR ADC controllers have specialized uses. Two of them support high-performance multiple-channel
scanning. Another two are used for low-power operation during deep sleep, and the last one is dedicated to
PWDET / PKDET (power and peak detection). A diagram of the SAR ADCs is shown in Figure 131.
28.3.2 Features
• Two SAR ADCs, with simultaneous sampling and conversion
• Up to five SAR ADC controllers for different purposes (e.g. high performance, low power or PWDET /
PKDET).
• One channel for internal voltage vdd33, two for pa_pkdet (available on selected controllers)
A summary of all the analog signals that may be sent to the SAR ADC module for processing by either ADC1 or
ADC2 is presented in Table 120.
There are five ADC controllers in ESP32: RTC ADC1 CTRL, RTC ADC2 CTRL, DIG ADC1 CTRL, DIG ADC2
CTRL and PWDET CTRL. The differences between them are summarized in Table 121.
The outline of a single controller’s function is shown in Figure 133. For each controller, the start of
analog-to-digital conversion can be triggered by register SENS_SAR_MEASn_START_SAR. The measurement’s
result can be obtained from register SENS_SAR_MEASn_DATA_SAR.
The controllers are intertwined with the ULP coprocessor, as the ULP coprocessor has a built-in instruction to
start an ADC measurement. In many cases, the controllers need to cooperate with the ULP coprocessor,
e.g.:
• when periodically monitoring a channel during deep sleep, where the ULP coprocessor is the only trigger
source during this mode;
• when scanning channels continuously in a sequence. Continuous scanning or DMA is not supported by
the controllers. However, it is possible with the help of the ULP coprocessor.
• High performance; the clock is much faster, therefore, the sample rate is highly increased.
• Multiple-channel scanning mode; there is a pattern table that defines the measurement rule for each SAR
ADC. The scanning mode can be configured as a single mode, double mode, or alternate mode.
Note:
We do not use the term “start of conversion” in this section, because there is no direct access to starting a single SAR
analog-to-digital conversion. We use “start of scan” instead, which implies that we expect to scan a sequence of channels
with DIG ADC controllers.
The pattern tables contain the measurement rules mentioned above. Each table has 16 items which store
information on channel selection, resolution and attenuation. When scanning starts, the controller reads
measurement rules one-by-one from a pattern table. For each controller the scanning sequence includes 16
different rules at most, before repeating itself.
The 8-bit item (the pattern table register) is composed of three fields that contain channel, resolution and
attenuation information, as shown in Table 122.
There are three scanning modes: single mode, double mode and alternate mode.
• Single mode: channels of either SAR ADC1 or SAR ADC2 will be scanned.
• Double mode: channels of SAR ADC1 and SAR ADC2 will be scanned simultaneously.
• Alternate mode: channels of SAR ADC1 and SAR ADC2 will be scanned alternately.
ESP32 supports up to a 12-bit SAR ADC resolution. The 16-bit data in DMA is composed of the ADC result and
some necessary information related to the scanning mode:
• For double mode or alternate mode, 4-bit information on channel selection is added plus one extra bit
indicating which SAR ADC was selected.
For each scanning mode there is a corresponding data format, called Type I and Type II. Both data formats are
described in Tables 123 and 124.
For Type I the resolution of SAR ADC is up to 12 bits, while for Type II the resolution is 11 bits at most.
DIG SAR ADC Controllers allow the use of I2S for direct memory access. The WS signal of I2S acts as a
measurement-trigger signal. The DATA signal provides the information that the measurement result is ready.
Software can configure APB_SARADC_DATA_TO_I2S, in order to connect ADC to I2S.
Inside of ESP32 there is a Hall sensor for magnetic field-sensing applications, which is designed to feed voltage
signals to the SAR ADC. It can be controlled by the ULP coprocessor, when low-power operation is required.
Such functionality, which enhances the power-processing and flexibility of ESP32, makes it an attractive solution
for position sensing, proximity detection, speed measurement, etc.
28.4.2 Features
• Built-in Hall element
• Capable of outputting both analog voltage and digital signals related to the strength of the magnetic field
• Powerful and easy-to-implement functionality, due to its integration with built-in ULP coprocessor, GPIOs,
CPU, Wi-Fi, etc.
The configuration of a Hall sensor for reading is done with registers SENS_SAR_TOUCH_CTRL1_REG and
RTCIO_HALL_SENS_REG, which are used to power up the Hall sensor. The subsequent processing is done by
SAR ADC1. The result is obtained from the RTC ADC1 controller. For more details, please refer to section
28.3.
28.5 DAC
28.5.1 Introduction
Two 8-bit DAC channels can be used to convert digital values into analog output signals (up to two of them). The
design structure is composed of integrated resistor strings and a buffer. This dual DAC supports power supply
and uses it as input voltage reference. The dual DAC also supports independent or simultaneous signal
conversions inside of its channels.
28.5.2 Features
The features of DAC are as follows:
• DMA capability
• Start of conversion can be triggered by software or SAR ADC FSM (please refer to the SAR ADC chapter
for more details)
A diagram showing the DAC channel’s function is presented in Figure 136. For a detailed description, see the
sections below.
28.5.3 Structure
The two 8-bit DAC channels can be configured independently. For each DAC channel, the output analog voltage
can be calculated as follows:
The start of conversion is determined by register RTCIO_PAD_PDACn_XPD_DAC. The conversion process itself
is controlled by software or SAR ADC FSM; see Figure 136.
• Adjustable frequency
The frequency of CW can be adjusted by register SENS_SAR_SW_FSTEP[15:0]:
• Scaling
Configuring register SENS_SAR_DAC_SCALEn[1:0]; the amplitude of a CW can be multiplied by 1, 1/2, 1/4
or 1/8.
• DC offset
The offset may be introduced by register SENS_SAR_DAC_DCn[7:0]. The result will be saturated.
• Phase shift
A phase-shift of 0 / 90 / 180 / 270 degrees can be added by setting register SENS_SAR_DAC_INVn[1:0].
28.6.1 Sensors
28.7 Registers
28.7.1 Sensors
E
CL
T
CY
E
BI
RC
G NV
E_
E_
V
O
DI
PL
PL
DI _I
_F
_
1_ ATA
AM
AM
LK
_C
AR D
_S
_S
_S R1_
R1
R1
R1
NS SA
SA
SA
SA
)
)
ed
ed
SE _
_
rv
rv
NS
NS
NS
NS
se
se
SE
SE
SE
SE
(re
(re
31 29 28 27 26 18 17 16 15 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 9 2 Reset
SENS_SAR1_DIG_FORCE 1: SAR ADC1 controlled by DIG ADC1 CTR, 0: SAR ADC1 controlled by
RTC ADC1 CTRL. (R/W)
SENS_SAR1_SAMPLE_BIT Bit width of SAR ADC1, 00: for 9-bit, 01: for 10-bit, 10: for 11-bit, 11:
for 12-bit. (R/W)
31 0
200 Reset
P
TO
T_
AR
E_ P
ST
RC TO
CT
TH
TH
FO T_
_C
T
ID
ID
P_ AR
2_ TES
T
W
DE
2_ OP
_C ST
T_
T_
O
_
PW
EN
LP P_
AR ST
ST
BI
BI
T
_U P_C
_S R1_
NI
2_
2_
1_
_I
AR
AR
AR
AR
C
NS SA
NS UL
)
SE S_ )
ed
N d
_P
_S
_S
_S
_S
SE rve
SE S_
rv
NS
NS
NS
NS
NS
se
se
N
SE
SE
SE
SE
SE
SE
(re
(re
31 24 23 22 21 11 10 9 8 7 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Reset
SENS_SAR2_BIT_WIDTH Bit width of SAR ADC2, 00: 9 bits, 01: 10 bits, 10: 11 bits, 11: 12 bits.
(R/W)
SENS_SAR1_BIT_WIDTH Bit width of SAR ADC1, 00: 9 bits, 01: 10 bits, 10: 11 bits, 11: 12 bits.
(R/W)
31 0
0x0FFFFFFFF Reset
SENS_SAR_ATTEN1_REG 2-bit attenuation for each pad, 11: 1 dB, 10: 6 dB, 01: 3 dB, 00: 0 dB,
[1:0] is used for ADC1_CH0, [3:2] is used for ADC1_CH1, etc. (R/W)
31 0
0x0FFFFFFFF Reset
SENS_SAR_ATTEN2_REG 2-bit attenuation for each pad, 11: 1 dB, 10: 6 dB, 01: 3 dB, 00: 0 dB,
[1:0] is used for ADC2_CH0, [3:2] is used for ADC2_CH1, etc (R/W)
NE A E
E
O _S C
RC
_D RT OR
_S R
AR
AR
O
S1 TA T_F
_F
_S
D
EA 1_S AR
A
PA
PA
AT
_M AS ST
N_
N_
_D
NS ME 1_
E
_E
S1
1_
SE _ AS
R1
EA
AR
NS ME
SA
M
_S
SE S_
_
NS
NS
NS
N
SE
SE
SE
SE
31 30 19 18 17 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_SAR1_EN_PAD_FORCE 1: SAR ADC1 pad enable bitmap is controlled by SW, 0: SAR ADC1
pad enable bitmap is controlled by ULP coprocessor. (R/W)
SENS_SAR1_EN_PAD SAR ADC1 pad enable bitmap; active only when reg_sar1_en_pad_force =
1. (R/W)
SENS_MEAS1_START_FORCE 1: SAR ADC1 controller (in RTC) is started by SW, 0: SAR ADC1
controller is started by ULP coprocessor. (R/W)
SENS_MEAS1_START_SAR SAR ADC1 controller (in RTC) starts conversion; active only when
reg_meas1_start_force = 1. (R/W)
AY
H_ UT CE E
UC O R C
L
T
O H_ FO OR
DE
UT EN
EL
AI
W
_T UC LL_ _F
S_
_S
O _1
D_
NS TO HA SE
EA
XP
SE S_ D_ HA
M
H_
H_
N XP _P
UC
UC
SE S_ LL
N HA
TO
)
ed
_T
SE S_
_
rv
NS
NS
se
N
SE
SE
SE
(re
31 28 27 26 25 24 23 16 15 0
SENS_TOUCH_OUT_SEL 1: the touch pad is considered touched when the value of the counter is
greater than the threshold, 0: the touch pad is considered touched when the value of the counter
is less than the threshold. (R/W)
SENS_TOUCH_XPD_WAIT The waiting time (in 8 MHz cycles) between TOUCH_START and
TOUCH_XPD. (R/W)
H1
H
_T
_T
UT
UT
O
O
H_
H_
UC
UC
O
O
_T
_T
NS
NS
SE
SE
31 16 15 0
H2
H3
_T
_T
UT
UT
O
O
H_
H_
UC
UC
TO
TO
_
_
NS
NS
SE
SE
31 16 15 0
H5
_T
_T
UT
UT
O
O
H_
H_
UC
UC
O
O
_T
_T
NS
NS
SE
SE
31 16 15 0
H7
_T
_T
UT
UT
O
O
H_
H_
UC
UC
O
O
_T
_T
NS
NS
SE
SE
31 16 15 0
H8
H9
_T
_T
UT
UT
O
O
H_
H_
UC
UC
TO
TO
_
_
NS
NS
SE
SE
31 16 15 0
1
UT
UT
O
O
S_
S_
EA
EA
M
M
H_
H_
UC
UC
O
O
_T
_T
NS
NS
SE
SE
31 16 15 0
3
UT
UT
O
O
S_
S_
EA
EA
M
M
H_
H_
UC
UC
O
O
_T
_T
NS
NS
SE
SE
31 16 15 0
5
UT
UT
O
O
S_
S_
EA
EA
M
M
H_
H_
UC
UC
O
TO
_T
_
NS
NS
SE
SE
31 16 15 0
7
UT
UT
O
O
S_
S_
EA
EA
M
M
H_
H_
UC
UC
O
O
_T
_T
NS
NS
SE
31 16 15 SE 0
9
UT
UT
O
O
S_
S_
EA
EA
M
M
H_
H_
UC
UC
O
O
_T
_T
NS
NS
SE
SE
31 16 15 0
NE N
ES
R
H_ TAR _EN CE
DO _E
CL
CL
S_ SM
UC S T R
N_
CY
O H_ AR FO
EN
EA F
_E
P_
_T UC ST T_
M T_
S_
S
NS TO H_ AR
EE
EA
EA
SE S_ UC _ST
L
M
M
_S
H_
H_
H
N TO H
UC
UC
SE _ UC
UC
O
NS TO
O
NS d)
_T
_T
_T
SE rve
SE S_
NS
NS
se
N
SE
SE
SE
(re
31 30 29 14 13 12 11 10 9 0
SENS_TOUCH_START_FORCE 1: starts the Touch FSM via software; 0: starts the Touch FSM via
timer. (R/W)
SENS_TOUCH_START_EN 1: starts the Touch FSM; this is valid when reg_touch_start_force is set.
(R/W)
EN
1
2
EN
EN
RK
UT
UT
O
_W
_O
_O
D
D
PA
PA
PA
H_
H_
H_
UC
UC
UC
O
O
d)
_T
_T
_T
e
rv
NS
NS
NS
se
SE
SE
SE
(re
31 30 29 20 19 10 9 0
SENS_TOUCH_PAD_OUTEN1 Bitmap defining SET1 for generating a wakeup interrupt; SET1 is con-
sidered touched if at least one of the touch pads in SET1 is touched. (R/W)
SENS_TOUCH_PAD_OUTEN2 Bitmap defining SET2 for generating a wakeup interrupt; SET2 is con-
sidered touched if at least one of the touch pads in SET2 is touched. (R/W)
E
CL
T
CY
E
BI
RC
G NV
E_
E_
V
O
DI
PL
PL
DI _I
_F
_
2_ ATA
AM
LK
A
_C
AR D
_S
_S
_S R2_
R2
R2
R2
NS SA
SA
SA
SA
)
)
ed
ed
SE _
_
rv
rv
NS
NS
NS
NS
se
se
SE
SE
SE
SE
(re
(re
31 30 29 28 27 18 17 16 15 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 9 2 Reset
SENS_SAR2_DIG_FORCE 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL, 0: SAR
ADC2 controlled by RTC ADC2 CTRL (R/W)
SENS_SAR2_SAMPLE_BIT Bit width of SAR ADC2, 00: for 9-bit, 01: for 10-bit, 10: for 11-bit, 11:
for 12-bit. (R/W)
O _S C
RC
_D RT OR
_S R
AR
R
O
SA
S2 TA T_F
_F
AD
A_
EA 2_S AR
PA
AT
_P
_M AS ST
N_
_D
EN
NS ME 2_
_E
S2
2_
SE _ AS
R2
EA
AR
NS ME
A
_M
_S
_S
SE S_
NS
NS
NS
N
SE
SE
SE
SE
31 30 19 18 17 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_SAR2_EN_PAD_FORCE 1: SAR ADC2 pad enable bitmap is controlled by SW, 0: SAR ADC2
pad enable bitmap is controlled by ULP coprocessor. (R/W)
SENS_SAR2_EN_PAD SAR ADC2 pad enable bitmap; active only when reg_sar2_en_pad_force =
1. (R/W)
SENS_MEAS2_START_FORCE 1: SAR ADC2 controller (in RTC) is started by SW, 0: SAR ADC2
controller is started by ULP coprocessor. (R/W)
SENS_MEAS2_START_SAR SAR ADC2 controller (in RTC) starts conversion; active only when
reg_meas2_start_force = 1. (R/W)
O E_ GH
E OW
_F C HI
RC L
IG OR E_
_D K_F RC
_D C_ K_ V
N
AC CL FO
NS DA CL IN
_E
P
SE S_ C_ LK_
NE
TE
O
N DA C
S
_T
_F
SE S_ C_
SW
N DA
d)
)
ed
_S
ve
SE S_
_
rv
NS
NS
er
se
N
s
SE
SE
SE
(re
(re
31 26 25 24 23 22 21 17 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_DAC_DIG_FORCE 1: DAC1 & DAC2 use DMA, 0: DAC1 & DAC2 do not use DMA. (R/W)
SENS_SW_FSTEP Frequency step for CW generator; can be used to adjust the frequency. (R/W)
NV 1
1
N
LE
LE
AC _E
NS C_ _
CA
CA
C1
SE DA _CW
NV
C
_D
_D
_S
_S
_I
_I
_ C
AC
AC
AC
AC
AC
NS DA
)
ed
_D
_D
_D
_D
_D
SE S_
rv
NS
NS
NS
NS
NS
se
N
SE
SE
SE
SE
SE
SE
(re
31 26 25 24 23 22 21 20 19 18 17 16 15 8 7 0
0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_DAC_INV2 DAC2, 00: does not invert any bits, 01: inverts all bits, 10: inverts MSB, 11: inverts
all bits except for MSB. (R/W)
SENS_DAC_INV1 DAC1, 00: does not invert any bits, 01: inverts all bits, 10: inverts MSB, 11: inverts
all bits except for MSB. (R/W)
SENS_DAC_SCALE2 DAC2, 00: no scale, 01: scale to 1/2, 10: scale to 1/4, scale to 1/8. (R/W)
SENS_DAC_SCALE1 DAC1, 00: no scale, 01: scale to 1/2, 10: scale to 1/4, scale to 1/8. (R/W)
_C AR
AR
_P LE
LE
ED
TT _C
EN
1_ TT L
LE
E
L AT
AR PA SE
PA _P
IV
DC ST _M E
_L
RC
DC SA _S I2S
RA C_ R2 OD
T_
SE G
_D
_S R2_ AR_
TT
_S ART UX
DC R_ K_
O
RA C_ TA O_
AT
LK
M
PA
_F
L
P
K_
SA AD DA _T
_C
AP AR _SA _C
2_
1_
RT
B_ AR C_ TA
AP _S AD OR
AR
AR
AR
C R
TA
AP _S AD _DA
B_ AD SA
SA D SA
W
_S
_S
_S
AP AR C_
B_ AR C_
B AR C
DC
DC
DC
AP _S AD
S D
RA
RA
RA
A
B AR
B_ R
B R
)
ed
SA
SA
SA
A
AP _S
AP _S
AP _S
rv
B_
B_
B_
se
B
AP
AP
AP
AP
AP
(re
31 27 26 25 24 23 22 19 18 15 14 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 15 15 4 1 0 0 0 0 0 Reset
APB_SARADC_DATA_TO_I2S 1: I2S input data is from SAR ADC (for DMA), 0: I2S input data is
from GPIO matrix. (R/W)
APB_SARADC_DATA_SAR_SEL 1: sar_sel will be coded by the MSB of the 16-bit output data, in
this case, the resolution should not contain more than 11 bits; 0: using 12-bit SAR ADC resolution.
(R/W)
APB_SARADC_SAR2_PATT_P_CLEAR Clears the pointer of pattern table for DIG ADC2 CTRL.
(R/W)
APB_SARADC_SAR1_PATT_P_CLEAR Clears the pointer of pattern table for DIG ADC1 CTRL.
(R/W)
APB_SARADC_SAR_SEL 0: SAR1, 1: SAR2, this setting is applicable in the single SAR mode. (R/W)
APB_SARADC_SAR2_MUX 1: SAR ADC2 is controlled by DIG ADC2 CTRL, 0: SAR ADC2 is con-
trolled by PWDET CTRL. (R/W)
IT
M
IM
NU
_L
S_
M
EA
NU
1_ V
V
AR IN
IN
_M
S_
_S R2_
EA
AX
DC SA
_M
_M
RA C_
DC
DC
SA AD
RA
RA
B_ AR
)
ed
SA
SA
AP _S
rv
B_
B_
se
B
AP
AP
AP
(re
31 11 10 9 8 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 255 0 Reset
APB_SARADC_SAR2_INV 1: data to DIG ADC2 CTRL is inverted, 0: data is not inverted. (R/W)
APB_SARADC_SAR1_INV 1: data to DIG ADC1 CTRL is inverted, 0: data is not inverted. (R/W)
d)
SA
e
rv
B_
se
AP
(re
31 24 47 24
2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0x00F0F0F0F Reset
APB_SARADC_SAR1_PATT_TAB1_REG Pattern tables 0 - 3 for SAR ADC1, one byte for each
pattern table: [31:28] pattern0_channel, [27:26] pattern0_bit_width, [25:24] pattern0_attenuation,
[23:20] pattern1_channel, etc. (R/W)
31 0
0x00F0F0F0F Reset
APB_SARADC_SAR1_PATT_TAB2_REG Pattern tables 4 - 7 for SAR ADC1, one byte for each
pattern table: [31:28] pattern4_channel, [27:26] pattern4_bit_width, [25:24] pattern4_attenuation,
[23:20] pattern5_channel, etc. (R/W)
31 0
0x00F0F0F0F Reset
APB_SARADC_SAR1_PATT_TAB3_REG Pattern tables 8 - 11 for SAR ADC1, one byte for each
pattern table: [31:28] pattern8_channel, [27:26] pattern8_bit_width, [25:24] pattern8_attenuation,
[23:20] pattern9_channel, etc. (R/W)
31 0
0x00F0F0F0F Reset
31 0
0x00F0F0F0F Reset
APB_SARADC_SAR2_PATT_TAB1_REG Pattern tables 0 - 3 for SAR ADC2, one byte for each
pattern table: [31:28] pattern0_channel, [27:26] pattern0_bit_width, [25:24] pattern0_attenuation,
[23:20] pattern1_channel, etc. (R/W)
31 0
0x00F0F0F0F Reset
APB_SARADC_SAR2_PATT_TAB2_REG Pattern tables 4 - 7 for SAR ADC2, one byte for each
pattern table: [31:28] pattern4_channel, [27:26] pattern4_bit_width, [25:24] pattern4_attenuation,
[23:20] pattern5_channel, etc. (R/W)
31 0
0x00F0F0F0F Reset
APB_SARADC_SAR2_PATT_TAB3_REG Pattern tables 8 - 11 for SAR ADC2, one byte for each
pattern table: [31:28] pattern8_channel, [27:26] pattern8_bit_width, [25:24] pattern8_attenuation,
[23:20] pattern9_channel, etc. (R/W)
31 0
0x00F0F0F0F Reset
29.1 Introduction
The ULP co-processor is an ultra-low-power processor that remains powered on during the Deep-sleep mode of
the main SoC. Hence, the developer can store in the RTC memory a program for the ULP co-processor to
access peripheral devices, internal sensors and RTC registers during deep sleep. This is useful for designing
applications where the CPU needs to be woken up by an external event, or timer, or a combination of these,
while maintaining minimal power consumption.
29.2 Features
• Contains up to 8 KB of SRAM for instructions and data
• Contains four 16-bit general-purpose registers (R0, R1, R2, R3) for manipulating data and accessing
memory
• Includes one 8-bit Stage_cnt register which can be manipulated by ALU and used in JUMP instructions
APB Bus
bridge
TSENS CTRL
ULP
RTC Timer
Coprocessor
SAR CTRL
ESP32 RTC
The ULP co-processor can be started by software or a periodically-triggered timer. The operation of the ULP
co-processor is ended by executing the HALT instruction. Meanwhile, it can access almost every module in RTC
domain, either through built-in instructions or RTC registers. In many cases the ULP co-processor can be a good
supplement to, or replacement of, the CPU, especially for power-sensitive applications. Figure 138 shows the
overall layout of a ULP co-processor.
OpCode Operands
An instruction, which has one OpCode, can perform various different operations, depending on the setting of
Operands bits. A good example is the ALU instruction, which is able to perform 10 arithmetic and logic
operations; or the JUMP instruction, which may be conditional or unconditional, absolute or relative.
Each instruction has a fixed width of 32 bits. A series of instructions can make a program be executed by the
ULP co-processor. The execution flow inside the program uses 32-bit addressing. The program is stored in a
dedicated region called Slow Memory (RTC_SLOW_MEM), which is visible to the main CPUs as one that has an
address range of 0x5000_0000 to 0x5000_1FFF (8 KB).
The OpCode in this chapter is represented by 4’dx, where 4 stands for 4-bit width, ’d is a decimal symbol, x
stands for the value of OpCode (x: 0 ~ 15).
The ALU instruction, which has one OpCode, can perform various different arithmetic and logic operations,
depending on the setting of the instruction’s bits [27:21] accordingly.
31 28 27 25 24 21 5 4 3 2 1 0
When bits [27:25] of the instruction in Figure 140 are set to 3’b0, ALU performs operations, using the ULP
co-processor register R[0-3]. The types of operations depend on the setting of the instruction’s bits [24:21]
presented in Table 127.
Operand Description - see Figure 140
ALU_sel Type of ALU operation
Rdst Register R[0-3], destination
Rsrc1 Register R[0-3], source
Rsrc2 Register R[0-3], source
Note:
• All ALU operations can be used to set/clear the zero flag in ALU.
31 28 27 25 24 21 19 4 3 2 1 0
Figure 141: Instruction Type — ALU for Operations with Immediate Value
When bits [27:25] of the instruction in Figure 141 are set to 3’b1, ALU performs operations, using register R[0-3]
and the immediate value stored in [19:4]. The types of operations depend on the setting of the instruction’s bits
[24:21] presented in Table 128.
Operand Description - see Figure 141
ALU_sel Type of ALU operation
Rdst Register R[0-3], destination
Rsrc1 Register R[0-3], source
Imm 16-bit signed value
Note:
• All ALU operations can be used to set/clear the zero flag in ALU.
31 28 27 25 24 21 11 4
Figure 142: Instruction Type — ALU for Operations with Stage Count Register
ALU is also able to increment/decrement by a given value, or reset the 8-bit register Stage_cnt. To do so, bits
[27:25] of instruction in Figure 142 should be set to 3’b2. The type of operation depends on the setting of the
instruction’s bits [24:21] presented in Table 129. The Stage_cnt is a separate register and is not a part of the
instruction in Figure 142.
Operand Description - see Figure 142
ALU_sel Type of ALU operation
Stage_cnt Stage count register, a separate register [7:0] used to store variables, such as loop index
Imm 8-bit value
Note:
• Data from Rsrc is always stored in the lower 16 bits of a memory word. Differently put, it is not possible to
store Rsrc in the upper 16 bits of memory.
• The ”Mem” written is the RTC_SLOW_MEM memory. Address 0, as seen by the ULP co-processor,
corresponds to address 0x50000000, as seen by the main CPUs.
• In any case, it is always the lower 16 bits of a memory word that are loaded. Differently put, it is not
possible to read the upper 16 bits.
• The ”Mem” loaded is the RTC_SLOW_MEM memory. Address 0, as seen by the ULP co-processor,
corresponds to address 0x50000000, as seen by the main CPUs.
Note:
All jump addresses are expressed in 32-bit words.
Description
The instruction prompts a jump to a relative address, if the above-mentioned condition is true. The condition itself
is the result of comparing the R0 register value and the Threshold value.
Note:
All jump addresses are expressed in 32-bit words.
29.4.6 JUMPS – Jump to a Relative Address (Conditional upon Stage Count Regis-
ter)
31 28 27 25 24 17 16 15 7 0
• A description of how to set the stage count register is provided in section 29.4.1.3.
Description
The instruction prompts a jump to a relative address if the above-mentioned condition is true. The condition itself
is the result of comparing the value of Stage_cnt (stage count register) and the Threshold value.
4’d11
Description
The instruction ends the operation of the processor and puts it into power-down mode.
Note:
After executing this instruction, the ULP co-processor timer gets started.
31 28 27 25 0
1’b1
4’d9 3’b0
• If the SoC is in Deep-sleep mode, and the ULP wake-up is enabled, the above-mentioned interrupt will
wake up the SoC.
• If the SoC is not in Deep-sleep mode, and the ULP interrupt bit (RTC_CNTL_ULP_CP_INT_ENA) is set in
register RTC_CNTL_INT_ENA_REG, a RTC interrupt will be triggered.
4’d4 Cycles
Description
The instruction prompts the taking of measurements with the use of ADC. Pads/signals available for ADC
measurement are provided in Table 131.
Description
Communicate (read/write) with external I²C slave devices. Details on using the RTC I²C peripheral are provided in
section 29.6.
Note:
When working in master mode, RTC_I2C samples the SDA input on the negative edge of SCL.
R0 = REG[Addr][High:Low]
In case of more than 16 bits being requested, i.e. High - Low + 1 > 16, then the instruction will return
[Low+15:Low].
Note:
• This instruction can access registers in RTC_CNTL, RTC_IO, SENS and RTC_I2C peripherals. The address
of the register, as seen from the ULP co-processor, can be calculated from the address of the same register
on the DPORT bus, as follows:
addr_ulp = (addr_dport - DR_REG_RTCCNTL_BASE)/4
• The addr_ulp is expressed in 32-bit words (not in bytes), and value 0 maps onto the
DR_REG_RTCCNTL_BASE (as seen from the main CPUs). Thus, 10 bits of address cover a 4096-byte
range of peripheral register space, including regions DR_REG_RTCCNTL_BASE, DR_REG_RTCIO_BASE,
DR_REG_SENS_BASE and DR_REG_RTC_I2C_BASE.
REG[Addr][High:Low] = Data
If more than 8 bits are requested, i.e. High - Low + 1 > 8, then the instruction will pad with zeros the bits above
the eighth bit.
Note:
See notes regarding addr_ulp in section 29.4.13 above.
In a typical power-saving scenario, the ULP co-processor operates while the main CPUs are in deep sleep. To
save power even further, the ULP co-processor can get into sleep mode, as well. In such a scenario, there is a
specific hardware timer in place to wake up the ULP co-processor, since there is no software program running at
the same time. This timer should be configured in advance by setting and then selecting one of the
SENS_ULP_CP_SLEEP_CYCn_REG registers that contain the expiration period. This can be done either by the
main program, or the ULP program with the REG_WR and SLEEP instructions. Then, the ULP timer should be
enabled by setting bit RTC_CNTL_ULP_CP_SLP_TIMER_EN in the RTC_CNTL_STATE0_REG register.
The ULP co-processor puts itself into sleep mode by executing the HALT instruction. This also triggers the ULP
timer to start counting RTC_SLOW_CLK ticks which, by default, originate from an internal 150 kHz RC oscillator.
Once the timer expires, the ULP co-processor is powered up and runs a program with the program counter (PC)
which is stored in register SENS_PC_INIT. The relationship between the described signals and registers is shown
in Figure 156.
On reset or power-up the above-mentioned ULP program may start up only after the expiration of
SENS_ULP_CP_SLEEP_CYC0_REG, which is the default selection period of the ULP timer.
A sample operation sequence of the ULP program is shown in Figure 157, where the following steps are
executed:
2. The ULP timer expires and the ULP co-processor starts running the program at PC = SENS_PC_INIT.
3. The ULP program executes the HALT instruction; the ULP co-processor is halted and the timer gets
restarted.
4. The ULP program executes the SLEEP instruction to change the sleep timer period register.
5. The ULP program, or software, disables the ULP timer by using bit RTC_CNTL_ULP_CP_SLP_TIMER_EN.
The specific timing of the wakeup, program execution and sleep sequence is governed by the ULP FSM as
follows:
1. On the ULP timer expiration the FSM wakes up the ULP and this process takes two clock cycles.
2. Then, before executing the program, the FSM waits for the number of cycles configured in
RTC_CNTL_ULPCP_TOUCH_START_WAIT field of the RTC_CNTL_TIMER2_REG register. This time is
spent waiting for the 8 MHz clock to get stable.
4. After calling HALT instruction, the program is stopped. The FSM requires additional two clock cycles to put
the ULP to sleep.
1. Set the low and high SCL half-periods by using RTC_I2C_SCL_LOW_PERIOD_REG and
RTC_I2C_SCL_HIGH_PERIOD_REG in RTC_FAST_CLK cycles (e.g. RTC_I2C_SCL_LOW_PERIOD=40,
RTC_I2C_SCL_HIGH_PERIOD=40 for 100 kHz frequency).
2. Set the number of cycles between the SDA switch and the falling edge of SCL by using
RTC_I2C_SDA_DUTY_REG in RTC_FAST_CLK (e.g. RTC_I2C_SDA_DUTY=16).
3. Set the waiting time after the START condition by using RTC_I2C_SCL_START_PERIOD_REG (e.g.
RTC_I2C_SCL_START_PERIOD=30).
4. Set the waiting time before the END condition by using RTC_I2C_SCL_STOP_PERIOD_REG (e.g.
RTC_I2C_SCL_STOP_PERIOD=44).
7. Write the address(es) of external slave(s) to SENS_I2C_SLAVE_ADDRn (n: 0-7). Up to eight slave
addresses can be pre-programmed this way. One of these addresses can then be selected for each
transaction as part of the ULP I²C instruction.
Once RTC_I2C is configured, instructions ULP I2C_RD and I2C_WR can be used.
The I2C_RD instruction performs the following I²C transaction (see Figure 158):
2. Master sends slave address, with r/w bit set to 0 (“write”). Slave address is obtained from
SENS_I2C_SLAVE_ADDRn, where n is given as an argument to the I2C_RD instruction.
4. Master sends slave register address (given as an argument to the I2C_RD instruction).
1 2 3 4 5 6 7 8 9 10
RSTRT
START
NACK
STOP
Master Slave Address W Reg Address Slave Address R
ACK
ACK
Slave Data
Note:
The RTC_I2C peripheral samples the SDA signals on the falling edge of SCL. If the slave changes SDA in less
than 0.38 microseconds, the master will receive incorrect data.
The byte received from the slave is stored into the R0 register.
The I2C_WR instruction performs the following I²C transaction (see Figure 159):
2. Master sends slave address, with r/w bit set to 0 (“write”). Slave address is obtained from
SENS_I2C_SLAVE_ADDRn, where n is given as an argument to the I2C_WR instruction.
4. Master sends slave register address (given as an argument to the I2C_WR instruction).
1 2 3 4 5 6 7 8 9 10
RSTRT
START
STOP
ACK
ACK
Slave
ULP I2C_RD and I2C_WR instructions will not report error conditions, such as a NACK from a slave, via ULP
registers. Instead, applications can query specific bits in the RTC_I2C_INT_ST_REG register to determine if the
transaction was successful. To enable checking for specific communication events, their corresponding bits
should be set in register RTC_I2C_INT_EN_REG. Note that the bit map is shifted by 1. If a specific
communication event is detected and set in register RTC_I2C_INT_ST_REG, it can then be cleared using
RTC_I2C_INT_CLR_REG.
SDA and SCL signals can be mapped onto two out of the four GPIO pins, which are identified in Table RTC_MUX
Pin Summary in Chapter IO_MUX and GPIO Matrix, using the RTCIO_SAR_I2C_IO_REG register.
Note:
Interrupts from RTC_I2C are not connected. The interrupt registers above are listed only for debugging
purposes.
29.8 Registers
29.8.1 SENS_ULP Address Space
31 0
20 Reset
SENS_ULP_CP_SLEEP_CYCn_REG ULP timer cycles setting n; the ULP co-processor can select
one of such registers by using the SLEEP instruction. (R/W)
P
TO
T_
AR
E_ P
ST
RC TO
FO T_
P_ AR
_C ST
LP P_
T
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NI
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ed
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ve
SE rve
rv
NS
r
se
se
se
SE
(re
(re
(re
31 22 21 11 10 9 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
SENS_ULP_CP_START_TOP Set this bit to start the ULP co-processor; it is active only when
SENS_ULP_CP_FORCE_START_TOP = 1. (R/W)
R1
DD
DD
_A
A
E_
VE
AV
LA
L
_S
_S
2C
2C
e d)
_I
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rv
NS
NS
se
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31 22 21 11 10 0
R2
R3
DD
DD
_A
_A
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E
AV
AV
L
L
_S
_S
2C
C
)
ed
I2
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rv
NS
NS
se
SE
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(re
31 22 21 11 10 0
R4
5
DR
DD
D
_A
_A
E
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AV
AV
L
L
_S
_S
2C
2C
ed)
_I
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rv
NS
NS
se
SE
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(re
31 22 21 11 10 0
7
DR
DD
D
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_A
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VE
E
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AT
AV
LA
DO
SL
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C_
2C
2C
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2
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NS
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se
SE
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31 30 29 22 21 11 10 0
E
RC
RT O
TA _F
_S RT
RL
2C TA
CT
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C_
AR 2C
2
_S R_I
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AR
NS SA
d)
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ve
SE _
NS
NS
er
s
SE
SE
(re
31 30 29 28 27 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
D
IO
ER
_P
W
O
_L
CL
_S
)
ed
C
I2
rv
C_
se
RT
(re
31 19 18 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
UT
E_ UT
O
RC _O
(re C_ AN _F ST
DE T
S_ _S ST
O R
FO E
I2 TR SB IR
M TA
M S IR
A_ RC
C_ C_ _L _F
SD _FO
RT _I2 _TX SB
C C _L
C_ L
I2 SC
RT _I2 _RX
C_ C_
d)
RT ed)
C C
ve
RT _I2
RT I2
rv
er
C_
se
C
s
RT
(re
31 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
H
TC
RT _I2 _TIM _LO Y MA
C C B S _
C C S A S
RT _I2 _AR _BU DDR
E
RT I2 BU E_ N
AC E_ T
E
AT
K_ RW
C_ C_ E ST
U
C_ C_ AV RA
AT
L
C_ AV O
ST
VA
ST
I2 SL D_
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RT I2 BY
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C_
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I2
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RT _I2
rv
rv
C_
C_
se
se
C
RT
RT
RT
(re
(re
31 30 28 27 25 24 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_I2C_ARB_LOST Indicates the loss of I²C bus control, when in master mode. (R/W)
RTC_I2C_SLAVE_RW Indicates the value of the received R/W bit, when in slave mode. (R/W)
UT
EO
TIM
C_
)
ed
I2
rv
C_
se
RT
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_I2C_TIMEOUT Maximum number of FAST_CLK cycles that the transmission can take. (R/W)
R
DD
DD
_A
_A
E
VE
AV
LA
SL
_S
C_
d)
C
e
I2
I2
rv
C_
C_
se
RT
RT
(re
31 30 15 14 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
LR
R
ET R T_C
CL
T_
PL CL N
M T_ E_I
IN
S_ ST PL R
E_
CO _IN ET
AN LO OM CL
TR N_ C T_
E_ IO S_ _IN
C_ B _ P R
AV AT AN TE
I2 AR ER M CL
SL ITR TR LE
C_ C_ ST _CO T_
RT _I2 _MA NS T_IN
C C A U
RT _I2 _TR _O
C C E
RT I2 TIM
C_ C_
d)
)
ed
ve
RT _I2
rv
r
se
se
C
RT
(re
(re
31 9 8 7 6 5 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
NA A
_E N
NT _E
ST P_I A
LO M _EN
_I NT
N_ O T
IO _C _IN
BI R_ P NA
AT AN TE
AR TE OM _E
TR TR LE
C_ S C T
I2 MA S_ _IN
C_ C_ AN UT
RT _I2 _TR _O
C C E
RT I2 TIM
C_ C_
)
)
ed
ed
RT _I2
rv
rv
se
se
C
RT
(re
(re
31 9 8 7 6 5 4 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
_S T
NT _S
T
LO M _ST
_I NT
ST P_I
N_ O T
IO _C _IN
AT AN TE
BI R_ P T
AR TE OM _S
TR TR LE
C_ S C T
I2 MA S_ _IN
C_ C_ AN UT
RT _I2 _TR _O
C C E
RT _I2 _TIM
d)
)
ed
C C
ve
RT _I2
rv
er
se
C
s
RT
(re
(re
31 8 7 6 5 4 3 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TY
DU
A_
SD
C_
)
ed
I2
rv
C_
se
RT
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_I2C_SDA_DUTY Number of FAST_CLK cycles between the SDA switch and the falling edge of
SCL. (R/W)
I2
rv
C_
se
RT
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
D
O
RI
PE
T_
AR
ST
_
SCL
C_
d)
ve
I2
er
C_
s
RT
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
D
O
RI
PE
P_
TO
_S
CL
_S
d)
C
ve
I2
r
C_
se
RT
(re
31 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
30.1 Introduction
ESP32 offers efficient and flexible power-management technology to achieve the best balance between power
consumption, wakeup latency and available wakeup sources. Users can select out of five predefined power
modes of the main processors to suit specific needs of the application. In addition, to save power in
power-sensitive applications, control may be executed by the Ultra-Low-Power co-processor (ULP
co-processor), while the main processors are in Deep-sleep mode.
30.2 Features
• Five predefined power modes to support various applications
• Up to 16 KB of retention memory
1. When XPD_DIG_REG == 1, the regulator outputs a 1.1V voltage and the digital core is able to run; when
XPD_DIG_REG == 0, both the regulator and the digital core stop running.
3. The current to the digital core comes from pin VDD3P3_CPU and pin VDD3P3_RTC.
90
supports an adjustable output voltage of 0.90V to 1.25V in normal work mode, a fixed output voltage of about
0.75V both in Deep-sleep mode and Hibernation mode.
1. When the pin CHIP_PU is at a high level, the low-power voltage regulator cannot be turned off. It should be
switched only between normal-work mode and Deep-sleep mode.
3. In Deep-sleep mode, the output voltage of the regulator is fixed at about 0.75V.
90
1. When XPD_SDIO_VREG == 1, the regulator outputs a voltage of 3.3V or 1.8V; when XPD_SDIO_VREG ==
0, the output is high-impedance and, in this case, the voltage is provided by the external power supply.
2. When SDIO_TIEH == 1, the regulator shorts pin VDD_SDIO to pin VDD3P3_RTC. The regulator then
outputs a voltage of 3.3V which is the voltage of pin VDD3P3_RTC. When SDIO_TIEH == 0, the inner loop
ties the regulator output to the voltage of VREF, which is typically 1.8V.
3. DREFH_SDIO, DREFM_SDIO and DREFL_SDIO could be used to tune the reference voltage VREF slightly.
However, it is recommended that users do not change the value of these registers, since it may affect the
stability of the inner loop.
4. When the regulator output is 3.3V or 1.8V, the output current comes from the pin VDD3P3_RTC.
1. As the output of the brownout detector, RTC_CNTL_BROWN_OUT_DET goes high when the voltage of pin
VDD3P3_RTC is lower than the threshold value.
• Digital & analog power controller: generates actual power-gating/clock-gating signals for digital parts and
analog parts.
• Sleep & wakeup controller: handles the entry into & exit from the low-power mode.
• Timers: include RTC main timer, ULP co-processor timer and touch timer.
• Low-Power processor and sensor controllers: include ULP co-processor, touch controller, SAR ADC
controller, etc.
• Retention memory:
– RTC slow memory: an 8 KB SRAM, mostly used as retention memory or instruction & data memory
for the ULP co-processor. The CPU accesses it through the APB, starting from address 0x50000000.
– RTC fast memory: an 8 KB SRAM, mostly used as retention memory. The CPU accesses it through
IRAM0/DRAM0. Fast RTC memory is about 10 times faster than the RTC slow memory.
For the RTC core, there are five possible clock sources:
• internal 31.25-kHz clock CK8M_D256_OUT (derived from the internal 8-MHz oscillator divided by 256).
With these clocks, fast_rtc_clk and slow_rtc_clk is derived. By default, fast_rtc_clk is CK8M_OUT while
slow_rtc_clk is SLOW_CK. For details, please see Figure 166.
For the digital core, low_power_clk is switched among four sources. For details, please see Figure 167.
The switch among power-gating states can be see in Figure 168. The actual power-control signals could also be
set by software as force-power-up (FPU) or force-power-down (FPD). Since the power domains can be
power-gated independently, there are many combinations for different applications. Table 135 shows how the
power domains in ESP32 are controlled.
5. When the power-domain digital core is powered down, all included in power domains are powered
down.
6. The power-domain Wi-Fi includes the Wi-Fi MAC and BB.
7. Each internal SRAM can be power-gated independently.
• Active mode
– The CPU is clocked at XTAL_DIV_N (40 MHz/26 MHz) or PLL (80 MHz/160 MHz/240 MHz).
• Modem-sleep mode
– The Wi-Fi/Bluetooth baseband is clock-gated or powered down. The radio is turned off.
– Immediate wake-up.
• Light-sleep mode
– The internal 8 MHz oscillator, 40 MHz high-speed crystal, PLL, and radio are disabled.
– The clock in the digital core is gated. The CPUs are stalled.
– The ULP co-processor and touch controller can be periodically triggered by monitor sensors.
• Deep-sleep mode
– The internal 8 MHz oscillator, 40 MHz high-speed crystal, PLL and radio are disabled.
• Hibernatation mode
– The internal 8 MHz oscillator, 40 MHz high-speed crystal, PLL, and radio are disabled.
– The RTC memory and fast RTC memory are powered down.
By default, the ESP32 is in active mode after a system reset.There are several low-power modes for saving
power when the CPU does not need to be kept running, for example, when waiting for an external event. It is up
to the user to select the mode that best balances power consumption, wake-up latency and available wake-up
sources. For details, please see Figure 169.
Please note that the predefined power mode could be further optimized and adapted to any application.
2. EXT1 is especially designed to wake up the chip from any sleep mode, and it also supports multiple pads’
combinations. First, RTC_CNTL_EXT_WAKEUP1_SEL[17:0] should be configured with the bitmap of PADS
selected as a wake-up source. Then, if RTC_CNTL_EXT_WAKEUP1_LV is 1, as long as one of the PADs is at
high-voltage level, it can trigger a wake-up. However, if RTC_CNTL_EXT_WAKEUP1_LV is 0, it needs all selected
PADs to be at low-voltage level to trigger a wake-up.
3. In Deep-sleep mode, only RTC GPIOs (not DIGITAL GPIOs) can work as wakeup source.
5. To wake up the chip with a Wi-Fi or BT source, the power mode switches between the Active, Modem- and
Light-sleep modes. The CPU, Wi-Fi, Bluetooth, and radio are woken up at predetermined intervals to keep
Wi-Fi/BT connections active.
6. Wake-up is triggered when the number or positive edges of RxD signal is greater than or equal to
(UART_ACTIVE_THRESHOLD+2). Note that the RxD signal cannot be input through GPIO Matrix but only
through IO_MUX.
The RTC timer can be used to wake up the CPU at a designated time, and to wake up TOUCH or the ULP
co-processor periodically.
which remain powered-on in Deep-sleep mode. For small-scale codes (less than 8 KB), there are two methods
of speeding up the wake-up time, i.e. avoiding ROM unpacking and SPI booting.
3. When the CPU is powered up, the reset vector starts from 0x50000000, instead of 0x40000400. ROM
unpacking & SPI boot are not needed. The code in RTC memory has to do itself some initialization for the
C program environment.
2. Calculate CRC for the fast RTC memory, and save the result in register
RTC_CNTL_RTC_STORE6_REG[31:0].
3. Input register RTC_CNTL_RTC_STORE7_REG[31:0] with the entry address in the fast RTC memory.
5. When the CPU is powered up, after ROM unpacking and some necessary initialization, the CRC is
calculated again. If the result matches with register RTC_CNTL_RTC_STORE6_REG[31:0], the CPU will
jump to the entry address.
• The registers listed below have been grouped according to their functionality. This particular grouping does
not reflect the exact sequential order in which they are stored in memory.
• The base address for registers is 0x60008000 when accessed by AHB, and 0x3FF48000 when accessed
by DPORT bus.
30.5 Registers
RS ST
C0
E_ OR
C0
RT _C L_ AS_ C_ _FO CE U
RT _C L_ AS_ C_ RC _8 D
T
RT _C L_ L_ RC _FO EP P
8M
RT NT SW 2C OR RC PU
CN SW RO R _P PD
C NT BI I2 FO E M
C NT BI I2 E R _P
C NT BI I2 FO LW _P
C NT XT FO P LE E
U_
U_
RC _N
RT _C L_ AS_ C_ RC _PU
RT _C L_ AS_ OR LW _PD
RT _C L_ L_ LEE _S SLE
RT _C L_ PL RC _PU W_
C L_ _I F O E_
C_ L_ _P _FO CE E_
RT C L_ S_ R _N M
RT _C L_ AS_ OR _FO CE
TL _A CP CE_ U
_S PP U PD
CP
RT _C L_ PL I2C CE U
RT _C L_ _I2 I2C FO D
CP
FO CE
_S PU RST
C_ NT BIA FO CE _8
_P T
C_ NT BB C_ _F RC
C NT BB FO E L
C NT BB L_ R _P
C NT BB L_ _ _P
C NT BI F FO E
C NT XT S CE O
C NT BI C E R
PP
RT _C L_ PL FO _PD
P_ R
RT _C L_ AS_ OR _FO
_R
RT C L_ PL FO E
R
C _
RA _FO
G RA ST
C_ NT BB L_ RC
_A
C NT BB L_ E
C NT BI C E
_D _W _R
LL
LL
_W P
RT _C L_ AS_ OR
TL G YS
TA
TA
C NT BI C
CN L_D _S
_S
RT C L_ S_
C_ NT SW
W
C_ NT BIA
_S
RT _C L_
RT _C L_
TL
C NT
C NT
)
ed
CN
RT _C
R T _C
rv
C_
se
C
C
RT
RT
RT
(re
31 30 29 28 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_DG_WRAP_FORCE_RST The digital core can force a reset in deep sleep. (R/W)
31 0
0x000000000 Reset
IH
L_
M
TI
VA
N_
P_
AI
L
_M
_S
TL
TL
)
ed
CN
CN
rv
C_
C_
se
RT
RT
(re
31 17 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 Reset
LI E
VA AT
D
E_ D
IM UP
_T E_
TL IM
CN L_T
C_ NT
d)
ve
RT _C
er
C
s
RT
(re
31 30 59 30
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0x000000000 Reset
HI
E_
IM
_T
TL
)
ed
CN
rv
C_
se
RT
(re
31 16 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x00000 Reset
ER N
N
M _E
_E
TI ER
D
P_ IM
IN
SL _T
E_
CT P
H_ LP
DI A T
_A U
IV
_S _W EC
O KE
UC _S
CN L_S P_ EN
TL LP REJ
O P
C_ NT SL P_
_T _C
RT _C L_ EE
TL LP
C NT SL
CN L_U
RT _C L_
C NT
C_ T
)
)
ed
ed
N
R T _C
RT C
rv
rv
C_
se
se
C
RT
RT
(re
(re
31 30 29 28 27 25 24 23 22 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
EN
_
LL
TA
_S
PU
_C
TL
d)
CN
r ve
C_
se
RT
(re
31 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Reset
T
AI
W
T_
FF
AR
_O
ST
M
H_
8
UC
CK
TO
E_
IM
_
CP
_T
P
IN
UL
M
L_
_
TL
NT
)
ed
CN
C
rv
C_
C_
se
RT
RT
(re
31 24 23 15 14 0
L
_ VA
LP
_S
IN
_M
TL
d)
)
ed
CN
e
rv
rv
C_
se
se
RT
(re
(re
31 16 15 8 7 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x080 0 0 0 0 0 0 0 0 Reset
E_ U
PD
O _PU U
RC _P
U
TM C P
_P
FO CE
C d PV _I2 S_
PU
EN U
2C
RT ve L_ F BU
G _P
A_ R
N_
_I
LL FO
C d CK I2C
se NT TX _P
_ P A_
(re C _ X
RT rve L_ L_
R
R
TL LL
C_ NT RF
se NT PL
CN L_P
(re C L_
RT _C L_
L
C_ NT
C NT
C_ NT
RT _C )
R T _C )
)
ed
R T _C
rv
r
se
C
RT
(re
31 30 29 28 27 26 25 24 23 22 0
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
U
U
EC OR
CP
CP
_V T
RO
AT EC
PP
_A
_P
ST T_V
SE
SE
U_ TA
AU
AU
CP _S
_C
_C
PP PU
ET
ET
_A C
TL RO
ES
ES
_R
_R
CN L_P
TL
TL
C_ NT
d)
CN
CN
e
RT _C
rv
C_
C_
se
C
RT
RT
RT
(re
31 14 13 12 11 6 5 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x x x x x x x x x x x x Reset
E R
LT
FI
E
P_
US
A
EU
CA
EN
AK
P_
P_
_W
EU
EU
O
AK
AK
PI
_W
_W
G_
TL
TL
TL
d)
CN
CN
CN
ve
er
C_
C_
C_
s
RT
RT
RT
(re
31 23 22 21 11 10 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0x000 Reset
A
C NT W _V T A NA
IN NA
C NT TI C T NT A
EN
NA
RT _C L_ P_ _IN T_I _EN
RT _C L_ ME P_IN _EN _E
EU INT A
P_ _E
T_
AK T_ EN
TL LP IDL ENA _E
C_ NT SD IN D_ NA
C NT UL H U T
_W EC _
RT _C L_ UC _O _IN
T
RT _C L_ DT_ ALI _E
LP EJ _IN
C NT TO N ER
_S _R E
RT _C L_ OW IM
C NT BR _T
RT _C L_ AIN
C NT M
RT C L_
C_ NT
)
ed
RT _C
rv
se
C
RT
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_WDT_INT_ENA The interrupt enable bit for the RTC_CNTL_WDT_INT interrupt. (R/W)
W
C NT W _V T W AW
IN AW
C NT TI C T NT W
RA
AW
RT _C L_ P_ _IN T_I _RA
EU INT W
RT _C L_ ME P_IN _RA _R
P_ _R
T_
AK T_ RA
TL LP IDL RAW _R
C_ NT SD IN D_ AW
C NT UL H U T
_W EC _
RT _C L_ UC _O _IN
RT _C L_ DT_ ALI _R
T
LP EJ _IN
C NT TO N ER
_S _R E
RT _C L_ OW IM
C NT BR _T
RT _C L_ AIN
C NT M
RT C L_
C_ NT
)
ed
RT _C
rv
se
C
RT
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_TOUCH_INT_RAW The raw interrupt status bit for the RTC_CNTL_TOUCH_INT inter-
rupt. (RO)
RTC_CNTL_ULP_CP_INT_RAW The raw interrupt status bit for the RTC_CNTL_ULP_CP_INT inter-
rupt. (RO)
RTC_CNTL_WDT_INT_RAW The raw interrupt status bit for the RTC_CNTL_WDT_INT interrupt.
(RO)
ST
T
IN T
RT _C L_ R_ _IN T_I _ST
RT _C L_ ME T_S _ST _S
P_ _S
T
T_
AK T_ ST
TL LP IDL ST _S
C NT TI IN T NT
EU INT
C NT SA H U T
_W EC _
RT _C L_ UC _O _IN
T
LP EJ _IN
C_ NT SD IN D_
C NT TO N ER
C NT W _V T
_S _R E
RT _C L_ DT_ ALI
RT _C L_ OW IM
C NT BR _T
RT _C L_ AIN
C NT M
RT C L_
C_ NT
)
ed
RT _C
rv
se
C
RT
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_TOUCH_INT_ST The masked interrupt status bit for the RTC_CNTL_TOUCH_INT inter-
rupt. (RO)
RTC_CNTL_SAR_INT_ST The masked interrupt status bit for the RTC_CNTL_SAR_INT interrupt.
(RO)
RTC_CNTL_WDT_INT_ST The masked interrupt status bit for the RTC_CNTL_WDT_INT interrupt.
(RO)
R
C NT W _V L R LR
IN LR
C NT TI IN T NT R
CL
LR
RT C L_ R_ _IN _I CL
RT _C L_ ME T_C _CL _C
EU INT R
P_ _C
T_
AK T_ CL
TL LP IDL CLR _C
C_ NT SA H UT T_
_W EC _
RT _C L_ UC _O _IN
T
RT _C L_ DT_ ALI R
LP EJ _IN
C_ NT SD IN D_
C NT TO N ER
_S _R E
RT _C L_ OW IM
C NT BR _T
RT _C L_ AIN
C NT M
RT _C L_
C NT
d)
ve
R T _C
r
se
C
RT
(re
31 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
TR N
V
_C _E
_L
XT TR
_E _C
TL XT
_X _E
TL TL
CN L_X
C_ NT
d)
ve
RT _C
er
C
s
RT
(re
31 30 29 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_XTL_EXT_CTR_LV 0: power down XTAL at high level, 1: power down XTAL at low level.
(R/W)
)
ed
RT _C
rv
se
C
RT
(re
31 30 29 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
N
EJ T_ CT N
EC EN _E
_R C E E
O JE EJ T_
PI RE _R C
EN
_G O_ LP JE
SE
T_
TL DI _S _RE
AU
_C
CN L_S HT LP
C_ T IG S
CT
_
RT C L_ EP
JE
C_ NT DE
RE
L
_
RT C _
TL
L
C_ NT
)
ed
CN
N
R T _C
rv
C_
se
C
RT
RT
(re
31 28 27 26 25 24 23 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
L_
CP
SE
_
PU
TC
_C
_R
TL
TL
d )
CN
CN
ver
C_
C_
se
RT
RT
(re
31 30 29 28 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
TL B_C 8M _E _EN
SE EL
C_ _R EL
E_ U
PD
CN EN CK 2K 56
_S
K _D N
S
RC P
CL C_
RT NT EN XTA M_ N
K8 8M IV
C_ L_ B_ L3 D2
CN L_C CL TC
EL
O E_
L
C L_ _ K8 E
EQ
T_ RT
C_ NT DIG L M_
_F C
_S
M OR
FR
TL K8 K_
AS K_
IV
IV
K
RT _C L_ G_C K8
_D
_D
_D
K8 _F
CL
C NT DI L
RT C _ _C
_C M
M
A_
K8
K8
C_ NT DIG
O
CN AN
_C
_C
_C
S
F
C_ L_
C_ L_
C_ L_
RT C L_
TL
TL
L
T
RT NT
C_ NT
C_ T
)
C_ d)
)
ed
ed
CN
CN
CN
N
RT rve
C
RT C
RT C
rv
rv
C_
C_
C_
se
se
se
RT
RT
RT
RT
RT
(re
(re
(re
31 30 29 28 27 26 25 24 17 16 15 14 12 11 10 9 8 7 6 5 4 3 0
0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 Reset
RTC_CNTL_DIG_CLK8M_EN Enable CK8M for digital core (no relation to RTC core). (R/W)
RTC_CNTL_DIG_XTAL32K_EN Enable CK_XTAL_32K for digital core (no relation to RTC core). (R/W)
RTC_CNTL_CK8M_DIV CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11:
div1024. (R/W)
EN
_S EG
D_
_S O_ H DY
_P
FH VR
TL DI TIE EA
O
RE E
O
IO
_V C
G
DI
DI
RE IO_
CN _S IO_ _R
SD
O R
_S
DI FO
C_ NT SD P8
D
L_
M
TL D_S
RT _C L_ G1
F
F
RE
RE
C T E
CN XP
_D
_D
_D
R
C_ L_
RT C L_
TL
TL
L
RT NT
C_ T
)
ed
CN
CN
N
N
C
R T _C
rv
C_
C_
C_
se
C
RT
RT
RT
RT
(re
31 30 29 28 27 26 25 24 23 22 21 20 0
0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
AK
L P
E_ U
PD
_S
RC P
S_
O E_
BO ST CE U
ST R D
AS
_D O R _P
O _FO _P
A
_F C
BI
BI
TL BO _FO CE
_D
_D
AK
LP
P
CN L_D EG OR
G
A
_W
RE
RE
_S
DC
C_ NT PR _F
AS
AS
_V
_V
RT C L_ EG
K_
IG
IG
BI
BI
SC
C_ NT PR
_D
_D
_D
_D
RT _C L_
_
TL
TL
TL
TL
TL
C NT
)
ed
CN
CN
CN
CN
CN
RT _C
rv
C_
C_
C_
C_
C_
se
C
RT
RT
RT
RT
RT
RT
(re
31 30 29 28 27 25 24 22 21 14 13 11 10 8 7 0
1 0 1 0 4 4 0 4 4 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_VREG_FORCE_PD RTC voltage regulator - force power down (in this case power down
means decreasing the voltage to 0.8V or lower). (R/W)
RC IS SO
O
RT _C L_ ST EM FO E_ U
RT _C L_ ST EM OR _C D
IS
O E_ OI
EM FO CE SO
RT _C L_ RC EM OR E_L U
RT _C L_ RC _NO OL E_L U
RT _C L_ OW _IS SO _CP D
RT _C L_ ST EM D_ E_ U
C NT SL M _F EN PD
C NT FA M _ RC LP
C NT FA M _F LW LP
E_ O
U
NO
C NT SL M _ C U
C NT FA M _ RC D
C NT FO M _F C P
_F RC _N
C NT FO E _F C P
C NT SL E I W P
C NT FA M _P RC P
TM M_ OR E_I
RT _C L_ OW EM OR E_P
RT _C L_ OW EM FO E_P
RT _C L_ ST EM FO E_
RT _C L_ ST EM FO E_
RT C L_ ST EM O N
C NT FA M _ RC
AS E _F C
C_ NT FA M _F _E
C NT SL M _F C
_F TM M OR
RT _C L_ OW EM OR
RT _C L_ OW EM PD
TL AS ME _F
C NT SL M _
C_ NT SL M O
RT _C L_ OW EM
CN L_F OW EM
RT _C L_ RC _PU
RT _C L_ OW _PD
C NT SL M
C NT FO E
C NT SL E
C NT FO N
RT _C L_ RC
RT _C L_ _E
C NT PD
RT _C L_
C NT
)
ed
R T _C
rv
se
C
RT
(re
31 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 1 0 1 Reset
RT _C L_ TER RA 3_F RC PU
RT _C L_ TER RA 3_F RC PD
RT _C L_ TER RA 2_F RC PU
RT C L_ ER A _F C D
RT _C L_ TER RA 1_F RC PU
RT _C L_ TER RA 1_F RC PD
RT _C L_ M RA 0_F RC PU
CN L_L M0 OR _F CE D
_L P_ OR _P CE U
D
C_ NT INT _R M2 OR E_P
C_ NT RO 0_F M0 OR E_P
TL SL _F CE OR _P
SL M C U _P
E_ U
PD
C NT IN FO E C U
D
C NT IN _ M O E_
C NT IN _ M O E_
C NT IN _ M O E_
C NT IN _ M O E_
C NT IN _ M O E_
C NT RO _ M O E_
RC P
RT _C L_ IFI_ RC OR E_P
RT _C L_ TER RC _P E_P
CN L_I ER AM _P EN
_R ER AM PD N
M A P N
_E PD N
N
O E_
RT _C L_ TER RA 4_F RC
TL NT _R 2_ D_E
O _R 1_ _E
PD 0_ _E
N _E
C NT IN _ N EN
M _F PD
C_ NT INT _R M3 D_
_F RC
C NT W FO _F C
0_ M D
C NT IN _ M O
C NT IN _ E U
C_ NT INT _R M4 D
RT _C L_ IFI_ AP OR
RT _C L_ TER _E D_
RT C L_ ER A _P
P_ EM E_
RT C L_ ER A _F
EM O
RT _C L_ TER RA _P
C_ NT INT _R M4
C NT IN PD _P
C NT W R _F
RT _C L_ IFI_ AP
RT _C L_ _W AP
RT _C L_ TER RA
C NT W R
C NT DG R
RT _C L_ _W
RT _C L_ _W
C NT DG
C T G D
RT _C L_
RT C L_
C NT
C_ NT
)
)
ed
ed
N
R T _C
RT C
rv
rv
C_
se
se
C
RT
RT
(re
(re
31 30 29 28 27 26 25 24 23 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0
x x x x x x x x 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 Reset
LD
O N
HO
UT _E
_A LD
AD HO
_P O
LD DG UT
C_ NT INT _R M3 OR E_I ISO
RT _C L_ M FO 0_F RC ISO O
A
C NT IN _ M O E_ IS
C NT IN _ M O E_ IS
C NT RO 0_ M O E_ IS
C NT DG A RC N E_ IS
HO L_ _
_D _R C_ CE O LD
RT _C L_ TER RC _N E_I ISO
RT C L_ ER A _F C SO
O NT AD
RT _C L_ TER RA 3_F RC NO
RT _C L_ TER RA 2_F RC NO
RT _C L_ TER RA 1_F RC NO
RT _C L_ M RA 0_F RC NO
RT _C L_ _P FO E_ RC NO
_A TC DG O
TL LR RT OR E_IS HO
C_ NT RE AD OR E_ LD
C NT IN _ E OI SO
UT _C _P
C NT IN FO E C O
AD R L_ IS
C NT IN _ M O E_
C NT IN _ M O E_
C NT IN _ M O E_
C NT RO _ M O E_
C NT DG 0_ RC O E_
C NT DG A O IS O
RT _C L_ IFI_ RC OR E_N
RT _C L_ _P D_F RC HO
_P _ T O
CN L_C G_ _F C UN
RT _C L_ TER RA _IS SO
RT _C L_ TER RA 4_F RC
G EG CN _N
RT _C L_ _P D_F RC O
C NT DG A O E_
C NT W FO _F C
C NT IN _ M O
C NT IN _ M O
RT _C L_ IFI_ AP OR
RT _C L_ TER RA 4_F
C NT W R _F
RT _C L_ _W AP
C NT DG R
RT _C L_ _W
C NT DG
RT C L_
C_ NT
)
ed
RT _C
rv
se
C
RT
(re
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0x000000FFF Reset
d)
CN
e
rv
C_
se
RT
(re
31 30 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
31 0
0x050D83AA1 Reset
C1
C1
U_
U_
CP
CP
O
PP
PR
_A
L_
LL
L
TA
TA
_S
_S
SW
SW
_
L_
TL
NT
)
ed
CN
rv
C_
C_
se
RT
RT
(re
31 26 25 20 19 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
RTC_CNTL_SW_STALL_PROCPU_C1 reg_rtc_cntl_sw_stall_procpu_c1[5:0],
reg_rtc_cntl_sw_stall_procpu_c0[1:0] == 0x86 (100001 10) will stall PRO_CPU, see also
RTC_CNTL_OPTIONS0_REG. (R/W)
RTC_CNTL_SW_STALL_APPCPU_C1 reg_rtc_cntl_sw_stall_appcpu_c1[5:0],
reg_rtc_cntl_sw_stall_appcpu_c0[1:0] == 0x86 (100001 10) will stall APP_CPU, see also
RTC_CNTL_OPTIONS0_REG. (R/W)
31 0
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Reset
RT _C L_ UC _PA 4_ LD FOR E
RT _C L_ UC _PA 3_ LD FOR E
RT _C L_ UC _PA 2_ LD FOR E
RT _C L_ NS _PA 1_ LD FOR E
RT _C L_ NS 4_H 0_ LD FOR E
RT C L_ NS _H D LD OR E
RT _C L_ NS 2_H LD OR FOR E
RT _C L_ AC 1_H LD OR E E
C NT TO H D HO _ C
C NT TO H D HO _ C
C NT TO H D HO _ C
C NT SE H D HO _ C
C NT SE E D HO _ C
C_ NT SE E3 OL HO _F C
C NT SE E O _F _ C
C NT PD E O _F C C
RT _C L_ UC _PA 5_ LD FOR
C_ NT PD 2_ OL _FO CE
TL DC 1_H LD FO CE
DC _H LD OR E
1_ OL _F CE
LD FOR CE
_A 2 O _F RC
C NT TO H D HO _
RT _C L_ UC _PA 6_ LD
O E
E
CN L_A AC HO D_ R
RT C L_ UC _PA FO CE
RT _C L_ UC _PA 7_ CE
_F C
RC
HO D_ OR
C NT TO H D HO
C_ NT TO H D_ R
C NT TO H D R
RT _C L_ UC OL _FO
C NT TO _H D
RT _C L_ 2P OL
C NT X3 _H
RT _C L_ 2N
C NT X3
RT _C L_
C NT
d)
ve
RT _C
r
se
C
RT
(re
31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
R
CL
S_
TU
L
TA
E
_S
_S
P1
P1
EU
EU
AK
AK
_W
W_
XT
XT
E
_E
L_
TL
NT
)
ed
CN
C
rv
C_
C_
se
RT
RT
(re
31 19 18 17 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
S
TU
TA
_S
P1
EU
AK
W_
XT
_E
TL
d)
CN
e
rv
C_
se
RT
(re
31 18 17 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset
NA
_E
SH
SE NA
LA
T
NA
_F
LO _E
AI
ES
_W
_C _RF
_E
HR
NA
ST
ST
_E T
UT D
UT E
_T
O _D
_R
_R
O _P
UT
N_ T
UT
UT
N_ T
W _OU
W _OU
O
O
N_
N_
N_
RO N
RO N
W
_B W
_B W
O
TL RO
RO
RO
TL O
BR
R
_D
CN L_B
_B
_B
CN L_B
TL
TL
TL
C_ NT
C_ NT
)
ed
CN
CN
CN
RT _C
RT _C
rv
C_
C_
C_
se
C
C
RT
RT
RT
RT
RT
(re
31 30 29 27 26 25 16 15 14 13 0
RTC_CNTL_DBROWN_OUT_THRES Brownout threshold. The brownout detector will reset the chip
when the supply voltage is approximately below this level. Note that there may be some variation
of brownout voltage level between each ESP32 chip. 0: 2.43 V ± 0.05; 1: 2.48 V ± 0.05; 2: 2.58
V ± 0.05; 3: 2.62 V ± 0.05; 4: 2.67 V ± 0.05; 5: 2.70 V ± 0.05; 6: 2.77 V ± 0.05; 7: 2.80 V ± 0.05.
(R/W)
Revision History