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F A B D+ Abd: Tabla de Verdad

The document contains code for a logic circuit with inputs A, B, C, D and output F. It defines the circuit using a structural description with gates (F <= ((not A and B and (not D)) or (A and B and D))) and also provides a testbench simulation coding applying different input combinations over time and observing the output F.

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33 views4 pages

F A B D+ Abd: Tabla de Verdad

The document contains code for a logic circuit with inputs A, B, C, D and output F. It defines the circuit using a structural description with gates (F <= ((not A and B and (not D)) or (A and B and D))) and also provides a testbench simulation coding applying different input combinations over time and observing the output F.

Uploaded by

Speed Pizzas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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F= Á B D́+ ABD

Tabla de verdad

Codigo de esquematico

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity archivo is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
C : in STD_LOGIC;
D : in STD_LOGIC;
F : out STD_LOGIC);
end archivo;

architecture Behavioral of archivo is


begin

F <= ((not A and B and (not D)) or (A and B and D));


end Behavioral;

Código de simulación

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity sim1 is
-- Port ( );
end sim1;

architecture Behavioral of sim1 is

--Se coloca el nombre del archivo creado


component archivo
port(
--Puertos de entradas y salidas
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
F : out std_logic
);
end component;

-- Señales de las entradas


signal A,B,C,D : std_logic := '0';

-- Señales de salidas
signal F : std_logic;

begin

UO: archivo Port map (


A=>A,
B=>B,
C=>C,
D=>D,
F=>F
);
process begin
--- Estímulos de la simulación wait for 100 ns;

A <= '0';
B <= '0';
C <= '0';
D <= '0';--
wait for 100 ns;

A <= '0';
B <= '1';
C <= '0';
D <= '0';--Para 1
wait for 100 ns;

A <= '0';
B <= '1';
C <= '0';
D <= '0';--

wait for 100 ns;

A <= '0';
B <= '1';
C <= '0';
D <= '1';--Pára 1

A <= '0';
B <= '1';
C <= '1';
D <= '0';--

wait for 100 ns;

A <= '0';
B <= '1';
C <= '1';
D <= '1';--

wait for 100 ns;

A <= '1';
B <= '0';
C <= '0';
D <= '0';--

wait for 100 ns;


wait for 100 ns;
A <= '1';
B <= '1';
C <= '0';
D <= '1'; --Para 1

wait for 100 ns;

A <= '1';
B <= '1';
C <= '1';
D <= '1';--Para 1

wait for 100 ns;

wait;

end process;

end Behavioral;

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