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Digitally Controlled Oscillator (DCO)-Based Architecture for RF Frequency

Synthesis in a Deep-Submicrometer CMOS Process

Article  in  IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · December 2003
DOI: 10.1109/TCSII.2003.819128 · Source: IEEE Xplore

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 11, NOVEMBER 2003 815

Digitally Controlled Oscillator (DCO)-Based

Architecture for RF Frequency Synthesis in a
Deep-Submicrometer CMOS Process
Robert Bogdan Staszewski, Member, IEEE, Dirk Leipold, Khurram Muhammad, and
Poras T. Balsara, Senior Member, IEEE

Abstract—A novel digitally controlled oscillator (DCO)-based example, frequency tuning of a low-voltage deep-submicrom-
architecture for frequency synthesis in wireless RF applications eter CMOS oscillator is an extremely challenging task due to
is proposed and demonstrated. It deliberately avoids any use of its highly nonlinear frequency versus voltage characteristics
61
an analog tuning voltage control line. Fine frequency resolution is
achieved through high-speed dithering. Other imperfections [1] and low-voltage headroom making it susceptible to the
of analog circuits are compensated through digital means. The pre- power/ground supply and substrate noise. In such low supply
sented ideas enable the employment of fully-digital frequency syn- voltage case, not only the dynamic range of the signal suffers
thesizers using sophisticated signal processing algorithms, realized but also the noise floor rises, thus causing even more severe
in the most advanced deep-submicrometer digital CMOS processes degradation of the signal-to-noise ratio. At times, it is possible
which allow almost no analog extensions. They also promote cost-
effective integration with the digital back-end onto a single silicon to find a specific solution, such as utilizing a voltage doubler
die. The demonstrator test chip has been fabricated in a digital [2]. Unfortunately, with each CMOS feature size reduction,
0.13- m CMOS process together with a DSP, which acts as a digital the supply voltage needs also to be scaled down, which is
baseband processor with a large number of digital gates in order inevitable in order to avoid breakdown and reliability issues.
to investigate noise coupling. The phase noise is 112 dBc/Hz at Circuits designed to ensure proper operation of RF amplifiers,
500-kHz offset. The close-in spurious tones are below 62 dBc,
while the far-out spurs are below 80 dBc. The presented ideas filters, mixers, and oscillators depend on circuit techniques
have been incorporated in a commercial Bluetooth transceiver. that operate best with long-channel, thick-oxide devices with
supply voltage of 2.5 V or higher. The process utilized in
Index Terms—Deep-submicrometer CMOS, digital compen-
sation, digital control, digitally controlled oscillator (DCO), this paper is optimized for short-channel, thin-oxide devices
frequency synthesizer. operating as digital switches at only 1.5 V. In order to address
the various deep-submicrometer RF integration issues for
frequency synthesis, digitally-intensive techniques need to be
I. INTRODUCTION developed such that analog imperfections are compensated for
by using advanced signal processing techniques.
T RADITIONAL designs of commercial frequency synthe-
sizers for multigigahertz mobile RF wireless applications
have almost exclusively employed the use of a charge-pump
So far there have not been any reports in literature (except
recently in [1]) on the fully digital control of oscillators for
phase-locked loop (PLL), which acts as a local oscillator (LO) RF applications. Lack of the fully digital control is a severe
for both a transmitter and a receiver. Unfortunately, the design impediment for the total integration in a deep-submicrometer
flow and circuit techniques required are analog intensive and CMOS process, without which signal processing algorithms
utilize process technologies that are incompatible with a digital cannot be used to control or drive the analog circuits. There
baseband (DBB). Nowadays, the DBB design constantly mi- have been several disclosures on ring-oscillator-based DCOs
grates to the most advanced deep-submicrometer digital CMOS for clock recovery and clock generation applications [3] [4].
process available, which usually does not offer any analog ex- However, the frequency resolution is low and spurious tone
tensions and has very limited voltage headroom. Consequently, level is high for these DCOs, which seem to become an effective
the aggressive cost and power reductions of high-volume mo- deterrent against digitally-intensive RF synthesizers for wire-
bile wireless solutions can only be realistically achieved by the less communications. DCO in reference [1] deliberately avoids
highest level of integration, and this favors digitally-intensive any analog tuning voltage controls. This allows for its loop
approach in the most aggressive deep-submicrometer process. control circuitry, including loop filter, to be implemented in a
Deep-submicrometer CMOS processes present new integra- fully digital manner. That DCO, however, provides only a raw
tion opportunities on one hand, but make it extremely difficult and bare minimum of functionality from a signal processing
to implement traditional analog circuits, on the other. For standpoint. This paper introduces a circuitry built around it
for the purpose of adding a hierarchical layer of arithmetic
Manuscript received May 11, 2003; revised July 2003. This paper was rec-
ommended by Guest Editor M. Perrott. abstraction that makes it easier to operate the DCO from higher
R. B. Staszewski, D. Leipold, and K. Muhammad are with the Texas Instru- logical levels in a wide variety of digitally-intensive synthesizer
ments Inc., Dallas, TX 75243 USA (e-mail: [email protected]). architectures.
P. T. Balsara is with the Center for Circuits and Systems, University of Texas
at Dallas, Richardson, TX 75083 USA. The organization of this paper is as follows. Section II gives
Digital Object Identifier 10.1109/TCSII.2003.819128 an overview of the digitally controlled oscillator, whose time-
1057-7130/03$17.00 © 2003 IEEE

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Fig. 1. LC tank with dedicated discrete capacitor banks for each of the three operational modes.

domain mathematical model is derived in Section III. Section IV Fig. 2 demonstrates numerical example of the frequency
describes the normalized DCO and its time-domain model. The transversal for the implemented DCO. The acquisition mode
objective there is to suggest possibility of a fully-digital PLL starts from the mid-point reset value of 128. The desired center
implementation. Section V describes synchronously-timed ad- frequency lies two channels or 2-MHz lower from the center
justments of a tuning word to the DCO input. PVT and acquisi- channel of the Bluetooth band. This translates to between four
tion interfaces are presented in Section VI, whereas the tracking and five acquisition steps. As a result, the loop will first quickly
bit interface is shown in Section VII. An example of a digital move several steps lower. After reaching the point about 2 MHz
PLL architecture possible with the DCO is given in Section VIII. away, it will dither between the codes of 123 and 124, not being
The implementation and measured results are presented in Sec- able to resolve any finer. In this example, the transition to the
tion IX. tracking mode happens when the acquisition code is 123. This
code stays frozen for the duration of the packet. The tracking
mode always starts from the mid-point value of 31. It happens
II. DIGITALLY CONTROLLED OSCILLATOR (DCO)
that the desired center frequency is located about 230-kHz
Advanced CMOS process lithography allows nowadays to higher from that point—this corresponds to 10 tracking steps.
create extremely small size but well-controlled varactors. The The presented oscillator is built as an ASIC cell (Fig. 3) with
switchable capacitance of the finest differential varactor in this truly digital inputs and outputs (even at the RF frequency of
0.13- m CMOS process is 38 attofarads, which corresponds to 2.4 GHz with rise and fall times specified to be 50 ps) oper-
frequency step size of 23 kHz at 2.4 GHz. Frequency tuning of ating in the discrete-time domain, even though the underlying
the presented DCO is accomplished by means of a quantized functionality is mainly continuous-time and continuous-ampli-
capacitance (with no analog tuning voltage control) of the LC tude in nature. The RF signal digitizer is a differential-to-single-
tank (Fig. 1) based oscillator [1]. ended converter that transforms the analog oscillator waveform
There are three operational modes of the DCO as imple- into the zero-crossing digital waveform with a high degree of
mented in the presented IC chip: common-mode rejection. The digitizer stops the analog nature
• Process/voltage/temperature (PVT)—calibration mode: from propagating up in the hierarchy, right at the interface level.
Active during cold power-up and on as-needed basis. The analog design, modeling and simulation constraints of the
Places the nominal center frequency of the DCO in the system are thus vastly simplified. An analogy could be drawn
middle of the Bluetooth band. Possible to use this mode here to a flip-flop and its fundamental role in the sequential
on a regular basis as an ultra-fast acquisition before the digital circuits, even though its underlying nature and internals
regular acquisition mode. are analog. The digital nature of the DCO allows the frequency
• Acquisition mode: Active during channel select. synthesizer that controls it to be implemented in a fully-digital
• Tracking mode: Active during the actual transmit and re- manner, thus extending scalability, insensitivity to process and
ceive. The fractional bits undergo high-speed dithering to environmental variations and general ease of design.
increase frequency resolution.
The desired oscillating frequency is acquired step-by-step by III. TIME-DOMAIN MATHEMATICAL MODEL OF THE DCO
traversing through the three capacitor banks with progressively Due to the fact that the conventional RF synthesizers are
finer resolution. At the end of the PVT and acquisition modes, based on the frequency-domain model, whereas the proposed
the terminating-mode capacitor state is frozen and it now consti- discrete-time architecture is rooted in time domain, this section
tutes a new center frequency from which the frequency offsets, introduces basic time-domain equations and modeling concepts
during the following modes, are referenced. that are used in the proposed architecture. It should be noted

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(a)

(b)
Fig. 2. Frequency transversal example for the implemented DCO. (a) PVT to acquisition. (b) Acquisition to tracking. PVT is calibrated to the middle of the
Bluetooth band with code 111.

Fig. 3. DCO as an ASIC cell with digital I/Os.

here that recently there have been other attempts to model RF be . This will result in a higher frequency of
frequency synthesizers in the time domain, such as in [5] for oscillation of . Let’s determine the relationship
fractional-N PLLs. between and . Expanding results in
Let the nominal frequency of oscillation be . It is related
to the nominal clock period by its inverse . If (1)
the clock period is shortened by , the new clock period will

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Fig. 4. Development of an accumulative timing deviation (TDEV).

Fig. 5. nDCO time-domain model a with generic phase detection. The complete transfer function is unity. The generic phase detector suggests possibility of a
fully-digital PLL implementation.

For , using the approximation formula The oscillator tuning word (OTW) at the DCO input (active
, (1) simplifies to bits in Fig. 3, where is , or and ) will change its
operating frequency by . On every rising
(2) DCO edge event, the DCO event output multiplied by a
“constant” will be accumulated. At the end of cycles,
it will accumulate the TDEV timing deviation according to (4).
(2) was used extensively in this design as a conversion formula The accumulated timing deviation is only defined at the end of
for system analysis and simulation. The simulation environment the DCO clock cycle with each rising clock edge. The timing
is based on VHDL which, being an event-driven digital simu- deviation is a measure of “badness” and signifies the departure
lator, is foreign to the concept of frequency and exclusively op- from the desired timing instances that has to be corrected by a
erates in the native time domain. As an example of (2), 1 fs of feedback loop mechanism.
a period deviation will cause 5953-Hz frequency deviation in
the middle of the Bluetooth band at 2440 MHz. It is obvious
IV. DCO GAIN NORMALIZATION AND ITS TIME-DOMAIN
that a fine timing resolution is required at RF frequencies for
MODEL
time-domain simulation tools. In fact, it was necessary to resort
to the finest timing resolution of 1 fs that the VHDL standard At a higher level of abstraction, the DCO oscillator, together
provides. From a physical viewpoint, a femtosecond time devi- with the DCO gain normalization multiplier, com-
ation is quite meaningless for a single observation, and only an prise the normalized . The DCO gain normalization de-
averaged value could make sense. couples the phase and frequency information throughout the
For a time-invariant oscillator with a fixed frequency excur- system from the process, voltage and temperature variations that
sion, period deviation from will result in devia- normally affect the DCO gain , whose estimate is denoted
tion from ideal timing instances within one oscillator clock pe- as . The frequency information is normalized to the value
riod, within two clock periods, etc., as shown in Fig. 4. of the external reference frequency . The digital input to the
Within oscillator clock cycles, the accumulated timing devia- nDCO is a fixed-point normalized tuning word (NTW), whose
tion (TDEV) will reach integer part LSB bit corresponds to . For additional discus-
sion on the DCO gain normalization issue, see [6].
TDEV (3) The time-domain nDCO model is presented in Fig. 5.
Provided the DCO gain is estimated correctly, the normalized
tuning word (NTW) (denoted as ) at the nDCO input
For varying values, (3) could be rewritten as will change its operating frequency by . On
every rising DCO edge event, multiplied by will be
TDEV (4) accumulated. The accumulation interval is established by the
inverse of the reference frequency . It is related to
the nominal oscillation frequency by , where
Equation (4) states that the TDEV defined as the difference is the traditionally-defined (possibly fractional) frequency
between actual and ideal timing instances is an integral of the division ratio. During the interval, the frequency tuning
oscillator frequency deviation. The direction is selected to- input is assumed constant. It is justified by the fact that between
ward shortening the period such that and signs agree. the reference events there are not any updates to the tuning

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Fig. 6. Synchronously-optimal sampling and timing adjustment of the DCO

input.

word. At the end of cycles, the accumulated timing deviation

TDEV will be sampled with value
Fig. 7. Waveforms for capacitance change of an LC-tank oscillator.
TDEV TDEV

instances when the oscillating energy is fully stored in a capac-

itor are the worst moments to change the capacitance. The total
charge must be preserved, so changing the capacitance at those
moments causes the electrical potential to exhibit the largest
(5) change , as shown plot in Fig. 7(a). These per-
turbations are then AM-to-PM translated by the oscillator circuit
where . The samples out of the nDCO are at the DCO into timing jitter. Changing the varactor capacitance at times
rate while the generic phase detector operates at the reference when it is fully discharged will hardly affect its voltage and thus
clock. The change of data rate is accomplished using a sampler hardly contribute to the oscillating jitter [Fig. 7(b)].
which employs a first-order interpolation [7]. The proposed solution is to control the timing moments when
The DCO phase accumulation is not tied to any hardware. It the varactor capacitance change is allowed to occur, thus min-
simply reflects the workings of a progression of time. However, imizing jitter due to the tuning word update. This is imple-
the sampling mechanism requires an explicit hardware that would mented by feeding the delayed oscillator edge transitions back
take periodic snapshots of the evolving TDEV. Time-domain as the clock input to the synchronous register retiming stage,
model of the entire normalized DCO is also given in Fig. 5. A as shown in Fig. 6. The retiming stage ensures that the input
generic hardware circuitry is added to the nDCO that would control data, as seen by the oscillator, is allowed to change at
detect TDEV and convert it to the digital bit format. At the same precise and optimal time after the oscillator zero crossings. The
time, it deals with the troublesome unit of time by performing feedback loop delay is set algorithmically to minimize the os-
normalization to the clock period of the DCO oscillation, defined cillator jitter. The algorithm to control the delay line value for
as unit interval (UI). The diagram does not suggest any particular the optimal timing adjustment takes advantage of the fact that
mechanism, it merely indicates and mathematically describes a the phase error, which is related to the DCO jitter metric to be
timing deviation detector that would determine any frequency and minimized, is now in digital form and readily available for pro-
phase deviations of the oscillator which would then be fed back cessing. Various statistics of this signal, such as mean squared
as loop corrections. The transfer function from the normalized error, could be thus optimized by utilizing the digital signal pro-
tuning word input to the detector output is 1 [bits/bits] within cessing hardware. The tightly-integrated companion DSP en-
one frequency reference clock cycle. An appropriate digital gine is capable of transferring the digital phase error samples
scaler/filter between and will give rise to the phase-locked to its own memory at the 13-MHz reference frequency and then
loop (PLL). An example is shown in Section VIII. to postprocess them.
The actual delay could be accomplished by a voltage-con-
V. SYNCHRONOUSLY OPTIMAL OSCILLATOR trolled delay line. In the testchip, we chose a long string of
TUNING WORD RETIMING inverters while externally controlling their supply voltage.
The allowed range of the delay line voltage is quite limited
Fig. 6 shows a principle of the synchronously-optimal DCO
(from 1 to about 1.8 V) so the delay change contribution per in-
input tuning word retiming method. This idea is based on the
verter is not very significant. However, the delay multiplied by
observation that changing the tuning control input of an oscil-
the total number of inverters can exceed the DCO clock cycle,
lator, in order to adjust its phase/frequency in a normal PLL
thus guaranteeing the full 360 coverage.
operation, is quite a disturbing event that reveals itself as jitter
or phase noise [8]–[10]. This is especially noticeable in case
VI. PVT AND ACQUISITION DCO BANKS INTERFACE TO
of a sample-mode oscillator, such as the DCO, where its os-
DIGITAL LOGIC
cillating frequency is commanded to change at discrete times.
Since the oscillating frequency of an LC tank is controlled by Fig. 8 illustrates the interface control structure for the 8-bit
a voltage-to-capacitance conversion device (e.g., varactor), the binary-weighted acquisition bits (the structure for PVT bits is

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Fig. 8. Control circuit of the oscillator acquisition bits.

almost identical). Their direct digital control is arithmetically ating frequency. They are inactive during the subsequent normal
expressed as unsigned number arguments into the effective res- operation when the settled synthesized frequency is used. The
onating capacitance of the LC tank. The digital PLL loop con- tracking bits of the DCO oscillator, on the other hand, need a
trol, however, natively operates at an offset frequency with re- much greater care and attention to detail since any phase noise
spect to a certain center or “natural” frequency. A conversion or spurious tone contribution of the tracking bits will degrade
mechanism, by simply inverting the MSB bit, is thus only re- the synthesizer performance.
quired at the interface point. Fig. 9 shows the idea to increase frequency resolution of the
The two sets of interface words from memory registers could DCO. Tracking part of the oscillator tuning word (OTW) is
be the last frequency estimate from the controller’s lookup table split into 6 integer bits and 5 fractional bits. The LSB of the
in order to speed up the loop operation. The two sets of fre- integer part corresponds to the basic frequency resolution of
quency offset status words are reported back to the controller the DCO oscillator. The integer part is thermometer encoded to
through the memory registers. At reset, the DCO is placed at the control the same-size DCO varactors of the LC-based tank os-
center of the operational frequency range through asynchronous cillator. In this scheme, all the varactors are unit weighted but
clear of the driving registers. This mechanism prevents the os- their switching order is predetermined. This guarantees mono-
cillator from failing to oscillate if the random power-up values tonicity and helps to achieve an excellent linearity, especially if
of tuning word registers set it above the oscillating range, which their switching order agrees with the physical layout. The tran-
might happen at the slow process corner. sients are minimized since the number of switching varactors
During the active mode of operation, the new tuning word is is no greater than the code change. This compares very favor-
latched by the register with every clock cycle. Upon the DCO ably with the binary-weighted control, where an incremental
operational bank mode change-over, the last stored value of the change can cause all the varactors to toggle. In addition, due to
tuning word is maintained by the register. Consequently, during equal load throughout for all bits, the switching time is equalized
the regular operation, only one interface path can be active at in response to code changes. In this implementation, a slightly
a given time, whereas the previously executed modes maintain more general unit-weighted capacitance control is used to add
their final DCO control states. A zero phase restart (ZPR) mech- some extra coding redundancy which lends itself to various al-
anism is used to zero out the phase detector output to avoid any gorithmic improvements of the system operation, as described
discontinuities in the oscillator tuning word during the mode below.
switchover. A short explanation of the ZPR principle is as fol- The fractional part, on the other hand, employs a time-aver-
lows: At the mode switchover, the tuning word of the last mode aged dithering echanism to further increase the frequency res-
corresponds to a certain value of the phase error. This tuning olution. The dithering is performed by a digital modulator
word is now frozen, so the phase error value that maintains it that produces a high-rate integer stream whose average value
is not longer needed. However, the new mode is always refer- equals the lower-rate fractional input. The digital Modu-
enced to the new center frequency established by the last mode. lator (SDM) is considered an essential part of the proposed DCO
Consequently, it operates on the excess phase error rather than solution for wireless applications. techniques have been
absolute. Therefore, the old value of the phase error that corre- used successfully for over two decades in the field of analog data
sponds to the frozen tuning word of the last mode would have converters. This has developed a rich body of knowledge for
to be constantly subtracted from the new phase error. A better other applications to draw upon [11]. A simple first-order SDM
solution is to use the proposed method of zero phase restarting. pattern [12] is not random at all and is likely to create spurious
In this way, a hitless progression through the three DCO opera- tones. If the LSB varactor has a frequency resolution of and
tional modes is accomplished. is dithered at a rate of then it will produce two spurs away
on both sides of the oscillating frequency with the power level of
VII. TRACKING DCO BANK INTERFACE TO DIGITAL LOGIC relative to the carrier, where .
The PVT and acquisition bits described above are used in In this implementation, the step size of the LSB varactors is
the preparatory steps to quickly establish center of the oper- and if the dithering clock is 600 MHz such

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Fig. 9. Improving frequency resolution with 61 dither of DCO tracking bits.

that the maximum dithering rate (for the frac- 2.4-GHz DCO is with a 13-MHz update rate.
tional input of 0.5), then the generated spur level is only 92 Consequently, the effective time-averaged frequency resolution,
dBc. It could be shown through Fourier series decomposition of within one reference cycle, after the 600 MHz dither with
the modulating wave that for the slowest nonzero dithering rate five sub-LSB bits would be .
of (corresponding to the fractional input of The frequency resolution improvement achieved here is
1/32) and beyond, the generated spur rises only 4 dB to 88.3 . This roughly corresponds to the sampling rate
dBc. Even though this level is sufficiently low for most wire- speedup of .
less applications, it is far from representing the worst case. First The structure of the digital modulator is depicted
of all, the DCO input, and consequently the dithering rate, in Fig. 10. It is implemented as a third-order MASH-type
is not constant but is subject to a continual change during the architecture [13] that could be conveniently and efficiently
normal closed-loop PLL operation thus widely spreading the scaled down to a lower order. It is clocked by the 600 MHz
spur energy. Second, the modulator is normally selected divided-by-4 oscillator clock. Its topology is based on [12].
to operate in the second or third order to further randomize the The original structure is not the best choice for high-speed
dithering pattern. With such insignificant amount of quan- designs because the critical path spans through all the three
tization energy, no phase noise degradation could be observed accumulator stages and the carry sum adders. A critical path
in our system during normal operation. retiming transformation needed to be performed in order to
The integer part of the tuning word is then added to the shorten the longest timing path to only one accumulator so
integer-valued high-rate-dithered fractional part. The resulting that the 600-MHz clock operation could be reached. Since
binary signal is thermometer encoded to drive the sixty-four the structure is highly modular, the lower-order modulation
tracking bank varactors. In this simplest embodiment, the characteristics could be set by disabling the tail accumulators
high-rate fractional part is arithmetically added to the low-rate through gating off the clock, which is a preferred method from
integer part thus making its output, as well as the entire signal power saving standpoint.
path terminating at the varactors inside the DCO, high rate. The combiner circuit merges the three single-bit carry-out
The separate DCO fractional bits of Fig. 1 are not used streams such that the resulting multi-bit output satisfies the
here. A preferred solution to implement this approach is third-order spectral property. The stream equation
presented below. It should be noted here that we purposefully below is a result of register retiming of the architecture origi-
left uncorrected a small delay mismatch between the integer nally described in [12]
and fractional parts due to the SDM group delay. The precise
alignment was not necessary since it was determined that the (6)
resulting degradation was insignificant due to the high-rate
dithering and small amount of quantization energy. where is the delay element operation. This equation
The dithering method trades the sampling rate for the is easily scaled down to the second- or first-order by disre-
frequency granularity. Here, the frequency resolution of the garding the third or third and second terms, respectively.

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Fig. 10. MASH-3 61 digital modulator structure.

Fig. 11. Implementation block diagram of the DCO tracking bits with DEM of the integer part and 61 dithering of the fractional part. Critical high-speed
arithmetic operations are performed in “analog” domain through capacitative additions inside the DCO.

Fig. 11 reveals the preferred method of implementing the Fig. 13 illustrates the second-order MASH-type mod-
integer and fractional oscillator tracking control from a lower ulation of the fixed-point tracking DCO tuning control word
power standpoint. The fractional path of the DCO tracking bits, with five-fractional bits. The fixed-point tuning word (upper
which undergoes high-rate dithering, is entirely separated from plot) consists of six-integer bits and five fractional bits and is
the lower-rate integer part. It even has a dedicated DCO input clocked at the 13-MHz reference frequency. The modulates
just to avoid “contaminating” the rest of the tracking bits with the five-bit fractional part at 600-MHz clock rate and outputs the
frequent transitions. The switch matrix, together with the row integer stream that controls the DCO frequency. The lower plot
and column select logic, operates as a binary-to-unit-weight en- shows the output stream “merged” with the 6-bit integer
coder in response to the integer part of the tracking tuning word. part stream. For the purposes of visualization only, the integer
The modulator is responsive to only the fractional part of stream is mathematically decoded into an unsigned number rep-
the tracking tuning word. The actual merging of both parts is resentation and added to the mathematically decoded signed
performed inside the oscillator through time-averaged capaci- fractional stream.
tance summation at the LC tank.
Another important benefit of the chosen approach is that A. Dynamic Element Matching of the Varactors
the high-speed arithmetic operation of the (6) combiner is now
trivial. Fig. 12 shows the proposed implementation. All that is Ideally, each of the unit-weighted capacitors of the tracking
required are flip-flop registers (for the delay operation) with com- bank has the exact same capacitative value. Using real-world
plementary outputs (for the negation). The arithmetic addition is fabrication process, however, the capacitative value of each ca-
performed inside the oscillator through capacitance summation. pacitor will vary slightly from the ideal. As capacitors are turned

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Fig. 12. 61 modulator carry-out combiner structure.

Fig. 13. Simulation plot using the 61

modulation of the fractional part of the tracking tuning word. Top: fixed-point tuning word at 13-MHz frequency reference.
Bottom: decoded merged DCO integer input at 600 MHz with running average.

on and off by the integer tracking oscillator controller, nonlin-

earities will be evident in the output due to variations in capac-
itative values, as shown in Fig. 14.
A method to improve the digital-to-frequency conversion lin-
earity is also revealed in Fig. 11. It cyclically shifts the unit-
weighted varactors using the dynamic element matching (DEM)
method recently being employed in digital-to-analog converters
[14]. The integer part of the tuning word is split into upper and
lower bits. The upper bits are encoded and control the row se-
lection of the switch matrix. The lower bits are also encoded and
select the next column of the switch matrix. The cyclic shift of
unit-weight varactors is performed within the row (see Fig. 15)
but could also extend to other rows. However, the number of ac-
tive switches does not change for the same control input. Fig. 14. Cumulative nonlinearity of the DCO tracking bits.
In Fig. 15, the capacitors associated with an unfilled row
(“next row” signal of Fig. 11) of the switch matrix are rotated on rather than columns one through three are enabled. On the next
each clock cycle. Initially, the first three columns of row three clock cycle, columns three through five are enabled, etc. Ac-
are enabled. On the next clock cycle, columns two through four, cordingly, on each clock cycle, the set of capacitors used in the

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Fig. 15. Dynamic element matching through cyclic shift within a matrix row.

64-element array changes slightly. Over time, the nonlinearities be more mismatched due to the process gradient. If, during the
shown in Fig. 14 average out, thereby producing a much more course of operation, the varactor selection transitions through
accurate output. the column boundary, it is likely to create larger switching per-
With this DEM scheme, the enabled switches for a single turbations. It is proposed that before entering the finest tracking
row are rotated. This is accomplished by modulo incrementing mode, a rearrangement of DCO varactors to be performed such
the starting column of the enabled switches on each clock that “lower quality” capacitors be filled in order to maximize the
cycle. This method could be varied slightly by including two frequency dynamic range of the most preferred capacitor sec-
(or more) rows in the rotation. As a result, a larger frequency tion. In this architecture, this could be done upon switchover
range would be subject to the beneficial time averaging, by from fast tracking to tracking.
including a greater number of capacitors in the rotation, but at It should be noted that, while in other designs, the tracking
a cost of a longer repetition cycle. An alternative method of capacitors could be arranged differently depending upon various
increasing the DEM frequency span would be to lengthen the layout issues, a certain set of capacitors will always be favored
number of columns per row, thus creating a nonsquare matrix. based on the proximity metric to the control logic.
The output bits of the switch matrix are individually cou- Fig. 17 illustrates a method of improving the quality of the
pled to the bank of sixty-four resampling drivers, which are im- DFC conversion. In the initial state, half of the capacitors in
plemented as flip-flop registers. Each driver controls a single each column are turned on (as designated by a “ ”) and half
unit-weighted varactor of the LC tank. Using resampling by the are turned off (as designated by a “ ”). During fast tracking, the
clock eliminates delay mismatches due to path differences, such capacitors of the less desirable right-hand column are enabled
that the timing points of varactor transitions coincide. This helps or disabled in order to fine tune the oscillator to the selected
with the spurious noise control. It should be noted that while channel, to the extent possible. If additional capacitors need to
the switch matrix is shown (from an algorithmic standpoint) in be enabled or disabled, the capacitors from the left-hand column
a row/column configuration, the actual implementation is not a may be used, preferably those capacitors at the edges of the
precise grid. In fact, a group of rows could be physically com- column. After channel tuning, the capacitors in the left-hand
bined into a single line. column are used for modulation and drift control. In this way,
The principal difference in DFC versus DAC specification the most desirable capacitors are used for maintaining lock and
requirements is that the full dynamic range is not required for for generating the signal once data is being transmitted.
the available number of controlled units. In the DFC application,
the frequency headroom is required because it is not expected VIII. EXAMPLE OF A DIGITAL PLL ARCHITECTURE
that the oscillator operates at the precisely specified frequency The presented DCO-based system architecture allows for
before entering the tracking mode. the frequency synthesizer to be implemented in a fully-digital
manner and places little restrictions on the specific architecture
B. DCO Varactor Rearrangement of the PLL loop. For this reason, the phase detector mechanism
As illustrated in Fig. 16, the sixty-four integer tracking-bit depicted in Fig. 4 was described in generic terms. Since the
varactors of the LC tank have a physical layout of two long focus of this paper is on the DCO and its surrounding circuitry,
columns and the fractional tracking-bit varactors are arranged a brief description of a specific PLL structure used in our work
separately. However, the controlling circuitry is located only on is provided below as a means of further motivation.
one side. This creates an unbalanced structure in which routing The PLL architecture shown in Fig. 18 belongs to a class
to one varactor column is significantly shorter with easier ac- of PLL frequency synthesizers operating in the phase-domain,
cess than to the other and, therefore, their transient response is which was proposed in [15]. It is a type-I structure that operates
different. Moreover, the spatially separated devices are likely to in a digital fixed-point phase domain. The variable phase

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Fig. 16. Layout diagram of the tracking capacitors.

Fig. 17. Tracking capacitors rearrangement after initial settling.

is determined by counting the number of rising-edge clock tran- sampled by the frequency reference (FREF) clock and adjusted
sitions of the digitally controlled oscillator (DCO) clock. It is through linear interpolation [7] for the fractional time difference

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Fig. 18. Digital PLL architecture.

Fig. 19. Micrograph of the RF area residing in the lower-left corner of the chip
is shown.

Fig. 20. Measured synthesizer phase noise with the presented DCO: wide loop
between the DCO and FREF clock edges. The reference phase bandwidth of 8 kHz. Used HP8563E spectrum analyzer with HP85671A phase
is obtained by accumulating the FCW with every rising noise measurement utility.
edge of the FREF clock. The sampled variable phase is
subtracted from the reference phase in a digital-arith- processes (this process features 150 k gates per ). Conse-
metic phase detector. The digital phase error is then multiplied quently, in order to optimize cost, the number of classical RF
by a proportional loop gain constant and then normalized by components shall be minimized with proper architectural and
the DCO gain. circuit design choices. The synthesized RF output is buffered to
The chief advantage of keeping the phase information in the external pins through a class-E power amplifier (PA), which
fixed-point digital numbers is that, after the conversion, it was chosen due to its digital-friendly characteristics. The DCO
cannot be further corrupted by noise. Consequently, the phase core consumes 2.3 mA from a 1.5 V supply and has a very large
detector could be simply realized as an arithmetic subtractor tuning range of 500 MHz. Its frequency pushing is 600 kHz/V.
that performs an exact digital operation. Therefore, the number Measured phase noise of an all-digital frequency synthesizer
of conversion places is kept at minimum. with the presented DCO is shown in Fig. 20. The PLL loop
forms a type-I first-order structure with the 3-dB loop band-
width of 8 kHz. Fig. 21 reveals spurious tones emitted during
IX. EXPERIMENTAL RESULTS
locked operation in the wide span of 1.5 GHz when the DSP is
Fig. 19 is a die micrograph of the RF frequency synthesizer turned on. The close-in spurs lie below 62 dBc and are due
area. It is located in the lower-left corner and occupies 0.54 to suboptimal layout of power and ground lines causing exces-
. The LC-tank inductor itself occupies a 270 m 270 m sive FREF coupling. The spur level could be even lower if the
square. High-speed Digital (HSD) running at 600 MHz (di- layout is improved. The far-out spurs are vanishingly small and
vide-by-4 DCO clock) performs the dithering of the well below the floor of 80 dBc. Key measured performance
DCO varactors. The companion TMS320C54X DSP (used in parameters are summarized in Table I. The overall performance
cellular phones) digital baseband occupies 6 . This photo easily meets the Bluetooth spec.
dramatically illustrates the high cost (in terms of digital gates) By scanning the DCO feedback delay line adjustment voltage
of conventional RF components in high-density modern CMOS (Fig. 6), a 1–2 dB variation in phase noise was observed. Since

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ACKNOWLEDGMENT
The authors would like to thank the anonymous reviewer for
constructive comments that helped to improve quality of the
paper.

REFERENCES
[1] R. B. Staszewski, D. Leipold, C.-M. Hung, and P. T. Balsara, “A first
digitally controlled oscillator in a deep-submicron CMOS process for
multi-GHz wireless applications,” in Proc. 2003 IEEE Radio Frequency
Integrated Circuits (RFIC) Symp., sec. MO4B-2, June 2003, pp. 81–84.
[2] G. K. Dehng, C. Y. Yang, and J. M. Hsu et al., “A 900-MHz 1-V
CMOS frequency synthesizer,” IEEE J. Solid-State Circuits, vol. 35,
pp. 1211–1214, Aug. 2000.
[3] J. Dunning, G. Garcia, J. Lundberg, and E. Nuckolls, “An all-digital
phase-locked loop with 50-cycle lock time suitable for high performance
microprocessors,” J. Solid-State Circuits, vol. 30, pp. 412–422, Apr.
1995.
[4] R. E. Best, Phase Locked Loops: Design, Simulation and Applications,
3rd ed. New York: McGraw-Hill, 1997.
[5] M. H. Perrott, M. D. Trott, and C. G. Sodini, “A modeling approach
61
Fig. 21. Spurious tones generated by a synthesizer with the presented DCO
using 61 varactor randomization. Measured with Rohde&Schwarz (R&S) for - fractional-N frequency synthesizers allowing straightforward
FSIQ-7 signal analyzer. noise analysis,” IEEE J. Solid-State Circuits, vol. 37, pp. 1028–1038,
Aug. 2002.
[6] R. B. Staszewski, D. Leipold, and P. T. Balsara, “Just-in-time gain es-
timation of an RF digitally controlled oscillator for digital direct fre-
TABLE I quency modulation,” IEEE Trans. Circuits Syst. II, vol. 50, pp. 887–892,
MEASURED KEY SYNTHESIZER PERFORMANCE Nov. 2003.
[7] F. M. Gardner, “Interpolation in digital modems—part I: fundamentals,”
IEEE Trans. Commun., vol. 41, pp. 501–507, Mar. 1993.
[8] T. H. Lee and A. Hajimiri, “Oscillator phase noise: a tutorial,” IEEE J.
Solid-State Circuits, vol. 35, pp. 326–336, Mar. 2000.
[9] A. Hajimiri and T. H. Lee, “A general theory of phase noise in elec-
trical oscillators,” IEEE J. Solid-State Circuits, vol. 35, pp. 326–336,
Feb. 1998.
[10] , The Design of Low Noise Oscillators. Norwell, MA: Kluwer,
1999.
[11] J. C. Candy and G. C. Temes, “Oversampling methods for A/D
and D/A conversion,” in Oversampling Delta-Sigma Data Con-
verters. Piscataway, NJ: IEEE Press, 1991.
the oscillator performance significantly exceeds the require- [12] B. Miller and R. J. Conley, “A multiple modulator fractional divider,”
IEEE Trans. Instrum. Meas., vol. 40, pp. 578–583, June 1991.
ments of the targeted Bluetooth specification, the inaccuracy in [13] Y. Matsua et al., “A 16-bit oversampling A/D conversion technology
the DCO timing adjustments was considered inconsequential using triple integration noise shaping,” IEEE J. Solid-State Circuits, vol.
to warrant added software complexity. The presented results SC-22, pp. 921–929, Dec. 1987.
therefore use a nominal value of the adjustment voltage. This
[14] R. E. Radke, A. Eshraghi, and T. S. Fiez, “A 14-bit current-mode - 61
DAC based upon rotated data weighted averaging,” IEEE J. Solid-State
tradeoff should be revisited for more challenging standards, Circuits, vol. 35, pp. 1074–1084, Aug. 2000.
such as GSM. [15] A. Kajiwara and M. Nakagawa, “A new PLL frequency synthesizer with
high switching speed,” IEEE Trans. Veh. Technol., vol. 41, pp. 407–413,
Nov. 1992.

X. CONCLUSION
A novel digitally controlled oscillator (DCO)-based system
architecture for wireless RF applications has been proposed and
demonstrated. This enables to employ fully-digital frequency
synthesizers in the most advanced deep-submicrometer CMOS
Robert Bogdan Staszewski (M’94) received the
processes with almost no analog extensions. It allows cost-ef- BSEE (summa cum laude), the M.S.E.E., and Ph.D.
fective integration with the digital back-end onto a single silicon degrees from the University of Texas, Dallas in
die. The proposed combination of various circuit and architec- 1991, 1992, and 2002, respectively.
From 1991 to 1995, he was with Alcatel Network
tural techniques has brought to fruition a fully digital solution Systems, Richardson, TX, where he worked on
that has a fine-frequency resolution with low-spurious content Sonnet cross-connect systems. He joined Texas
and low phase noise. A 2.4-GHz DCO and its peripheral cir- Instruments, Dallas, TX, in 1995 where he is
currently a Senior Member of the Technical Staff. At
cuitry have been fabricated in a digital 0.13 CMOS process Texas Instruments, he has been engaged in advanced
and integrated with a DSP in order to investigate noise coupling. CMOS read channel development and since 1999,
This paper demonstrates feasibility and attractiveness of the dig- he has been involved in RF CMOS synthesizer design for short-distance
wireless and cellular phones. His research interests include RF transceivers,
itally controlled oscillator in a digital synthesizer architecture frequency synthesizers, high-speed and low-power digital circuits and system
for RF multigigahertz applications. implementation in a deep-submicrometer CMOS process.

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Dirk Leipold received the Diploma and Ph.D. Poras T. Balsara (S’83–M’85–SM’95) received the
degrees in physics from the University of Konstanz, L.E.E. diploma in electronics from The Victoria Ju-
Germany, in 1991 and 1995, respectively. bilee Technical Institute, Bombay, India in 1980, the
From 1991 to 1995, he was with the Paul Scherrer B.E. degree from the University of Bombay, India, in
Institute, Zurich, Switzerland, where he worked 1983, and the M.S. and Ph.D. degrees in computer
on Smart pixel optoelectronics. In 1995, he joined science from Pennsylvania State University, Univer-
Texas Instruments, Germany, where he was involved sity Park, in 1985 and 1989, respectively.
in RF process integration, device characterization, Currently, he is a Professor of Electrical Engi-
and modeling, and in the development of RF-CMOS neering with the Erik Jonsson School of Engineering
technologies on high-resistivity substrates. From and Computer Science, The University of Texas at
1998 to 1999, he represented Texas Instruments Dallas, Richardson. His research interests include,
in the ETSI Hiperlan2 Committee, where he was Editor for the PHY layer VLSI design, design of energy efficient digital circuits and systems, computer
technical specification. In 1999, he moved to Texas Instruments, Dallas, where arithmetic, application-specific architecture design, and reconfigurable com-
he is currently Manager of the Digital Radio Processor Architecture Group. His puting. He has published several journal and conference papers in these areas.
research interests include advanced RF architectures, nanometer scale CMOS
process, and quantum electronics.

Khurram Muhammad received the B.Sc. degree

from the University of Engineering and Technology,
Lahore, Pakistan, in 1990, the M. Eng. SC. degree
from the University of Melbourne, Parkville,
Victoria, Australia, in 1993, and the Ph.D. degree
from Purdue University, West Lafayette, IN in 1999.
From 1990 to 1991 and 1993 to 1994, he worked
with Carrier Telephone Industries, Islamabad,
Pakistan, in Research and Development where he
was involved in the development of board level
designs for rural and urban telecommunication
projects. From 1994 to 1995, he was a Research Associate, Department of
Electronic Engineering, Ghulam Ishaq Khan Institute of Engineering Science
and Technology. In 1995, he was with Hong Kong University of Science and
Technology, Kowloon, where he developed fast simulation techniques for
DS/CDMA systems in multipath fading. Since 1999, he has been working at
Texas Instruments Inc., Dallas.

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