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Physical Design Training

CONSTRAINTS PREPARATION
Agenda

 Constraining the Design

Introduction to synthesis
Optimization Constraints
Timing Constraints
Design Rule Constraints (DRC’s)
Environmental Conditions
 Overview

Constraints are used to influence the design implementation tools

including the synthesizer, and place-and-route tools.
 They allow the design team to specify the design performance
requirements and guide the tools toward meeting those requirements.
The implementation tools prioritize their actions based on the
optimization levels of synthesis, specified timing, assignment of pins, and
grouping of logic provided to the tools by the design team.
Synthesis Transformations

Synthesis = Translation + Logic optimization + gate mapping (Technology dependent)

1) Translate (HDL Compiler)

Timing Constraints 3) Optimize + map

Create_clock ….. (Compile_ultra)
Set_clock_uncertainity .. GTech
2) Constraint mapped-gate level netlist
(No Timing info)

Technology- specific
mapped gate level netlist
(Timing info )
Types of Synthesis
Logical Synthesis : (WLM Based Synthesis)

• wire load model is being used to calculate the length, timing , area and power
consumed by the nets which are interconnecting the gates and macros in a
design . The results may have huge deviation to the result of final chip.

Physical Synthesis : (Physical data based Synthesis)

• A coarse placement and virtual routing is performed, based on the physical

constraint provided in the design, giving the most likely wire length of the nets,
interconnecting the gates and macros in a design and thus have less deviation in
the timing, area and power to the result of final chip.
Major Design Optimization Constraints

Fig: Major Design optimization constraints

7
Optimization Constraints (Goals)

A design is constrained for

 Timing

 Area

 Power

8
 Optimization for Area

 Before applying constraint, always verify that the current design is your
intended design

 When area constraint is reached, area optimization will quit

 If area constraint is not set, there will be minimal area optimization

dc_shell> current_design TOP_CHIP

dc_shell> set_max_area 5000

 Is set_max_area 0 acceptable ??

9
 Optimization for Area
 Is set_max_area 0 acceptable ??

 If it is tightly constrained like 0 , area optimizations will be performed, till the

time, timing of the design starts degrading against its constrained value

 As timing constraints have higher priority then area constraints, So it will try
to optimize area till the timing starts worsening. Having area constraint as 0
will increase run time if timing constraints is not much aggressive
 Optimization for Timing
There are 4 types of Data paths:

 Input pin/port to register

 Register to register

 Register to output pin/port

 Input to output pin/port

Fig. showing the 4 types of Path
 Constraining Reg to Reg

 The reg to reg paths starts at the clock pin of the sequential element and end
at the data input of a sequential element

 The path is constrained for clock_uncertainty, clock_latency and

clock_transition
 Defining a clock

 For a synchronous designs, we have to define a clock. While designing a clock,

we should atleast have a clock source port/pin and a clock period

 By default, the clock rises at 0ns and has 50 % duty cycle

 During synthesis, the clock net is not “buffered up ”, although it has a high
fanout of flipflops connected by clock/enable pin

 During synthesis, the clock is represented as “ideal”- having infinite driving

capability, zero rise/fall transition times, zero skew, zero insertion delay or
latency
 Defining a clock cont ..

 If a design has positive and a negative flops, then define duty cycle also. We can also
define rise time, fall time, clock name and offset.

create_clock –name clk_1 –period 2 [get_ports clk]

 Modeling a clock Tree

 During synthesis, we don’t actually have a real, propagated clock. It is available only
after Clock tree synthesis (CTS) stage

 So in synthesis, we model a clock which would be as close as similar to the propagated

clock available after CTS

 We model the clock by constraining it by certain parameter’s like uncertainty, skew,

transition time and latency at the Placement and routing stage
 Modeling a clock uncertainty

 Clock uncertainty is the time difference between the arrivals of clock signals at
registers in one clock domain or between domains

 It is a way to incorporate a margin of error in the design to account for possible

variances such as Jitter in the clock propagation times in the post-layout design

Difference In the
Delay
 Cont…

 We can specify it by using command:

set_clock_uncertainty –set up 10 [get_clock clk]

Prelayout clock uncertainity = clock skew + Uncertainity is placed on this
jitter + margin clock object
 Before clock tree synthesis, clock uncertainty is caused by clock jitter, margin, and skew
 After clock tree synthesis, with propagated latency, the tool separately accounts for uncertainty resulting
from different propagation delays through the clock tree. So after CTS, uncertainty comprises only of clock
jitter and margin

Eg:
During pre-layout: set_clock_uncertainity 10 clk
During post-layout: set_clock_uncertainity 5 clk
 After post-layout tool calculates the skew between the branches, so skew value is removed from
set_clock_uncertainity command
 Example for clock_uncertainity

 Let we have executed the following commands

create_clock -period 10 [get_ports clk]

set_clock_uncertainity -setup 0.4 [get_clocks clk]

 Modeling clock latency (Insertion Delay)

Clock latency = source latency + network latency

 Source Latency: It is the time taken by the clock signal to propagate from its ideal
waveform origin point to the clock definition point in the design

 Network Latency: It is the time taken by the clock signal to propagate from the clock
definition point in the design to the clock pin of the sequential device

Fig : source latency and network latency

 Modeling clock latency cont ..

 It is the delay that is assumed to exist between the clock source and the flip-flop clock
pin

 It is not the actual delay, but the delay specified by the user, to account for the clock
delay which will be auto calculated after CTS

 The timing analyzer uses this information to determine clock arrival times during
synthesis
 During pre-layout and post-layout, the value for source latency remains the same
 During pre-layout, the clock is ideal, we need to model network delay but after the
clock is propagated at post-layout, we don’t have to define or estimate network delay as
we have realistic values. Define propagated clock as set_propagated_clock clk
 Cont..

 Command for clock latency is:

set_clock_latency -source 2.0 [get_clocks CLK]

#It assign source latency as 2.0

 If we do not use –source , then it represent network latency, eg

set_clock_latency 2.0 [get_clocks CLK]

#It assign network latency as 2.0

Once CTS is complete i.e. post CTS, the actual delay from the clock root pin to the clock
sink pin can be calculated. Then this delay is called insertion delays at that point
 Clock Transition

 The transition time of a net is the longest time required for its driving pin to change
logic value

 Clock Transition
During pre-layout: set_clock_transition 0.30 clk
During post-layout: We don’t have to define it as we have realistic values of propagated
clock
 Constraining input paths (input port to reg)

 The input pin/port to reg paths, starts at the input pin/port of and end at the data
input of a sequential element

 The input data at pin “A” should arrive after TCLKTOQ + TM. This is the minimum
amount. of time to specify as input delay
 Constraining output paths (Reg to output port)

 The reg to output pin/port paths, starts at the output pin of the sequential element
and end at the output pin/port

 The output delay at pin “A” should be estimated as TN + TSETUP. This is external logic’s
setup requirement relative to the clock.
 Constraining combinational path : Virtual clocks

 Virtual clocks do not have any physical existence in a design

 They are used as a reference to module for input and output delays. Thus they are
needed to constrain the input ports to register timing paths and reg to output port
timing paths

 These are local to a design

 To define a virtual clock , just give create_clock without any generation point
create_clock -name clk_vrt –period 10

 The waveform of virtual clock is same as real clock. We should also define the latency
of virtual clock as same as real clock
 Summary: Commands Covered

# area constraint
set_max_area 5000

#Timing constraint (SDC constraints)

create_clock –name clk_1 –period 2 [get_ports clk]
create_clock -name clk_vrt –period 10
set_clock_uncertainty –setup 10 [get_clock clk]
set_clock_latency -source 2 [get_clocks clk]
set_clock_latency 2 [get_clocks clk]
set_clock_transition 0.30 clk
set_propagated_clock clk
set_input_delay 1.2 –clock clk [all_inputs]
set_output_delay 1.2 –clock clk [all_output]
 Design Rule Constraints

 Maximum Transition Time

 Maximum Fanout

 Maximum Capacitance

 Minimum Capacitance

• Cell Degradation
 Design Rule Constraints (cont.)

 Maximum Fanout
• Most technology libraries place fanout restrictions on driving pins, creating an
implicit fanout constraint for every driving pin in designs using that library
• Design Compiler models fanout restrictions by associating a fanout_load attribute
with each input pin and a max_fanout attribute with each output (driving) pin on a
cell.

Fig. showing fanout load at the pin z

 Design Rule Constraints (cont.)

 Maximum Capacitance
• The maximum capacitance design rule constraint allows you to control the
capacitance of nets allows you to control the capacitance of nets directly. (The design
rule constraints max_fanout and max_transition limit the actual capacitance of nets
indirectly)

 Minimum Capacitance
• The min_capacitance design rule specifies the minimum load a cell can drive. It
specifies the lower bound of the range of loads with which a cell has been
characterized to operate
 Design Rule Constraints (cont.)

 Cell degradation
 Some logic libraries contain cell degradation tables
 The tables list the maximum capacitance that can be driven by a cell as a
function of the transition times at the inputs of the cell.
 The cell_degradation design rule specifies that the capacitance value for a net is
less than the cell degradation value
 set_cell_degradation command sets the cell_degradation attribute to a specified
value on specified input ports.
 Maximum Transition time
• The maximum transition time for a net is the longest time required for its
driving pin to change logic values. Typically fixed by buffering the output of
driving gate.
 Precedence of Design Rule Constraints

 Minimum Capacitance

 Maximum Transition

 Maximum Fanout

 Maximum Capacitance

 Cell degradation
 Commands to constraint DRCs

 set_max_transition
• Set the maximal transition time (low-high and high-low) for a port or a design. The library defines the
transition measure points (i.e: 10%-90%, 20%-80%)
• Delay of library cells as well as their output transition depends on this value. Also, setup and hold
time of sequential cells is affected by it
 set_max_fanout
• In all libraries a cell input has a fanout load value. In most cases it’s 1, but can be a different value
• Compile attempts to ensure that the sum of the fanout_load attributes for input pins on nets driven by
the specified ports or all nets in the specified design is less than the given value
 set_max_capacitance
• Limits the allowed capacitance on input, output or bidirectional ports and/or designs
Summary: Commands Covered

 set_max_transition

 set_max_fanout

 set_max_capacitance

 Set_min_capacitance

 Set_cell_degradation
Design Environment

 Design to work expectedly, define certain environmental condition on which the

library/design is characterized :

• Operating Conditions

• Wire Load Models (WLM)

• System Interface Characteristics

Operating Conditions

 Operating Conditions are operating temperature, supply voltage and manufacturing

process

 These three factors together provide minimum and maximum cell and wire delays that,
depending on which combination of PVT is chosen for optimization

 The three choices of operating conditions for optimizing their design – worst case, best
case and typical case operating conditions
Defining Operating Conditions

 Select operating condition with following command:

set_operating_conditions –analysis on_chip_variation -min BCCOM -max WCCOM

 To see the operating conditions that are defined for the current design, use the
report_design command
Wire Load Model (WLM)
 A wire load model is a statistical model, provided by vendor
 A wire load model calculates parasitic R and one C for each net, based on the net’s
fanout number

 Path delays are based on cell delays as well as net delays

 Cell Delay = f (input transition, Cnet + Cpin)
 Net Delay = f (Rnet, Cnet + Cpin)

 Synthesis tool perform following steps:

• Determines the fanout of the net
• Looks up the length in the wire load model
• Calculates the resistance and capacitance by multiplying the length by the
respective coefficient in the wire load model
 Wire load Model defined in a lib :

 Synthesis tool perform following steps:

• Determines the fanout of the net

• Looks up the length in the wire load model

• Calculates the resistance and capacitance by multiplying the length by the

respective coefficient in the wire load model

 System Interface Characteristics

 Loads on Input and Output Ports

 Drive Characteristics for Input Ports

 Information about the external drive strength and the loading at each input port needs
to determine the delay and transition time characteristics of incoming signals

 Drive strength is the reciprocal of the output drive resistance

 Transition delay at an input port is the product of the drive resistance and the
capacitance load of the input port
 Drive Characteristics for Input Ports

 set_driving_cell command is used to specify drive characteristics on ports that are

driven by cells in the logic library

 set_drive or set_input_transition command is used to set the drive resistance on the

top-level ports of the design

current_design top_level_design
set_drive 1.5 {I1 I2}
current_design sub_design2
set_driving_cell -lib_cell IV {I3}
set_driving_cell -lib_cell AN2 -pin Z -from_pin B {I4}
 Effect of Input Transition Time

 Rise and fall transition times on an input port affect the cell delay of the input gate
 Modeling Input Transition

 Command used to model input Transition at Chip level :

set_input_transition 0.12 [get_ports A]

 Command used to model input Transition at Block level :

set_driving_cell –lib_cell FD1 –pin Qn [get_ports A]
Loads on Input and Output Ports

 Use the set_load command to set a capacitive load value on input and output ports of
the design. Following command sets a load of 30 on output pin out1
set_load 30 {out1}

 Use set_fanout_load command to model the external fanout effects by specifying the
expected fanout load values on output ports
set_fanout_load 4 {out1}
Summary: Commands Covered

 set_operating_conditions –analysis on_chip_variation

 report_design

 set_driving_cell

 set_drive

 set_input_transition

 set_load

 set_fanout_load
Power constraints

• These commands apply when multi-voltage islands

are present in a design.
• create_voltage_area -name name
• set_level_shifter_strategy [-rule rule_type]
• set_level_shifter_threshold [-voltage float]
• set_max_dynamic_power power [unit]
• set_max_leakage_power power [unit]
 Thank you
( Some of the constraints will be covered in STA )
STATIC TIMING ANALYSIS
Agenda

 STA

Basic Flow

Timing verification

On chip variation

Timing closure & Analysis

Static Verification Flow
What/Why is Static Verification?

Static verification:
 Verifies timing and functionality
The STA is static since the analysis of the design is carried out statically and
does not depend upon the data values being applied at the input pins.
Uses formal, mathematical techniques instead of vectors
 Does not use dynamic logic simulation
The purpose of static timing analysis is to validate if the design can operate
at the rated speed.
Static Timing Analysis Flow
Required Input Files
Read and Constraints
Basic timing checks_Setup and hold definition

• Data must become valid and stable at least one setup time before being
captured by flip-flop.

Tlaunch + Tck2q + Tdp < Tcapture + Tcycle - Tsetup

• Data remains stable for a minimum time as required by capture flip-flop. (Hold
Check)

Tlaunch + Tck2q + Tdp > Tcapture + Thold

F-F SETUP/HOLD CHECK AND REPORT

Setup Check
CONTD..

Hold check
Input to Flip-flop Path Setup/hold check

Setup check
create_clock -name VIRTUAL_CLKM -period 10 -waveform {0
5}
set_input_delay -clock VIRTUAL_CLKM \
-max 2.55 [get_ports INA]
CONTD..

set_input_delay -clock VIRTUAL_CLKM -min 1.1 [get_ports INA]

Flip-flop to Output Path setup and hold check

set_output_delay -clock VIRTUAL_CLKP \

-max 5.1 [get_ports ROUT]
set_load 0.02 [get_ports ROUT]
CONTD..

set_output_delay -clock VIRTUAL_CLKP -min 2.5 [get_ports ROUT]

 Input to Output Path setup and hold check

set_input_delay -clock VIRTUAL_CLKM \

-max 3.6 [get_ports INB]
set_output_delay -clock VIRTUAL_CLKM \
-max 5.8 [get_ports POUT]
CONTD..

>set_load -pin_load 0.15 [get_ports

POUT]
>set_output_delay -clock
VIRTUAL_CLKM -min 3.2 [get_ports
POUT]
>set_input_delay -clock VIRTUAL_CLKM
-min 1.8 [get_ports INB]
>set_input_transition 0.8 [get_ports
INB]
Multicycle Paths

In some cases, the combinational

data path between two flip-flops can take more
than one clock cycle to propagate through the
logic.
In such cases, the combinational path
is declared as a multicycle path. Even though
the data is being captured by the capture flip-
flop on every clock edge, we directSTA that the
relevant capture edge occurs after the specified
number of clock cycles.

>create_clock -name CLKM -period 10

[get_ports CLKM]
>set_multicycle_path 3 -setup -from [get_pins
\UFF0/Q] -to [get_pins UFF1/D]

>set_multicycle_path 2 -hold -from [get_pins

UFF0/Q] -to [get_pins UFF1/D]
Setup check hold check
False Paths
It is possible that certain timing paths are not real (or not possible) in the actual functional operation of
the design. Such paths can be turned off during STA by setting these as false paths. A false path is
ignored by the STA for analysis and To save run time

>set_false_path -from [get_clocks SCAN_CLK] -to [get_clocks CORE_CLK]

>set_false_path -through [get_pins UMUX0/S]
>set_false_path -through [get_pins SAD_CORE/RSTN]]
>set_false_path -to [get_ports TEST_REG*]
>set_false_path -through UINV/Z -through UAND0/Z

Specifying delays

>set_max_delay –from port1 –to port2

>set_min_delay –from port1 –to port2
Half-Cycle Paths
If a design has both negative-edge triggered flip-
flops (active clock edge isfalling edge) and
positive-edge triggered flip-flops (active clock
edge is rising
edge), it is likely that half-cycle paths exist in the
design.
Asynchronous timing checks

A removal timing check ensures that there A recovery timing check ensures that there is a
is adequate time between an active clock minimum amount of time between the
edge and the release of an asynchronous asynchronous signal becoming inactive and the next
control signal. The check ensures that the active clock edge. In other words, this check ensures
active clock edge has no effect because the that after the asynchronous signal becomes inactive,
asynchronous control signal remains active there is adequate time to recover so that the next
until removal time after the active clock active clock edge can be effective.
edge.
Timing across different Clock Domains

Slow to Fast Clock Domains

create_clock -name CLKM \

-period 20 -waveform {0 10} [get_ports CLKM]
create_clock -name CLKP \
-period 5 -waveform {0 2.5} [get_ports CLKP]
Fast to Slow Clock Domains

create_clock -name CLKM \

-period 20 -waveform {0 10} [get_ports
CLKM]
create_clock -name CLKP \
-period 5 -waveform {0 2.5} [get_ports CLKP]
Non-Integer Multiples clocks
Data to Data Checks

 Setup and hold checks can also be applied

between any two arbitrary data pins, neither
of which is a clock. One pin is the
constrained pin, which acts like a data pin of
a flip-flop, and the second pin is the related
pin, which acts like a clock pin of a flip-flop.
 The data to data setup checks are also
referred to as zero-cycle checks or same-
cycle checks

>set_data_check -from SDA -to SCTRL -setup 2.1

>set_data_check -from SDA -to SCTRL -hold 1.5
Non-Sequential Checks

 A non sequential check is a check between two pins, neither of which is a clock. The check specifies how long the
data on the constrained pin must be stable before and after the change on the related pin.
 A non-sequential check is similar to a data to data check described , though there are two main differences.
 In a non-sequential check, the setup and hold values are obtained from the standard cell library, where the setup
and hold timing models can be described using a NLDM table model or other advanced timing models. In a data to
data check, only a single value can be specified for the data to data setup or hold check.
 The second difference is that a non-sequential check can only be applied to pins of a cell, whereas a data to data
check can be applied to any two arbitrary pins in a design.
pin (WEN) {
timing () {
timing_type: non_seq_setup_rising;
intrinsic_rise: 1.1;
intrinsic_fall:1.15;
related_pin: “D0”;
} timing () { Library spec for non seq checks
timing_type: non_seq_hold_rising;
intrinsic_rise: 0.6;
intrinsic_fall:0.65;
related_pin: “D0”;
}
}
Clock Gating Checks

A clock gating check occurs when a gating signal can control the path of a clock
signal at a logic cell.
condition for a clock gating check is that the clock that goes through the cell
must be used as a clock downstream.
Another condition for the clock gating check applies to the gating signal.The
signal at the gating pin of the check should not be a clock or if it is a clock, it
should not be used as a clock downstream.

There is two types of clock gating

Active high: Occurs when the gating cell has an and or a nand function.
Active low: Occurs when the gating cell has an or or a nor function.
Latch based design (Time borrowing)

In latch based designs timing check has to be done based on Time borrowing technique (Cycle
Stealing). Here one edge of the clock makes the latch transparent that is called Opening
edge. Other edge of the clock makes the latch closes the data i.e. called Closing edge.

Time borrowing: If the data is ready at latch input before the active edge of the clock then as the
latch is transparent with the active part of the clock, it can pass the data later the active edge of the
clock. Here it is borrowing(stealing some part of the clock cycle) some time i.e called Time
borrowing Technique.

Case 1
Case 2
Case 1:
Please observe the explanation based on case 1.If the data DIN is available prior to the
opening edge of the latch at 10ns, data flows to the output of the latch as it opens. The timing
behavior is modeled exactly as like flip-flop. The opening edge only captures the data and the
same edge launches the data to the next start point of path.

Case 2:
Please observe the explanation based on case 2. If the data DIN is available after the
opening edge and before closing edge of the latch (i.e while the latch is transparent), the
output of latch only used as the launch point for the next path.Here the time is borrowed from
the available clock cycle is nothing but time borrowing. I can say that the available time is less
for capturing.

Case 3:
If the data DIN is available after closing edge of the latch is a timing violation.

Observation:
So based on this i can say that the timing check happens with respect to closing edge of
the clock cycle as like these three cases
Case Analysis

 Case analysis allows timing analysis to be performed using logic constants or logic
transitions (rising or falling) on ports or pins, to limit the signal propagated
through the design.
 Case analysis is a path-pruning mechanism and is most commonly used for timing
the device in a given operational configuration or functional mode.

set_case_analysis 0 [get_ports
"SCAN_MODE"]
Mode Analysis
Library cells and timing models can have operating modes defined in them, such as read and write
modes for a RAM cell. Each mode has an associated set of timing arcs that PrimeTime analyzes when
that mode is active.
Cell modes
Cell modes are defined in a timing model or library cell, such as the read and write modes for a RAM
cell. Design modes are user-defined modes that exist at the design level, such as normal and test
modes
Design modes
You can map a design mode to a set of cell modes in cell instances or to a set of paths.
examples

>map_design_mode read -from Raddr

-through U1/A
>map_design_mode write -from
Waddr -through U1/B
On-Chip Variations
 Due to process variations, identical MOS transistors in different portions of the die may not have similar
characteristics. These differences are due to process variations within the die.

 These differences can arise due to many factors, including

i. IR drop variation along the die area affecting the local power
supply.
ii. Voltage threshold variation of the PMOS or the NMOS device.
iii. Channel length variation of the PMOS or the NMOS device.
iv. Temperature variations due to local hot spots.
v. Interconnect metal etch or thickness variations impacting the interconnect
resistance or capacitance.

 On-Chip Variations (OCV) and these variations can affect the wire delays and cell delays in different portions of
the chip. The OCV effect is typically more pronounced on clock paths as they travel longer distances in a chip.
Derating setup timing check for OCV

From the figure,

LaunchClockPath = 1.2 + 0.8 = 2.0
MaxDataPath = 5.2
CaptureClockPath = 1.2 + 0.86 = 2.06
Tsetup_UFF1 = 0.35
This results in a minimum clock period of:
2.0 + 5.2 – 2.06 + 0.35 = 5.49ns
set_timing_derate -early 0.9
set_timing_derate -late 1.2
set_timing_derate -late 1.1 -cell_check
With these derating values, we get the following for setup
check:
LaunchClockPath = 2.0 * 1.2 = 2.4
MaxDataPath = 5.2 * 1.2 = 6.24
CaptureClockPath = 2.06 * 0.9 = 1.854
Tsetup_UFF1 = 0.35 * 1.1 = 0.385
This results in a minimum clock period of:
2.4 + 6.24 – 1.854 + 0.385 = 7.171ns
Derating hold timing check for OCV
LaunchClockPath = 0.25 + 0.6 = 0.85
MinDataPath = 1.7
CaptureClockPath = 0.25 + 0.75 = 1.00
Thold_UFF1 = 1.25
implies
0.85 + 1.7 – 1.00 - 1.25 = 0.3n >=0
set_timing_derate -early 0.9
set_timing_derate -late 1.2
set_timing_derate -early 0.95 -cell_check

LaunchClockPath = 0.85 * 0.9 = 0.765

MinDataPath = 1.7 * 0.9 = 1.53
CaptureClockPath = 1.00 * 1.2 = 1.2
Thold_UFF1 = 1.25 * 0.95 = 1.1875
Common clock path pessimism: 0.25 * (1.2 - 0.9) = 0.075
0.765 + 1.53 – 1.2 - 1.1875 + 0.075 = -0.0175ns
Hold violated

In general, the hold timing check is performed at the best-case fast PVTcorner. In such a scenario, no
derating is necessary on the early paths, as those paths are already the earliest possible.
Clock Reconvergence Pessimism Removal (CRPR).

In the setup check above, there is a discrepancy since the common clock path of the clock tree,
with a delay of 1.2ns, is being derated differently for the launch clock and for the capture clock.
This part of the clock tree is common to both the launch clock and the capture clock and should not
be derated differently.
The pessimism caused by different derating factors applied on the common part of the clock tree
is called Common Path Pessimism (CPP) which should be removed during the analysis.

CPP = LatestArrivalTime@CommonPoint - EarliestArrivalTime@CommonPoint

This implies a CPP of: 1.44 - 1.08 = 0.36ns

>setAnalysisMode –crpr –onChipVariation

>set_global \timing_remove_clock_reconvergence_pessimism true
Advanced on chip variation analysis
Advanced on-chip variation (AOCV) analysis reduces unnecessary pessimism by taking the
design methodology and fabrication process variation into account. AOCV determines
derating factors based on metrics of path logic depth and the physical distance traversed by
a particular path.

Graph-Based AOCV Analysis

Graph-based AOCV analysis is a fast, design-wide analysis performed during the update_timing
command. It allows designers to exploit reduced derating pessimism across the entire design to
reduce silicon area and improve design performance.
Path-Based AOCV Analysis
If violations still remain after completion of graph-based AOCV analysis, you can reduce pessimism
and improve the accuracy of results by invoking path-based AOCV analysis, which analyzes each path
in isolation from other paths
The following example of an AOCV file sets an early AOCV table for the whole design, which
applies to all cell and nets:

The following example of an AOCV file sets

an early AOCV table for the whole design,
which
applies to all cells with the voltage of 1.2
volts:
Parametric On-Chip Variation

PrimeTime ADV parametric on-chip variation (POCV) models the delay of an instance as a function
of a variable that is specific to the instance.
POCV provides the following:
• Statistical single-parameter derating for random variations
• Single input format and characterization source for both AOCV and POCV table data
• Nonstatistical timing reports
• Limited statistical reporting (mean, sigma) for timing paths
• Compatibility with existing PrimeTime functionality
PrimeTime Timing Models Support

Timing extraction plays an important role in hierarchical top-down flow and

bottom-up IP authoring flow by reducing the complexity of timing verification
and by providing a level of abstraction which hides the implementation details of
IP blocks.
 Three most desired features in timing extraction are accuracy, efficiency, and
usability. The model must preserve the timing behavior of the original circuit and
produce accurate results.
 Quick Timing Model (QTM)
 Extracted Timing Model (ETM)
 Interface Logic Model (ILM)
QTM
 A temporary model used early in the design cycle for a block that has no netlist
available. QTM creation is faster than writing ad-hoc model . The model contains
both min and max time arc for setup and hold checks.
 Check consistency between blocks’ constraints and updates boundary constraints
(after each iteration of synthesis) The netlist used for QTM generation can be easily
generated (low effort RTL mapping) since existence or absence of timing arc is
independent from the
logic/physical design.
 Inputs
Constraints (SDC)
Configuration file
Header file
The QTM model is generated using Black Box commands. Using this command set
allows to define timing arcs and electrical data (i.e. output driver, input load,…)
create_qtm_model
ILM
ILMs embody a structural approach to model generation, where the original gate-level netlist is
replaced by another gate-level netlist that contains only the interface logic of the original netlist.

Interface logic contains all circuitry leading from I/O ports to edgetriggered registers called
interface registers. The clock tree leading to interface registers is preserved in an ILM. Logic that is
only contained in register-to-register paths on a block is notin an ILM.
create_ilm –block_scope –verification_script -parasitics_options {spef
input_port_nets constant_nets}
ETM

Extracted timing models differ from ILMs

in that the interface logic for a block is
replaced by context-independent timing
relationships between pins on a library cell.

 The extracted library cell contains timing

arcs between external pins. Internal pins are
introduced only when there are clocks
defined on internal pins of the design
Paths Failing Timing?
In this section, we provide examples that highlight the critical aspects that a designer needs to focus on during
debugging of STA results

1. No Path Found
i. the timing path is broken, or
ii. the path does not exist, or
iii. there is a false path
2. Clock Crossing Domain

3. Inverted Generated Clocks

4. Missing Virtual Clock Latency

5. Large I/O Delays

6. Incorrect I/O Buffer Delay/ Incorrect Latency Numbers

7. Half-cycle Path/ Large Delays and Transition Times/ Missing Multicycle Hold

8. Path Not Optimized

9. Validating Timing Constraints
Thank you