Hardware Verification using DFT & TetraMax

CS 6745 - Testing and Verification of Digital Circuits

Anh Luong & Andrzej Forys

1 Objective
This project0 s goal was to combine our new knowledge of hardware verification with our previous VLSI experiences
including fabrication and post silicon testing. Throughout the Testing and Verification of Digital Circuits course, we
learned the algorithms for fault detection and what happens behind the scenes of test pattern generators and verifiers.
Given the Synopsys tools designed for this type of testing, Design for Test (DFT) Compiler and TetraMAX, our goal
was to learn about the tools, determine the additional hardware and software needed for functionality, and apply them
to previously designed hardware in Verilog.

2 Introduction
DFT and TetraMAX tools are useful for testing and verification of pre and post silicon digital circuits, including
finding errors in logic and fabrication. Although these can be used for both sequential and combinational circuits,
the verification of sequential systems requires the use of Scan Flip-Flops (FF). In this report we will cover the basic
designs of Scan FFs, scan chain insertion using DFT, and preparing library files and verilog files for Automatic Test
Pattern Generation (ATPG) with TetraMAX.

The referenced report by Edwin Jose covers the basics of using DFT and TetraMAX to perform Full Scan versus
Partial Scan Analysis [1]. The tools and commands used in that report have since been updated several versions and it
is no longer up to date. The workflows have also slightly changed. This report will also provide new library files and
scripts to use the latest versions of the tools.

3 Background
Part of the verification process requires the use of the Synopsys Design Compiler (DC). Although our scripts and
library can be used to first synthesize the design, we will not cover the DC details because we assume the user has
common knowledge of this tool. This also applies to the process of creating cells that are used to generate the library.
Refer to ”Digital VLSI Chip Design with Cadence and Synopsys CAD Tools” for more information about these pro-
cedures [2].

These are the versions of the tools we have been using for this project:

DC and DFT Compiler Versions D-2010.03-SP2

TetraMax Version F-2011.09-SP4 (S13 Directory, script updated for new installation)
TetraMax Version W-2004.12-SP4 (S12 Directory)

4 Synopsys Tools
Synopsys has two main tools used for this type of testing: the DFT Compiler and TetraMAX. These tools can test
faults in both combinational and sequential logic [3]. In the case of sequential logic that uses FFs, a special Scan
FF needs to be developed. This gives the tools or users direct control over the values inside registers. It allows for
propagating values into and out of the data path [4].

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4.1 DFT Compiler
The DFT Compiler uses additional features on top of the standard DC to regenerate the netlist with Scan FFs. It
modifies the structural Verilog produced through DC by replacing standard FFs with Scan FFs. The tool is smart
enough to update all the cells and nets associated with the new design. It runs its own test design rule checking
(DRC) and is able to fix several clock, reset, and scan signal routing errors with AutoFix. The DFT tool has access
to DFTMAX which allows it to create the ATPG test protocol and compressed netlist for the entire design, which is
used by TetraMAX. Along with providing circuit size, number of nets, and timing delay analysis before and after scan
insertion, the tool provides scan coverage details such as how many faults are testable and what types of faults are
encountered [3]. Figure 1 shows the procedure flow used by the DFT Compiler.

Figure 1: Design procedure in DFT Compiler [5].

4.2 Design Vision (DV)

Synopsys also has a GUI based DFT tool called Design Vision which lets the designer view a full schematic of his or
her structural Verilog before and after Scan FF replacement. It can be used as an interactive command window and a
schematic viewer. This can be useful in finding DRC errors, because the tool can show specific failure locations in the
schematic. When using the tool to only view schematics of the netlists generated by DFT, a structural Verilog file is
needed along with the test protocol defining STIL file (.spf) [3]. Figure 2 shows a section of our scan inserted design.

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 Figure 2: Scan chain in processor controller.

4.3 TetraMAX ATPG

Another Synopsys tool, called TetraMax ATPG, is used to generate the test patterns for fault analysis. This tool will
determine all testable faults along with those that are unreachable or untestable due to issues like redundancy. It will
generate a testbench compatible file corresponding to all the generated patterns. Although in some cases similar to
the fault analysis done by the DFT Compiler, its main difference is the ability to generate test patterns for the entire
design, test individual faults, and show the propagation results to the user [4]. Figure 3 shows the TetraMAX ATPG
process flow.

Figure 3: Process of TetraMAX ATPG [6].

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5 Verification Procedures
5.1 Scan Flip-Flop Design
The difference between ordinary FFs and Scan FFs is that the latter has more than one data input pin which is activated
during test modes. There are two types of Scan FFs we considered: the kind that share a clock with the rest of the
integrated circuit (IC) while utilizing a 0 scan enable0 signal to activate the 0 scan input0 and the kinds that use a separate
0 scan clock0 to switch between data sources [3]. Our implementation is based on the design using the scan enable

signal.

The simplest way of designing Scan FFs like this is to add a multiplexer (MUX) on the data input line. The scan
enable signal is the select bit on the MUX and it controls whether the FF receives its input from the data path or
scan input. We designed 3 slightly different Scan FFs for this project. The first used a FF and a MUX from our own
cell library. The second used cells from the UofUDigital v 2 library accessible to VLSI students [2]. The third was
modeled after a standard design found in [7].

The schematic, layout, and analog extracted views need to be created for the scan cell before starting library gen-
eration. Figure 4 shows the schematic for the standard design from [7]. When finished simulating the schematic,
it0 s useful to independently test a behavioral view to verify a properly working Scan FF. Next, once Layout Versus
Schematic Checking (LVS) shows that netlists match between the schematic and layout, the analog extracted view can
be generated [2]. This will later be used to generate the cell library file. The layout based on our own library can be
seen in Figure 5.

Figure 4: Schematic of Scan FF based on design in [7].

Figure 5: Scan FF layout based on our library.

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5.2 Library Modifications
There are a few additions that need to be made to the Scan FF cell in the library before the .db file is produced. These
will occur after the 0 cad-alf2lib0 command when following the Encounter Library Characterization (ELC) process in
[2].

A special test cell() needs to be defined in the scan cell to let the tools know how to use it. It0 s inserted between
the initial ff() declaration and the first pin() declaration. It needs to contain all the cell pins and their corresponding
direction and signal type. The direction indicates input/output/tri-state while the signal type is used for the test scan
signals. Notice that the ff() declaration is also included with its next state and clock signals. The function designation
refers to the generated IQ and IQN signal names for the output of the FF. Below is a snippet of the library showing the
additional test cell() information.
test cell () {
p i n (D) {
direction : input ;
}
p i n (CLK) {
direction : input ;
}
pin ( SI ) {
direction : input ;
signal type : test scan in ;
}
p i n ( SE ) {
direction : input ;
signal type : test scan enable ;
}
f f ( IQ , IQN ) {
n e x t s t a t e : ”D” ;
c l o c k e d o n : ”CLK ” ;
}
p i n (Q) {
direction : output ;
f u n c t i o n : ” IQ ” ;
signal type : test scan out ;
}
p i n (QB) {
direction : output ;
f u n c t i o n : IQN ;
signal type : test scan out inverted ;
}
}
Another addition to the cell is a nextstate designation for pins associated with 0 scan in0 and 0 scan enable.0 See the
format below:
...
pin ( SI ) {
nextstate type : ” scan in ”;
direction : input ;
...
p i n ( SE ) {
nextstate type : ” scan enable ”;
direction : input ;
...

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5.3 Behavioral Verilog Design Modifications
The Verilog design needs additional signals before it can be synthesized. These signals are only required for sequential
circuits, where FFs reside. The Scan FF will be inserted during the compilation process to create a scan chain. Because
the Scan FF contains additional signals that will need to be routed, the netlist needs inputs and outputs to allow ATPG
to control the input sequence and to validate the output sequence. For this reason, the circuit needs the following pins
created in the top module: test mode, scan input, scan output, and scan enable. Below is a snippet of the top module
declaration.
module c o n t r o l l e r ( i n p u t c l k , reset ,
input [ 5 : 0 ] op ,
input zero ,
input s i , se , t e s t m o d e , / / s c a n i n , s c a n e n a b l e , t e s t m o d e
output so , / / s c a n o u t
output reg memread , memwrite , a l u s r c a , memtoreg , i o r d ,
output pcen ,
output reg regwrite , regdst ,
output reg [ 1 : 0 ] pcsource , a l u s r c b , aluop ,
output reg [3:0] irwrite );

parameter FETCH1 = 4 ’ b0001 ;

parameter FETCH2 = 4 ’ b0010 ;
...

6 Verification Procedures
6.1 DC and DFT Setup
In our setup, the DC and DFT are run together using a single script. They could be run as two separate scripts, but
problems might arise during the file export and import process from DC to DFT respectively. Therefore, we assumed
that the design is already imported and ready for scan insertion. When reading the script, the breakpoint between the
two compilers occurs at the ”Insert Test Structures” comment. For the rest of the setup information, we will not go
into each instruction in detail. This is because the ”man” command can be used to view the manual entries of DC to
find out functionality and usage of unclear commands. Instead we will cover a high level description of the design flow.

The DC script starts with updating the target libraries for both standard cells and the Scan FF. In our process, we
differentiate between the standard cells library and the scan library but they do not necessarily need to be separated.
The scan cell style is then set up. There are several designs to choose here including multiplexed FF, clocked scan,
level-sensitive scan design (lssd), auxiliary clock lssd, combinational, or none. Based on our Scan FF design, only
multiplexed scan flip-flop is used. We then set up the AutoFix feature for clock and reset signals. This allows the
compiler to fix any test DRC errors at gate level logic introduced by the additional nets.

During the next process, we set up the test protocol, including all the parameters for clock, reset, and test mode if
they are used. Once the test protocol is created, we check the current design against the test design rules. Any major
violation in this step could cause the flow to continue incorrectly and ultimately fail in the TetraMAX tool. If errors
occur, the ”man” command can be used with the error number in parentheses to find out more information about the
violation.

Assuming errors have not occurred, we create the input signal delays. The delay allows the circuit to be fully re-
set before a certain input is applied. At this step, we can choose between Full Scan or Partial Scan. With Partial Scan,
the commented command, ”set scan element false {...},” blocks certain registers from being replaced with the Scan
FF. Otherwise, Full Scan is assumed and the script will continue with the compilation process. This process replaces
all sequential elements during optimization. This allows the design to be compiled in the future without the need of
reoptimization.

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Once the compilation process is completed, we can start on setting up the scan chain. This process is not needed
for combinational designs because there will be no replacements. This section sets up what each signal does in the
scan chain design. We also include a memory wrapper section, which is used specifically for designs with memory.
Here the Scan FFs will be inserted before and after the memory block instead of replacing each individual FF cell. This
allows the memory block to be tested as a single module. Next, we preview the design before the scan chain insertion
process begins. We also update the design state to reflect the inserted scan chain. The test design rules are checked
again to ensure no major errors occurred during the scan insertion process. Finally, we create all output reports, the
new structural design with inserted scan chains, and the test protocol (STIL) file. A similar process can be done with
Design Vision, while viewing the physical modifications in the schematic.

6.2 TetraMAX
The process for TetraMAX starts with importing the following: the complete netlist including scan inserted structural
Verilog, the cell library (behavioral Verilog) and the scan cell library (behavioral Verilog). The design then builds
and checks for synthesized violations of the testing rules. Once completed successfully, TetraMAX can generate test
patterns and coverage reports. TetraMAX also allows faults to be analyzed and simulated individually. Although we
did not experiment with all of the features available in TetraMAX due to conflicting version installations, our script
will now work with the recently installed F-2011.09-SP4 version, assuming proper Scan FFs have been designed.

7 Results
The following results will include output information from verifying sequential or combinational Verilog designs.
Due to an unresolved issue with our main Scan FF chain, our sequential design could not pass the TetraMAX DRC.
Whether this was caused by tool installation issues or the scan chain itself, part of our Future Work will be to determine
the root cause. We were, however, able to test combinational designs using TetraMAX and included a section of the
generated test patterns. The scan cell library file (.lib) and the behavioral library file (.v) are included in Appendix A
and B respectively.

The next comparison shows the size differences between our synthesized sequential controller using DC and the
scan inserted version using DFT. These results show our best case Scan FF, which turned out the be the one built from
the UofU Digital v1 2 library cells. Appendix C shows our script for running the DC and DFT Compiler.

From Size (µm square) Number of Nets (wires with same label)
DC: 384 90
DFT: 424 102

The next important piece of data is a high percentage of fault coverage. This means that if a fault occurs in the
fabricated model, there0 s a large chance the test patterns can pinpoint the exact area of failure. Below we outline the
types of faults detected during the DFT Compiler process on our sequential controller.

Fault Type # of faults

Detected 568
Undetectable 1
ATPG untestable 5
Not detected 0
total faults 574
test coverage 99.13%

The last snippet of output is from the TetraMAX process using our combinational adder circuit. Here we show 2 out
of 15 test patterns generated by TetraMAX. This particular circuit has a total of 268 detected faults. These 15 patterns
give us a test coverage of 100%, not including 14 undetectable faults for this particular circuit. Appendix D shows the
script for TetraMax.

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p a t t e r n = 0 ; / / 200
#0 P I = 23 ’ b11110100110000110001001 ;
#0;
XPCT = 8 ’ b10110111 ;
MASK = 8 ’ b11111111 ;
#0 −>m e a s u r e P O d e f a u l t W F T ;
# 1 0 0 ; / / 300

p a t t e r n = 1 ; / / 300
#0 P I = 23 ’ b01011100011111101010110 ;
#0;
XPCT = 8 ’ b11011010 ;
MASK = 8 ’ b11111111 ;
#0 −>m e a s u r e P O d e f a u l t W F T ;
# 1 0 0 ; / / 400
The behavioral Verilog code for the sequential controller and combinational adder can be found in Appendix E and F,
respectively.

8 Future Work
The first part will be to determine what causes our scan chain to fail the TetraMAX DRC. The newer version of Tetra-
MAX has been installed recently so we have not been able to retest our sequential designs. Another issue could be a
discrepancy between the DFT Compiler and the setup files used by TetraMAX.

The next part would be getting the sequential ATPG to work so full test vectors can be generated for the controller
module. We would also apply this tool flow to our entire processor design. Once completed, fabrication and actual
testing of our scan enabled design is desired to validate the patterns generated by TetraMax for fault detection.

9 Conclusion
Based on what we have learned about the Synopsys testing and verification tools, along with the scripts we have
developed, and the experience designing Scan FFs, we will be able to test our combinational and sequential Verilog
designs. Currently we are able complete scan insertion and get a coverage analysis on our sequential designs using the
DFT Compiler, although we might need slight modifications to the scan chain to complete the TetraMax process. As
for combinational designs, there is no scan insertion process in the DFT Compiler, but we can still achieve an ATPG
coverage and the test patterns from TetraMAX. The complete combinational output file, called expAdd tb patterns.v,
from TetraMAX is included in the source folder.

Only the main library files and scripts have been included in the Appendix. For a complete set of source files, re-
fer to the zipped source folder included with this report. The files step0, step1, and step2 are used to quickly run the
scripts.

step0 - sources the Synopsys environment setup file.

step1 - runs through the DC and DFT Compiler script.
step2 - runs through the TetraMAX script.

Note that modifications to the scripts are required depending on what type of Verilog design is being used.

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References
[1] E. Jose, “Scan insertion and atpg using synopsys & full scan v/s partial scan analysis,” 2006.
[2] Digital VLSI Chip Design with Cadence and Synopsys CAD Tools. Pearson Education Inc., 2010.

[3] Synopsys DFT Compiler User Guide.

[4] Synopsys TetraMax User Guide.
[5] Synopsys, Synopsys DFT Compiler.

[6] Synopsys, Synopsys TetraMAX ATPG.

[7] V. S. Ashok Kumar Suhag, “Delay testable enhanced scan flip-flop: Dft for high fault coverage,” 2011 Interna-
tional Symposium on Electronic System Design, 2011.

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10 Appendix
A foo.lib
/∗
d e l a y model : typ
c h e c k model : typ
power model : typ
c a p a c i t a n c e model : typ
o t h e r model : typ
∗/
l i b r a r y ( foo ) {

delay model : table lookup ;

in place swap mode : match footprint ;

/∗ unit a t t r i b u t e s ∗/
t i m e u n i t : ”1 n s ” ;
v o l t a g e u n i t : ”1V” ;
c u r r e n t u n i t : ”1mA” ;
p u l l i n g r e s i s t a n c e u n i t : ”1 kohm ” ;
l e a k a g e p o w e r u n i t : ”1nW” ;
c a p a c i t i v e l o a d u n i t (1 , pf ) ;

power supply ( ) {
d e f a u l t p o w e r r a i l : RAIL VDD ;
p o w e r r a i l ( RAIL GND , 0 ) ;
p o w e r r a i l ( RAIL VDD , 5 ) ;
}

/∗ Default a t t r i b u t e s ∗/
/∗ Fanout ( in terms of c a p a c i t i v e load u n i t s ) ∗/
d e f a u l t f a n o u t l o a d : 0.3 ; default max fanout : 10.0 ;
/∗ Pin Capacitance ∗/
d e f a u l t i n o u t p i n c a p : 0.00675 ;
d e f a u l t i n p u t p i n c a p : 0.00675 ;
d e f a u l t o u t p u t p i n c a p : 0.0 ;
/ ∗ l e a k a g e power ∗ /
default cell leakage power : 0.0 ;
default leakage power density : 0.0 ;

s l e w u p p e r t h r e s h o l d p c t r i s e : 80;
s l e w l o w e r t h r e s h o l d p c t r i s e : 20;
s l e w u p p e r t h r e s h o l d p c t f a l l : 80;
s l e w l o w e r t h r e s h o l d p c t f a l l : 20;
i n p u t t h r e s h o l d p c t r i s e : 30;
i n p u t t h r e s h o l d p c t f a l l : 70;
o u t p u t t h r e s h o l d p c t r i s e : 70;
o u t p u t t h r e s h o l d p c t f a l l : 30;
nom process : 1;
nom voltage : 5;
nom temperature : 25;
operating conditions ( typical ) {

10
 process : 1;
voltage : 5;
temperature : 25;
p o w e r r a i l ( RAIL GND , 0 ) ;
p o w e r r a i l ( RAIL VDD , 5 ) ;
}
default operating conditions : typical ;

lu table template ( delay template 5x5 ) {

variable 1 : input net transition ;
variable 2 : total output net capacitance ;
index 1 (”1000.0 , 1001.0 , 1002.0 , 1003.0 , 1004.0”);
index 2 (”1000.0 , 1001.0 , 1002.0 , 1003.0 , 1004.0”);
}
power lut template ( energy template 5x5 ) {
variable 1 : input transition time ;
variable 2 : total output net capacitance ;
index 1 (”1000.0 , 1001.0 , 1002.0 , 1003.0 , 1004.0”);
index 2 (”1000.0 , 1001.0 , 1002.0 , 1003.0 , 1004.0”);
}
lu table template ( hold template 5x3 ) {
variable 1 : constrained pin transition ;
variable 2 : related pin transition ;
index 1 (”1000.0 , 1001.0 , 1002.0 , 1003.0 , 1004.0”);
index 2 (”1000.0 , 1001.0 , 1002.0”);
}
power lut template ( passive energy template 5x1 ) {
variable 1 : input transition time ;
index 1 (”1000.0 , 1001.0 , 1002.0 , 1003.0 , 1004.0”);
}
lu table template ( setup template 5x3 ) {
variable 1 : constrained pin transition ;
variable 2 : related pin transition ;
index 1 (”1000.0 , 1001.0 , 1002.0 , 1003.0 , 1004.0”);
index 2 (”1000.0 , 1001.0 , 1002.0”);
}
lu table template ( width template 5x1 ) {
variable 1 : related pin transition ;
index 1 (”1000.0 , 1001.0 , 1002.0 , 1003.0 , 1004.0”);
}

/ ∗ −−−−−−−−−−−−− ∗
∗ D e s i g n : SDFF ∗
∗ −−−−−−−−−−−−− ∗ /
c e l l ( SDFF ) {
area : 4500;
cell leakage power : 0.679284;
r a i l c o n n e c t i o n ( GND, RAIL GND ) ;
r a i l c o n n e c t i o n ( VDD, RAIL VDD ) ;
p i n o p p o s i t e ( ”Q” , ”QB ” ) ;
f f ( IQ , IQN ) {
n e x t s t a t e : ” ( ( SE S I ) + ( ! SE D ) ) ” ;
c l o c k e d o n : ” ( ! ( ! CLK ) ) ” ;
}

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test cell () {
p i n (D) {
direction : input ;
}
p i n (CLK) {
direction : input ;
}
pin ( SI ) {
direction : input ;
signal type : test scan in ;
}
p i n ( SE ) {
direction : input ;
signal type : test scan enable ;
}
f f ( IQ , IQN ) {
n e x t s t a t e : ”D” ;
c l o c k e d o n : ”CLK ” ;
}
p i n (Q) {
direction : output ;
f u n c t i o n : ” IQ ” ;
signal type : test scan out ;
}
p i n (QB) {
direction : output ;
f u n c t i o n : IQN ;
signal type : test scan out inverted ;
}
}
p i n (CLK) {
direction : input ;
i n p u t s i g n a l l e v e l : RAIL VDD ;
capacitance : 0.0172919;
r i s e c a p a c i t a n c e : 0.0172686;
f a l l c a p a c i t a n c e : 0.0172919;
r i s e c a p a c i t a n c e r a n g e ( 0.0172252 , 0.0172889) ;
f a l l c a p a c i t a n c e r a n g e ( 0.0172693 , 0.0173121) ;
clock : true ;
max transition : 1.2;
internal power () {
rise power ( passive energy template 5x1 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
values (”1.84638 , 1.87525 , 2.03345 , 2.18017 , 2.74568”);
}
fall power ( passive energy template 5x1 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
values (”3.21314 , 3.25617 , 3.4244 , 3.58177 , 4.14905”);
}
}
timing () {
r e l a t e d p i n : ”CLK ” ;
timing type : min pulse width ;
when : ” !D&!SE&! S I ” ;

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 s d f c o n d : ” D EQ 0 AN SE EQ 0 AN SI EQ 0 == 1 ’ b1 ” ;
r i s e c o n s t r a i n t ( width template 5x1 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
values (”0.763702 , 0.828201 , 0.970086 , 1.07303 , 1.38691”);
}
f a l l c o n s t r a i n t ( width template 5x1 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
values (”0.892968 , 0.967046 , 1.11533 , 1.22008 , 1.53877”);
}
}
}
p i n (D) {
direction : input ;
i n p u t s i g n a l l e v e l : RAIL VDD ;
capacitance : 0.0202517;
r i s e c a p a c i t a n c e : 0.019647;
f a l l c a p a c i t a n c e : 0.0202517;
r i s e c a p a c i t a n c e r a n g e ( 0.0196047 , 0.0290485) ;
f a l l c a p a c i t a n c e r a n g e ( 0.020241 , 0.0290314) ;
max transition : 1.2;
internal power () {
rise power ( passive energy template 5x1 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
values (”1.85927 , 1.88606 , 2.02546 , 2.14059 , 2.5922”);
}
fall power ( passive energy template 5x1 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
values (”2.58905 , 2.62006 , 2.77426 , 2.90761 , 3.38858”);
}
}
timing () {
r e l a t e d p i n : ”CLK ” ;
timing type : hold rising ;
when : ” ! SE ” ;
s d f c o n d : ”SE == 1 ’ b0 ” ;
r i s e c o n s t r a i n t ( hold template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0”);
}
f a l l c o n s t r a i n t ( hold template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.0 , 0.0 , 0.04875” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0”);

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 }
}
timing () {
r e l a t e d p i n : ”CLK ” ;
timing type : setup rising ;
when : ” ! SE ” ;
s d f c o n d : ”SE == 1 ’ b0 ” ;
rise constraint ( setup template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.31875 , 0.21375 , 0.0825” , \
”0.37125 , 0.26625 , 0.135” , \
”0.5325 , 0.37125 , 0.24” , \
”0.555 , 0.45 , 0.31875” , \
”0.8175 , 0.65625 , 0.525”);
}
f a l l c o n s t r a i n t ( setup template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.65625 , 0.495 , 0.36375” , \
”0.70875 , 0.60375 , 0.41625” , \
”0.87 , 0.765 , 0.5775” , \
”1.005 , 0.84375 , 0.7125” , \
”1.38 , 1.21875 , 1.0875”);
}
}
}
p i n (Q) {
direction : output ;
o u t p u t s i g n a l l e v e l : RAIL VDD ;
capacitance : 0;
r i s e c a p a c i t a n c e : 0;
f a l l c a p a c i t a n c e : 0;
r i s e c a p a c i t a n c e r a n g e ( 0 , 0) ;
f a l l c a p a c i t a n c e r a n g e ( 0 , 0) ;
max capacitance : 0.362947;
max transition : 1.90162;
f u n c t i o n : ” IQ ” ;
timing () {
r e l a t e d p i n : ”CLK ” ;
timing sense : non unate ;
timing type : rising edge ;
c e l l r i s e ( delay template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.794642 , 0.85843 , 0.983411 , 1.47749 , 2.216” , \
”0.859753 , 0.92356 , 1.04869 , 1.54274 , 2.2814” , \
”0.999215 , 1.06347 , 1.18848 , 1.68251 , 2.42133” , \
”1.0991 , 1.16287 , 1.28787 , 1.78199 , 2.52075” , \
”1.40103 , 1.46512 , 1.58968 , 2.08372 , 2.8224”);
}

14
r i s e t r a n s i t i o n ( delay template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.212049 , 0.27025 , 0.388735 , 0.873429 , 1.60609” , \
”0.212062 , 0.270261 , 0.388752 , 0.87342 , 1.60628” , \
”0.212056 , 0.270249 , 0.388731 , 0.873383 , 1.60638” , \
”0.211919 , 0.270204 , 0.388752 , 0.873397 , 1.60631” , \
”0.212035 , 0.270689 , 0.388878 , 0.873493 , 1.60631”);
}
c e l l f a l l ( delay template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.763702 , 0.847688 , 1.01205 , 1.65849 , 2.62194” , \
”0.828201 , 0.912709 , 1.07703 , 1.72356 , 2.68686” , \
”0.970086 , 1.05416 , 1.21854 , 1.8646 , 2.82858” , \
”1.07303 , 1.1568 , 1.32098 , 1.96665 , 2.93059” , \
”1.38691 , 1.47055 , 1.63436 , 2.28052 , 3.24412”);
}
f a l l t r a n s i t i o n ( delay template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.239486 , 0.30891 , 0.449662 , 1.02586 , 1.90162” , \
”0.239497 , 0.308911 , 0.449641 , 1.02587 , 1.90096” , \
”0.239593 , 0.308997 , 0.44968 , 1.026 , 1.90111” , \
”0.239997 , 0.309377 , 0.450007 , 1.02608 , 1.90162” , \
”0.241425 , 0.310253 , 0.450402 , 1.02617 , 1.90118”);
}
}
internal power () {
r e l a t e d p i n : ”CLK ” ;
rise power ( energy template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”3.85901 , 4.16808 , 4.78988 , 7.288 , 11.0389” , \
”3.88149 , 4.19063 , 4.81267 , 7.31086 , 11.0616” , \
”4.02798 , 4.33814 , 4.96001 , 7.45807 , 11.2088” , \
”4.1844 , 4.4939 , 5.11603 , 7.61452 , 11.3654” , \
”4.74256 , 5.05242 , 5.66497 , 8.1626 , 11.9132”);
}
fall power ( energy template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”3.15374 , 2.84656 , 2.2314 , 0.247617 , 3.98677” , \
”3.17082 , 2.87163 , 2.25649 , 0.222216 , 3.96146” , \
”3.36198 , 3.05475 , 2.43983 , 0.038051 , 3.77644” , \
”3.56539 , 3.25699 , 2.64074 , 0.161013 , 3.57758” , \
”4.28224 , 3.97203 , 3.35273 , 0.872756 , 2.86484”);
}
}

15
}
p i n (QB) {
direction : output ;
o u t p u t s i g n a l l e v e l : RAIL VDD ;
capacitance : 0;
r i s e c a p a c i t a n c e : 0;
f a l l c a p a c i t a n c e : 0;
r i s e c a p a c i t a n c e r a n g e ( 0 , 0) ;
f a l l c a p a c i t a n c e r a n g e ( 0 , 0) ;
max capacitance : 0.255931;
max transition : 2.23084;
f u n c t i o n : ”IQN ” ;
timing () {
r e l a t e d p i n : ”CLK ” ;
timing sense : non unate ;
timing type : rising edge ;
c e l l r i s e ( delay template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.578634 , 0.665801 , 0.837776 , 1.5144 , 2.522” , \
”0.643475 , 0.730434 , 0.902774 , 1.57827 , 2.58706” , \
”0.78463 , 0.87052 , 1.04096 , 1.71503 , 2.72262” , \
”0.887771 , 0.972984 , 1.14291 , 1.81416 , 2.82031” , \
”1.20173 , 1.28504 , 1.45249 , 2.11743 , 3.11921”);
}
r i s e t r a n s i t i o n ( delay template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.300933 , 0.386874 , 0.562848 , 1.24025 , 2.23053” , \
”0.301374 , 0.386853 , 0.562949 , 1.24026 , 2.23084” , \
”0.302073 , 0.387592 , 0.563185 , 1.2403 , 2.23055” , \
”0.305802 , 0.38985 , 0.564359 , 1.24049 , 2.23063” , \
”0.318665 , 0.400004 , 0.571868 , 1.24257 , 2.23075”);
}
c e l l f a l l ( delay template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.657902 , 0.715835 , 0.827302 , 1.26823 , 1.93043” , \
”0.723392 , 0.780451 , 0.892293 , 1.33321 , 1.99562” , \
”0.863344 , 0.920551 , 1.03245 , 1.47331 , 2.13539” , \
”0.96279 , 1.02048 , 1.1317 , 1.5726 , 2.23457” , \
”1.26559 , 1.32337 , 1.43455 , 1.87538 , 2.53717”);
}
f a l l t r a n s i t i o n ( delay template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.218249 , 0.27038 , 0.376187 , 0.800053 , 1.42646” , \
”0.218369 , 0.269748 , 0.376155 , 0.800069 , 1.42668” , \
”0.218317 , 0.269859 , 0.376014 , 0.800105 , 1.42646” , \
”0.218671 , 0.270596 , 0.376259 , 0.80017 , 1.42651” , \

16
 ”0.220108 , 0.27147 , 0.376756 , 0.80025 , 1.42647”);
}
}
internal power () {
r e l a t e d p i n : ”CLK ” ;
rise power ( energy template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”3.7891 , 4.14936 , 4.89649 , 8.00794 , 12.7455” , \
”3.81153 , 4.16713 , 4.91742 , 8.03012 , 12.763” , \
”3.99921 , 4.35042 , 5.08954 , 8.18483 , 12.9171” , \
”4.19431 , 4.54045 , 5.27395 , 8.35511 , 13.0813” , \
”4.90314 , 5.22963 , 5.94197 , 8.97826 , 13.6802”);
}
fall power ( energy template 5x5 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.025 , 0.05 , 0.1 , 0.3 , 0 . 6 ” ) ;
values ( \
”3.2416 , 2.9453 , 2.37277 , 0.195615 , 2.96504” , \
”3.26652 , 2.97248 , 2.39746 , 0.222417 , 2.94206” , \
”3.41397 , 3.12053 , 2.54626 , 0.368261 , 2.79364” , \
”3.57046 , 3.2763 , 2.7033 , 0.523699 , 2.63997” , \
”4.11927 , 3.82483 , 3.24799 , 1.06815 , 2.09762”);
}
}
}
p i n ( SE ) {
nextstate type : ” scan enable ”;
direction : input ;
i n p u t s i g n a l l e v e l : RAIL VDD ;
capacitance : 0.047487;
r i s e c a p a c i t a n c e : 0.047487;
f a l l c a p a c i t a n c e : 0.0471533;
r i s e c a p a c i t a n c e r a n g e ( 0.0463496 , 0.0504435) ;
f a l l c a p a c i t a n c e r a n g e ( 0.0466062 , 0.050495) ;
max transition : 1.2;
internal power () {
rise power ( passive energy template 5x1 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
values (”2.3186 , 2.34552 , 2.506 , 2.65134 , 3.57613”);
}
fall power ( passive energy template 5x1 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
values (”3.47275 , 3.53407 , 3.87065 , 4.18244 , 5.31637”);
}
}
timing () {
r e l a t e d p i n : ”CLK ” ;
timing type : hold rising ;
when : ” !D&S I ” ;
s d f c o n d : ” D EQ 0 AN SI EQ 1 == 1 ’ b1 ” ;
r i s e c o n s t r a i n t ( hold template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;

17
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0”);
}
f a l l c o n s t r a i n t ( hold template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.0 , 0.0 , 0.04875” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0”);
}
}
timing () {
r e l a t e d p i n : ”CLK ” ;
timing type : hold rising ;
when : ”D&! S I ” ;
s d f c o n d : ” D EQ 1 AN SI EQ 0 == 1 ’ b1 ” ;
r i s e c o n s t r a i n t ( hold template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0”);
}
f a l l c o n s t r a i n t ( hold template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0”);
}
}
timing () {
r e l a t e d p i n : ”CLK ” ;
timing type : setup rising ;
when : ” !D&S I ” ;
s d f c o n d : ” D EQ 0 AN SI EQ 1 == 1 ’ b1 ” ;
rise constraint ( setup template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \

18
 ”0.31875 , 0.21375 , 0.0825” , \
”0.37125 , 0.26625 , 0.135” , \
”0.47625 , 0.37125 , 0.18375” , \
”0.555 , 0.39375 , 0.2625” , \
”0.705 , 0.6 , 0.46875”);
}
f a l l c o n s t r a i n t ( setup template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.65625 , 0.55125 , 0.36375” , \
”0.70875 , 0.60375 , 0.41625” , \
”0.87 , 0.70875 , 0.5775” , \
”0.94875 , 0.84375 , 0.65625” , \
”1.32375 , 1.1625 , 0.975”);
}
}
timing () {
r e l a t e d p i n : ”CLK ” ;
timing type : setup rising ;
when : ”D&! S I ” ;
s d f c o n d : ” D EQ 1 AN SI EQ 0 == 1 ’ b1 ” ;
rise constraint ( setup template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.825 , 0.66375 , 0.47625” , \
”0.8775 , 0.71625 , 0.585” , \
”0.9825 , 0.8775 , 0.69” , \
”1.1175 , 0.95625 , 0.76875” , \
”1.38 , 1.21875 , 1.0875”);
}
f a l l c o n s t r a i n t ( setup template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.43125 , 0.32625 , 0.195” , \
”0.54 , 0.37875 , 0.2475” , \
”0.645 , 0.54 , 0.40875” , \
”0.72375 , 0.61875 , 0.4875” , \
”1.0425 , 0.88125 , 0 . 7 5 ” ) ;
}
}
}
pin ( SI ) {
nextstate type : ” scan in ”;
direction : input ;
i n p u t s i g n a l l e v e l : RAIL VDD ;
capacitance : 0.0208047;
r i s e c a p a c i t a n c e : 0.0202066;
f a l l c a p a c i t a n c e : 0.0208047;
r i s e c a p a c i t a n c e r a n g e ( 0.0201587 , 0.0299656) ;
f a l l c a p a c i t a n c e r a n g e ( 0.0207946 , 0.0299564) ;
max transition : 1.2;

19
internal power () {
rise power ( passive energy template 5x1 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
values (”1.85122 , 1.87905 , 2.01477 , 2.12971 , 2.57987”);
}
fall power ( passive energy template 5x1 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
values (”2.63597 , 2.66673 , 2.822 , 2.95425 , 3.43946”);
}
}
timing () {
r e l a t e d p i n : ”CLK ” ;
timing type : hold rising ;
when : ”SE ” ;
s d f c o n d : ”SE == 1 ’ b1 ” ;
r i s e c o n s t r a i n t ( hold template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0”);
}
f a l l c o n s t r a i n t ( hold template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.0 , 0.0 , 0.04875” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0” , \
”0.0 , 0.0 , 0.0”);
}
}
timing () {
r e l a t e d p i n : ”CLK ” ;
timing type : setup rising ;
when : ”SE ” ;
s d f c o n d : ”SE == 1 ’ b1 ” ;
rise constraint ( setup template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;
values ( \
”0.31875 , 0.21375 , 0.0825” , \
”0.37125 , 0.26625 , 0.135” , \
”0.5325 , 0.37125 , 0.24” , \
”0.555 , 0.45 , 0.31875” , \
”0.8175 , 0.65625 , 0.525”);
}
f a l l c o n s t r a i n t ( setup template 5x3 ) {
index 1 (”0.06 , 0.18 , 0.42 , 0.6 , 1 . 2 ” ) ;
index 2 (”0.06 , 0.3 , 0 . 6 ” ) ;

20
 values ( \
”0.65625 , 0.495 , 0.36375” , \
”0.70875 , 0.60375 , 0.41625” , \
”0.87 , 0.765 , 0.5775” , \
”1.005 , 0.84375 , 0.7125” , \
”1.38 , 1.21875 , 1.0875”);
}
}
}
}

B foo.v
module SDFF (CLK, D, Q, QB, SE , S I ) ;
input CLK, D, SE , S I ;
output Q, QB;
n o t ( n3 , CLK ) ;
n o t (Q, QB ) ;
mux ( n2 , SE , SI , D ) ;
mux ( n1 , n3 , n2 , n 1 ) ;
imux (QB, n3 , Q, n 1 ) ;
endmodule

C Script for DFT

# ∗ M o d i f i e d by Anh Luong & A n d r z e j F o r y s
# ∗ FALL 2012
# ∗
# ∗ A u t h o r : E r i k Brunvand , U n i v e r s i t y o f Utah
# ∗
# ∗ G e n e r a l s y n t h e s i s s c r i p t f o r S y n o p s y s . T h e r e s h o u l d be
# ∗ some g e n e r a l s w i t c h e s and p a r a m e t e r s s e t i n . s y n o p s y s d c . s e t u p
# ∗ b u t o t h e r d e s i g n −s p e c i f i c t h i n g s a r e s e t h e r e .
# ∗ You s h o u l d l o o k c a r e f u l l y a t e v e r y t h i n g a b o v e t h e
# ∗ ” below h e r e s h o u l d n ’ t n e e d t o be c h a n g e d ” l i n e .
# ∗
# ∗ Note t h a t l i s t s t h a t c o n t i n u e a c r o s s a l i n e n e e d a b a c k s l a s h
# ∗ t o c o n t i n u e t o t h e n e x t l i n e ( i f you h a v e a bunch o f
# ∗ d i f f e r e n t v e r i l o g f i l e s , one p e r l i n e , f o r example , o r a bunch
# ∗ o f t a r g e t l i b r a r y f i l e s ) . Make SURE t h e r e i s n ’ t a s p a c e a f t e r
# ∗ t h e \ because t h a t can cause Synopsys t o complain . . .
# ∗
# ∗ Once you ’ ve m o d i f i e d t h i n g s t o y o u r p r o j e c t , i n v o k e w i t h :
# ∗
# ∗ syn−dc −f syn− s c r i p t
# ∗
# ∗

# This s c r i p t assumes t h a t t h e f o l l o w i n g v a r i a b l e s a r e d e f i n e d
# i n t h e . s y n o p s y s d c . s e t u p f i l e . You s h o u l d make s u r e t h a t
# your . synopsys dc . s e t u p f i l e i s c o n f i g u r e d f o r your
# c e l l l i b r a r y ! I f you want t o o v e r r i d e o r

21
# add t o t h o s e s e a r c h p a t h s , you c a n do t h a t h e r e . . .
#
# S y n o p s y s I n s t a l l = path to synopsys i n s t a l l a t i o n d i r e c t o r y
# s y n t h e t i c l i b r a r y = designware f i l e s
# s y m b o l l i b r a r y = l o g i c s y m b o l s f o r making s c h e m a t i c s
#

# s e a r c h p a t h s h o u l d i n c l u d e d i r e c t o r i e s w i t h memory . db f i l e s
# as well as the standard c e l l s
# Your l i b r a r y p a t h may be empty i f y o u r l i b r a r y w i l l be i n
# y o u r s y n t h e s i s d i r e c t o r y b e c a u s e ” . ” i s a l r e a d y on t h e p a t h .
# set search path [ l i s t . \
# [ f o r m a t ”%s%s ” $ S y n o p s y s I n s t a l l / l i b r a r i e s / s y n ] \
# [ f o r m a t ”%s%s ” $ S y n o p s y s I n s t a l l / dw / s i m v e r ] \
# / u u s o c / f a c i l i t y / cad common / l o c a l / Cadence / l i b /OA/ U o f U D i g i t a l v 1 2 ]

# t a r g e t l i b r a r y l i s t s h o u l d i n c l u d e a l l t a r g e t . db f i l e s
s e t t a r g e t l i b r a r y [ l i s t U o f U D i g i t a l v 1 2 . db ]

# s y n t h e t i c l i b r a r y i s s e t i n . s y n o p s y s d c . s e t u p t o be
# the dw foundation l i b r a r y .
s e t l i n k l i b r a r y [ c o n c a t [ c o n c a t ”∗” $ t a r g e t l i b r a r y ] $ s y n t h e t i c l i b r a r y ]

####################################
# Print to screen options #
####################################
set verbose 1 ; # 1 W r i t e r e p o r t s t o s c r e e n , 0 do n o t w r i t e r e p o r t s t o s c r e e n
s e t v e r b o s e d f t 1 ; # 1 W r i t e r e p o r t s t o s c r e e n , 0 do n o t w r i t e r e p o r t s t o s c r e e n

####################################
# Synthesis #
####################################

# below a r e p a r a m e t e r s t h a t you w i l l want t o s e t f o r e a c h d e s i g n

# l i s t o f a l l HDL f i l e s i n t h e d e s i g n
s e t myFiles [ l i s t c o n t r o l l e r . v ]
set fileFormat verilog ; # v e r i l o g o r VHDL
s e t basename c o n t r o l l e r ; # Top−l e v e l module name
s e t myClk c l k ; # The name o f y o u r c l o c k
set virtual 0 ;# 1 i f v i r t u a l clock , 0 i f r e a l clock

# compiler switches . . .
# set optimizeArea 0 ;# 1 f o r area , 0 f o r speed
set useUltra 1 ;# 1 f o r c o m p i l e u l t r a , 0 fo r compile
# mapEffort , useUngroup a r e f o r
# non− u l t r a c o m p i l e . . .
s e t m a p E f f o r t 1 medium ; # F i r s t p a s s − low , medium , o r h i g h
s e t m a p E f f o r t 2 medium ; # s e c o n d p a s s − low , medium , o r h i g h
s e t useUngroup 1 ; # 0 i f no f l a t t e n , 1 i f f l a t t e n

# Timing and l o a d i n g i n f o r m a t i o n
s e t m y P e r i o d n s 25 ;# d e s i r e d clock period ( s e t s speed goal )
s e t myClkLatency ns 0.3 ; # clock network l a t e n c y

22
set myInDelay ns 0.25 ; # d e l a y from c l o c k t o i n p u t s v a l i d
set myOutDelay ns 0 . 2 5 ; # d e l a y from c l o c k t o o u t p u t v a l i d
set m y I n p u t B u f INVX4 ; # name o f c e l l d r i v i n g t h e i n p u t s
set myLoadLibrary U o f U D i g i t a l v 1 2 ; # name o f l i b r a r y t h e c e l l comes from
set myLoadPin Y ; # name o f p i n t h a t o u t p u t s d r i v e

# Control the w r i t i n g of r e s u l t f i l e s
s e t runname s t r u c t ; # Name a p p e n d e d t o o u t p u t f i l e s

# the following control which o u t p u t f i l e s you want . They

# s h o u l d be s e t t o 1 i f you want t h e f i l e , 0 i f n o t
set write v 1 ;# compiled s t r u c t u r a l Verilog f i l e
set write ddc 0 ; # c o m p i l e d f i l e i n ddc f o r m a t (XG−mode )
set write sdf 1 ; # s d f f i l e f o r back−a n n o t a t e d t i m i n g sim
set write sdc 1 ; # s d c c o n s t r a i n t f i l e f o r p l a c e and r o u t e
set write rep 0 ; # r e p o r t f i l e from c o m p i l a t i o n
s e t write pow 0 ; # r e p o r t f i l e f o r power e s t i m a t e

####################################
# DFT S w i t c h e s #
####################################
s e t dft runname scan ; # name a p p e n d e d t o o u t p u t f i l e s
s e t s c a n l i b r a r y [ l i s t f o o . db ] ; # L i b r a r y w i t h s c a n c h a i n c e l l s
# s e t s c a n c e l l SCANFF ; # Name o f ScanFF C e l l

# Setup t i m i n g v a r i a b l e s f o r d f t d r c command
set test d e f a u l t d e l a y 0 ; # d e f i n e t i m e when v a l u e s a r e a p p l i e d t o i n p u t p o r t s
set test d e f a u l t b i d i r d e l a y 0 ; # Defines the d e f a u l t switching time of b i d i r e c t i o n a l p
set test d e f a u l t s t r o b e 40 ; # d e f a u l t s t r o b e t i m e i n a t e s t c y c l e f o r o u t p u t p o r t s and b i d
set test d e f a u l t p e r i o d 100 ; # D e f i n e s t h e d e f a u l t l e n g t h o f a t e s t v e c t o r c y c l e

# Setup scan chain f o r i n s e r t d f t

# set t e s t d e f a u l t s c a n s t y l e m u l t i p l e x e d f l i p f l o p ; # Defines the d e f a u l t scan s t y l e for

#∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
#∗ below h e r e s h o u l d n ’ t n e e d t o be c h a n g e d . . . ∗
#∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

####################################
# remove any o t h e r d e s i g n s from d e s i g n c o m p i l e r ’ s memory
####################################
remove design −a l l
# IMPORTING DESIGN

# a n a l y z e and e l a b o r a t e t h e f i l e s
a n a l y z e −f o r m a t $ f i l e F o r m a t − l i b WORK $ m y F i l e s
e l a b o r a t e $basename − l i b WORK −u p d a t e
c u r r e n t d e s i g n $basename

# The l i n k command makes s u r e t h a t a l l t h e r e q u i r e d d e s i g n

# parts are linked together .
# The u n i q u i f y command makes u n i q u e c o p i e s o f r e p l i c a t e d
# modules .

23
link
uniquify

# SETUP CONSTRAINTS

# now you c a n c r e a t e c l o c k s f o r t h e d e s i g n
# and s e t o t h e r c o n s t r a i n t s
i f { $ v i r t u a l == 0 } {
c r e a t e c l o c k −p e r i o d $ m y P e r i o d n s $myClk
} else {
c r e a t e c l o c k −p e r i o d $ m y P e r i o d n s −name $myClk
}
#∗∗∗ add t h i s s h i t
s e t c l o c k l a t e n c y $ m y C l k L a t e n c y n s $myClk

# Set the driving c e l l for a l l inputs except the clock

# The c l o c k h a s i n f i n t e d r i v e by d e f a u l t . T h i s i s u s u a l l y
# what you want f o r s y n t h e s i s b e c a u s e you w i l l u s e o t h e r
# t o o l s ( l i k e SOC E n c o u n t e r ) t o b u i l d t h e c l o c k t r e e
# ( o r d e f i n e i t by hand ) .
i f { $ v i r t u a l == 0 } {
s e t d r i v i n g c e l l − l i b r a r y $myLoadLibrary − l i b c e l l $myInputBuf [ a l l i n p u t s ] \
} else {
s e t d r i v i n g c e l l − l i b r a r y $myLoadLibrary − l i b c e l l $myInputBuf \
[ r e m o v e f r o m c o l l e c t i o n [ a l l i n p u t s ] $myClk ]
}

# s e t t h e i n p u t and o u t p u t d e l a y r e l a t i v e t o myClk
i f { $ v i r t u a l == 0 } {
s e t i n p u t d e l a y $ m y I n D e l a y n s −c l o c k $myClk [ a l l i n p u t s ] \
} else {
s e t i n p u t d e l a y $ m y I n D e l a y n s −c l o c k $myClk \
[ r e m o v e f r o m c o l l e c t i o n [ a l l i n p u t s ] $myClk ]
}
s e t o u t p u t d e l a y $myOutDelay ns −c l o c k $myClk [ a l l o u t p u t s ]

# s e t the load of the c i r c u i t outputs in terms of the load

# of the next c e l l t h a t they w i l l drive , also t r y to f i x
# hold time i s s u e s
s e t l o a d [ l o a d o f [ f o r m a t ”%s%s%s%s%s ” $ m y L o a d L i b r a r y ” / ” $ m y I n p u t B u f ” / ” $myLoadPin ] ] [ a l l
s e t f i x h o l d $myClk

# FINISH SETUP CONSTRAINTS

# T h i s command w i l l f i x t h e p r o b l e m o f h a v i n g
# a s s i g n s t a t e m e n t s l e f t in your s t r u c t u r a l f i l e .
# But , i t w i l l i n s e r t p a i r s o f i n v e r t e r s f o r f e e d t h r o u g h s !
s e t f i x m u l t i p l e p o r t n e t s −a l l −b u f f e r c o n s t a n t s

# COMPILING DESIGN

# now c o m p i l e t h e d e s i g n w i t h g i v e n mapping e f f o r t
# and do a s e c o n d c o m p i l e w i t h i n c r e m e n t a l mapping
# o r u s e t h e c o m p i l e u l t r a meta−command

24
i f { $ u s e U l t r a == 1 } {
compile ultra
} else {
i f { $ u s e U n g r o u p == 1 } {
c o m p i l e −u n g o u p a l l −m a p e f f o r t $ m a p E f f o r t 1
c o m p i l e −i n c r e m e n t a l m a p p i n g −m a p e f f o r t $ m a p E f f o r t 2
} else {
c o m p i l e −m a p e f f o r t $ m a p E f f o r t 1
c o m p i l e −i n c r e m e n t a l m a p p i n g −m a p e f f o r t $ m a p E f f o r t 2
}
}

#
check design
# VIOLATIONS
report constraint −a l l v i o l a t o r s

#∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
#∗ now w r i t e o u t t h e r e s u l t s ∗
#∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

s e t f i l e b a s e [ f o r m a t ”%s%s ” [ f o r m a t ”%s%s ” $basename ” ” ] $runname ]

# s t r u c t u r a l ( s y n t h e s i z e d ) f i l e as v e r i l o g
i f { $ w r i t e v == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . v ” ]
r e d i r e c t change names \
{ c h a n g e n a m e s − r u l e s v e r i l o g − h i e r a r c h y −v e r b o s e }
w r i t e −f o r m a t v e r i l o g − h i e r a r c h y −o u t p u t $ f i l e n a m e
}

# w r i t e o u t t h e s d f f i l e f o r back−a n n o t a t e d v e r i l o g sim
# T h i s f i l e c a n be l a r g e !
i f { $ w r i t e s d f == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . s d f ” ]
w r i t e s d f −v e r s i o n 1 . 0 $ f i l e n a m e
}

# t h i s i s t h e t i m i n g c o n s t r a i n t s f i l e g e n e r a t e d from t h e
# c o n d i t i o n s a b o v e − u s e d i n t h e p l a c e and r o u t e p r o g r a m
i f { $ w r i t e s d c == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . s d c ” ]
write sdc $filename
}

# s y n o p s y s d a t a b a s e f o r m a t i n c a s e you want t o r e a d t h i s
# s y n t h e s i z e d r e s u l t b a c k i n t o s y n o p s y s l a t e r i n XG mode ( ddc f o r m a t )
i f { $ w r i t e d d c == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . ddc ” ]
w r i t e −f o r m a t ddc − h i e r a r c h y −o $ f i l e n a m e
}

# r e p o r t on t h e r e s u l t s from s y n t h e s i s

25
# n o t e t h a t > makes a new f i l e and >> a p p e n d s t o a f i l e
i f { $ w r i t e r e p == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . r e p ” ]
r e d i r e c t $filename { report timing }
r e d i r e c t −a p p e n d $ f i l e n a m e { r e p o r t a r e a }
}

# r e p o r t t h e power e s t i m a t e from s y n t h e s i s .
i f { $ w r i t e p o w == 1 } {
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . pow ” ]
r e d i r e c t $filename { report power }
}

# p r i n t report to the screen

i f { $ v e r b o s e == 1 } {
report design
report hierarchy
r e p o r t t i m i n g −p a t h f u l l −d e l a y max −n w o r s t 3 − s i g n i f i c a n t d i g i t s 2 − s o r t b y g r o u p
r e p o r t t i m i n g −p a t h f u l l −d e l a y min −n w o r s t 3 − s i g n i f i c a n t d i g i t s 2 − s o r t b y g r o u p
report area
report cell
report net
r e p o r t p o r t −v
r e p o r t p o w e r − a n a l y s i s e f f o r t low
}

# Design r e p o r t s
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . d e s i g n ” ]
r e d i r e c t $filename { report design }

# Hierarchy reports
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . d e s i g n ” ]
r e d i r e c t −a p p e n d $ f i l e n a m e { r e p o r t h i e r a r c h y }

# Timing r e p o r t s
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . t i m i n g ” ]
r e d i r e c t $ f i l e n a m e { r e p o r t t i m i n g −p a t h f u l l −d e l a y max −n w o r s t 5 − s i g n i f i c a n t d i g i t s 2 − s

s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . t i m i n g ” ]
r e d i r e c t −a p p e n d $ f i l e n a m e { r e p o r t t i m i n g −p a t h f u l l −d e l a y min −n w o r s t 5 − s i g n i f i c a n t d i g

# Report cell
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . a r e a ” ]
r e d i r e c t $filename { re port ar ea }

# Report area
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . a r e a ” ]
r e d i r e c t −a p p e n d $ f i l e n a m e { r e p o r t c e l l }

# Report port
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . p o r t s ” ]
r e d i r e c t $ f i l e n a m e { r e p o r t p o r t −v }

# Report net

26
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . n e t ” ]
r e d i r e c t $filename { r e p o r t n e t }

# R e p o r t power
s e t f i l e n a m e [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . pow ” ]
r e d i r e c t $ f i l e n a m e { r e p o r t p o w e r − a n a l y s i s e f f o r t low }

##########################################
#### I n s e r t T e s t S t r u c t u r e s ###
##########################################
# Update f i l e b a s e
s e t f i l e b a s e [ f o r m a t ”%s%s ” [ f o r m a t ”%s%s ” $basename ” ” ] $ d f t r u n n a m e ]

# Update t a r g e t l i b r a r y
set target library [ l i s t $target library $scan library ]

# S e t Scan C h a i n Type
s e t s c a n c o n f i g u r a t i o n −s t y l e m u l t i p l e x e d f l i p f l o p

# A u t o F i x f o r R e s e t and C l o c k
s e t d f t c o n f i g u r a t i o n −f i x r e s e t enable −f i x c l o c k enable

# Set Test Protocol

s e t t e s t d e f a u l t p e r i o d 100
s e t d f t s i g n a l −view e x i s t i n g d f t −t y p e S c a n C l o c k −t i m i n g {45 55} −p o r t c l k
s e t d f t s i g n a l −view e x i s t i n g d f t −t y p e R e s e t − a c t i v e s t a t e 1 −p o r t r e s e t
s e t d f t s i g n a l −view e x i s t i n g d f t −t y p e C o n s t a n t − a c t i v e s t a t e 1 −p o r t t e s t m o d e
create test protocol

# DFT Check
d f t d r c −v e r b o s e

# Add d e l a y i n g e n e r a t e d c l o c k s
c r e a t e c l o c k c l k −p e r i o d 1000
s e t i n p u t d e l a y 250 s i −c l o c k c l k
s e t i n p u t d e l a y 150 s e −c l o c k c l k

# Partial Scan
# set scan element false {state reg 3 }
# set scan element false {state reg 2 }
# set scan element false {state reg 1 }
# set scan element false {state reg 0 }

# T e s t −Ready S y n t h e s i s
c o m p i l e −s c a n

# Read D e s i g n & T e s t P r o t o c o l
# W r i t e o u t t h e t e s t p r o t o c o l and s c a n −r e a d y d e s i g n
# w r i t e t e s t p r o t o c o l −o u t p u t [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . s p f ” ]
# w r i t e −f o r m a t ddc − h i e r a r c h y −o u t p u t [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . ddc ” ]

# Read d e s i g n and t e s t p r o t o c o l
# r e a d f i l e −f o r m a t ddc [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . ddc ” ]
# c u r r e n t d e s i g n [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . ddc ” ] : $basename

27
# link
# r e a d t e s t p r o t o c o l [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . s p f ” ]

# S p e c i f y Scan C h a i n
s e t s c a n c o n f i g u r a t i o n −c h a i n c o u n t 1
s e t s c a n c o n f i g u r a t i o n −c l o c k m i x i n g no mix
s e t d f t s i g n a l −view s p e c −t y p e S c a n D a t a I n −p o r t s i
s e t d f t s i g n a l −view s p e c −t y p e S c a n D a t a O u t −p o r t s o
s e t d f t s i g n a l −view s p e c −t y p e S c a n E n a b l e −p o r t s e − a c t i v e s t a t e 1
s e t s c a n p a t h chain1 −s c a n d a t a i n s i −s c a n d a t a o u t so

# Memory Wrapper
# s e t t e s t p o i n t e l e m e n t −t y p e o b s e r v e [ g e t o b j e c t n a m e [ g e t p i n s RAM 64B / D∗ ] ] − c l o c k s i g n a l
# s e t t e s t p o i n t e l e m e n t −t y p e o b s e r v e [ g e t o b j e c t n a m e [ g e t p i n s RAM 64B / A∗ ] ] − c l o c k s i g n a l
# s e t t e s t p o i n t e l e m e n t −t y p e c o n t r o l 0 1 [ g e t o b j e c t n a m e [ g e t p i n s RAM 64B / Q∗ ] ] − c l o c k s i g
#report test point element

# Scan P r e v i e w
p r e v i e w d f t −show a l l
preview dft −t e s t p o i n t s all

# Scan C h a i n S y n t h e s i s
insert dft

# Scan C h a i n I d e n t i f i c a t i o n
set scan state scan existing

# DRC & C o v e r a g e
d f t d r c −c o v e r a g e e s t i m a t e

# R e p o r t Scan I n f o r m a t i o n
r e p o r t s c a n p a t h −view e x i s t i n g d f t −c h a i n a l l
r e p o r t s c a n p a t h −view e x i s t i n g d f t − c e l l a l l

# P r e p a r e TetraMax s c r i p t
change names −h i e r a r c h y −r u l e v e r i l o g
w r i t e −f o r m a t v e r i l o g − h i e r a r c h y −o u t [ f o r m a t ”%s%s%s ” . / s r c / $ f i l e b a s e ” . v ” ]
w r i t e −f o r m a t ddc − h i e r a r c h y −o u t p u t [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . ddc ” ]
w r i t e s c a n d e f −o u t p u t [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . d e f ” ]
set t e s t s t i l n e t l i s t f o r m a t verilog
w r i t e t e s t p r o t o c o l −o u t p u t [ f o r m a t ”%s%s%s ” . / r e p o r t s / $ f i l e b a s e ” . s p f ” ]

####################################
# Q u i t dc
####################################
quit

D Script for TetraMax

##################################################################
####
#### M o d i f i e d by Anh Luong & A n d r z e j F o r y s
#### U n i v e r s i t y o f Utah
#### F a l l 2012

28
####
#### TetraMax S c r i p t f o r ECE 128
#### P e r f o r m s ATPG P a t t e r n G e n e r a t i o n f o r S y n o p s y s G e n e r i c f i l e s
#### author : t j f
#### u p d a t e : wgibb , s p r i n g 2010

#### n o t e : t h i s s c r i p t w i l l o n l y r u n i n TMAX TCL mode

#### s t a r t tmax l i k e t h i s : tmax − t c l
#### s o u r c e t m a x a t p g . t c l
##################################################################

############################################################
#### l o c a l v a r i a b l e s , d e s i g n e r must c h a n g e t h e s e v a l u e s ####
############################################################
s e t top module c o n t r o l l e r
s e t s y n t h e s i z e d f i l e s [ l i s t . / s r c / ${ top module } s c a n . v ]
set c e l l l i b . / UofU Digital v1 2 . v
s e t s c a n l i b . / foo . v
s e t s t i l f i l e [ l i s t . / r e p o r t s / ${ t o p m o d u l e } s c a n . s p f ]

# C o n t i n u e e x e c u t i o n when command r e t u r n s an e r r o r
# set command n o a b o r t

b u i l d −f o r c e

#################################################
#### r e a d i n s t a n d a r d c e l l s and u s e r ’ s d e s i g n ###
#################################################
# remove any o t h e r d e s i g n s from d e s i g n c o m p i l e r ’ s memory
r e a d n e t l i s t −d e l e t e
# read in standard c e l l l i b r a r y
r e a d n e t l i s t $ c e l l l i b −l i b r a r y
# read in scan c e l l l i b r a r y
r e a d n e t l i s t $scan lib −l i b r a r y
# r e a d i n user ’ s s y n t h e s i z e d v e r i l o g code
read netlist $synthesized files

#################################################
#### BUILD and DRC t e s t model
#################################################
report modules −a l l
run build model $top module
# i g n o r i n g w a r n i n g s l i k e N20 o r B10
# S e t STIL f i l e from DFT C o m p i l e r
set drc $stil file
# r u n c h e c k t o s e e i f s y n t h e s i z e d c o d e v i o l a t e s any t e s t i n g r u l e s
run drc

#################################################
#### G e n e r a t e ATPG ( p a t t e r n s )− f u l l s e q u e n t i a l
#################################################
# capture all faults , 9 capture cycles
# s e t a t p g −c a p t u r e c y c l e s 9 −f u l l s e q a t p g
# remove faults −a l l

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report summaries f a u l t s patterns
add faults −a l l
# r u n a t p g i n f u l l s e q u e n t i a l mode f o r b e t t e r f a u l t c o v e r a g e
report summaries f a u l t s patterns
run atpg full sequential only
# write out p a t t e r n s ( overwrite old f i l e s )
report summaries f a u l t s patterns
w r i t e p a t t e r n s . / s r c / ${ t o p m o d u l e } t b p a t t e r n s . v − r e p l a c e − i n t e r n a l −f o r m a t v e r i l o g s i n g l e

#################################################
#### O u t p u t r e p o r t s
#################################################
r e p o r t p a t t e r n s − a l l >> . / r e p o r t s / $ { t o p m o d u l e } . tmax . p a t t e r n s
r e p o r t v i o l a t i o n s − a l l >> . / r e p o r t s / $ { t o p m o d u l e } . tmax . v i o l a t i o n s
r e p o r t f a u l t s −summary − c o l l a p s e d >> . / r e p o r t s / $ { t o p m o d u l e } . tmax . c o v e r a g e

#################################################
#### A n a l y z e F a u l t s
#################################################
# up t o u s e r t o r u n t h e s e commands , t h e y c a n i n s p e c t t h e f a u l t s and v a r i o u s r e a s o n s f o r the
# a n a l y z e f a u l t s − c l a s s an
# a n a l y z e f a u l t s − c l a s s an −v e r b o s e −max 3
# a n a l y z e f a u l t s i n a r e g r e g / p d r e g s c a n 0 / q −s t u c k 1

# E x i t t h e program
quit

E controller.v
module main ( i n p u t c l k , r e s e t ,
input [ 5 : 0 ] op / / ,
/ / input zero ,
/ / output reg memread , memwrite , a l u s r c a , memtoreg , i o r d ,
/ / output pcen ,
/ / output reg regwrite , regdst ,
/ / o u t p u t reg [ 1 : 0 ] pcsource , a l u s r c b , aluop ,
) ; / / output reg [ 3 : 0 ] i r w r i t e ) ;

parameter FETCH1 = 4 ’ b0001 ;

parameter FETCH2 = 4 ’ b0010 ;
parameter FETCH3 = 4 ’ b0011 ;
parameter FETCH4 = 4 ’ b0100 ;
parameter DECODE = 4 ’ b0101 ;
parameter MEMADR = 4 ’ b0110 ;
parameter LBRD = 4 ’ b0111 ;
parameter LBWR = 4 ’ b1000 ;
parameter SBWR = 4 ’ b1001 ;
parameter RTYPEEX = 4 ’ b1010 ;
parameter RTYPEWR = 4 ’ b1011 ;
parameter BEQEX = 4 ’ b1100 ;
parameter JEX = 4 ’ b1101 ;
parameter ADDIWR = 4 ’ b1110 ; / / a d d e d f o r ADDI

parameter LB = 6 ’ b100000 ;

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parameter SB = 6 ’ b101000 ;
parameter RTYPE = 6 ’ b0 ;
parameter BEQ = 6 ’ b000100 ;
parameter J = 6 ’ b000010 ;
parameter ADDI = 6 ’ b001000 ; / / / a d d e d f o r ADDI

reg [ 3 : 0 ] state , n e x t s t a t e ;
/ / reg pcwrite , pcwritecond ;

// state register
a l w a y s @( p o s e d g e c l k )
i f ( r e s e t ) s t a t e <= FETCH1 ;
e l s e s t a t e <= n e x t s t a t e ;

/ / next s t a t e logic
a l w a y s @( ∗ )
begin
case ( s t a t e )
FETCH1 : n e x t s t a t e <= FETCH2 ;
FETCH2 : n e x t s t a t e <= FETCH3 ;
FETCH3 : n e x t s t a t e <= FETCH4 ;
FETCH4 : n e x t s t a t e <= DECODE;
DECODE: c a s e ( op )
LB : n e x t s t a t e <= MEMADR;
SB : n e x t s t a t e <= MEMADR;
ADDI : n e x t s t a t e <= MEMADR; / / a d d e d f o r ADDI
RTYPE : n e x t s t a t e <= RTYPEEX ;
BEQ : n e x t s t a t e <= BEQEX ;
J: n e x t s t a t e <= JEX ;
d e f a u l t : n e x t s t a t e <= FETCH1 ; / / s h o u l d n e v e r h a p p e n
endcase
MEMADR: c a s e ( op )
LB : n e x t s t a t e <= LBRD ;
SB : n e x t s t a t e <= SBWR;
ADDI : n e x t s t a t e <= ADDIWR; / / a d d e d f o r ADDDI
d e f a u l t : n e x t s t a t e <= FETCH1 ; / / s h o u l d n e v e r h a p p e n
endcase
LBRD : n e x t s t a t e <= LBWR;
LBWR: n e x t s t a t e <= FETCH1 ;
SBWR: n e x t s t a t e <= FETCH1 ;
RTYPEEX : n e x t s t a t e <= RTYPEWR;
RTYPEWR: n e x t s t a t e <= FETCH1 ;
BEQEX : n e x t s t a t e <= FETCH1 ;
JEX : n e x t s t a t e <= FETCH1 ;
ADDIWR: n e x t s t a t e <= FETCH1 ; / / a d d e d f o r ADDI
d e f a u l t : n e x t s t a t e <= FETCH1 ; / / s h o u l d n e v e r h a p p e n
endcase
end

a l w a y s @( ∗ )
begin
/ / s e t a l l o u t p u t s to zero , then c o n d i t i o n a l l y a s s e r t j u s t the a p p r o p r i a t e ones
i r w r i t e <= 4 ’ b0000 ;
p c w r i t e <= 0 ; p c w r i t e c o n d <= 0 ;

31
r e g w r i t e <= 0 ; r e g d s t <= 0 ;
memread <= 0 ; memwrite <= 0 ;
a l u s r c a <= 0 ; a l u s r c b <= 2 ’ b00 ; a l u o p <= 2 ’ b00 ;
p c s o u r c e <= 2 ’ b00 ;
i o r d <= 0 ; memtoreg <= 0 ;
case ( s t a t e )
FETCH1 :
begin
memread <= 1 ;
i r w r i t e <= 4 ’ b0001 ; / / c h a n g e t o r e f l e c t new memory
a l u s r c b <= 2 ’ b01 ; // g e t t h e IR b i t s i n t h e r i g h t s p o t s
p c w r i t e <= 1 ; // FETCH 2 , 3 , 4 a l s o c h a n g e d . . .
end
FETCH2 :
begin
memread <= 1 ;
i r w r i t e <= 4 ’ b0010 ;
a l u s r c b <= 2 ’ b01 ;
p c w r i t e <= 1 ;
end
FETCH3 :
begin
memread <= 1 ;
i r w r i t e <= 4 ’ b0100 ;
a l u s r c b <= 2 ’ b01 ;
p c w r i t e <= 1 ;
end
FETCH4 :
begin
memread <= 1 ;
i r w r i t e <= 4 ’ b1000 ;
a l u s r c b <= 2 ’ b01 ;
p c w r i t e <= 1 ;
end
DECODE: a l u s r c b <= 2 ’ b11 ;
MEMADR:
begin
a l u s r c a <= 1 ;
a l u s r c b <= 2 ’ b10 ;
end
LBRD :
begin
memread <= 1 ;
iord <= 1 ;
end
LBWR:
begin
r e g w r i t e <= 1 ;
memtoreg <= 1 ;
end
SBWR:
begin
memwrite <= 1 ;
iord <= 1 ;

32
 end
RTYPEEX :
begin
a l u s r c a <= 1 ;
aluop <= 2 ’ b10 ;
end
RTYPEWR:
begin
regdst <= 1 ;
r e g w r i t e <= 1 ;
end
BEQEX :
begin
alusrca <= 1 ;
aluop <= 2 ’ b01 ;
p c w r i t e c o n d <= 1 ;
pcsource <= 2 ’ b01 ;
end
JEX :
begin
p c w r i t e <= 1 ;
p c s o u r c e <= 2 ’ b10 ;
end
ADDIWR: / / new s t a t e f o r a d d i w r i t e b a c k
begin
r e g w r i t e <= 1 ;
end
endcase
end
a s s i g n pcen = p c w r i t e | ( p c w r i t e c o n d & z e r o ) ; / / program c o u n t e r e n a b l e

endmodule

F expAdd.v
module expAdd ( Ex , Ey , Ez , B ) ;
i n p u t [ 7 : 0 ] Ex , Ey ;
input [ 6 : 0 ] B;
o u t p u t [ 7 : 0 ] Ez ;

a s s i g n Ez = Ex + Ey − B ;

endmodule

33