Chapter7 InputOutput PDF
Chapter7 InputOutput PDF
Luis Tarrataca
[email protected]
CEFET-RJ
4 I/O Modules
Module Function
Control and Timing
Processor Communication
Device communication
Data buffering
Error detection
Programmed I/O
Luis Tarrataca Chapter 7 - Input / Output 2 / 85
Table of Contents II
I/O Commands
Interrupt-Driven I/O
Interrupt Processing
5 DMA Module
7 References
Motivation
• Peripheral speed;
Why not connect the peripherals directly to the bus? Any ideas?
Why not connect the peripherals directly to the bus? Any ideas?
Why not connect the peripherals directly to the bus? Any ideas?
Why not connect the peripherals directly to the bus? Any ideas?
Why not connect the peripherals directly to the bus? Any ideas?
Succinctly:
• Detect errors.
Address Lines
µP Data Lines
Control Lines
I/O Module
What do you think are the main components of an external device? Any
ideas?
Control Signals:
• Report status;
Data signals:
Status signals:
Control logic:
Transducer:
• Converts data:
• From electrical to other forms of energy during output;
Buffer:
• To hold data.
Module Function
• Processor communication;
• Device communication;
• Data buffering;
• Error correction.
• Main memory and the system bus must be shared with the I/O function.
What do you think are the sequence of steps required for the processor
to interact with the I/O module? Any ideas?
• I/O module must communicate with the processor and external device
Processor Communication
• Command decoding:
• I/O module accepts commands from processor:
• Control bus signals
Processor Communication
• Data:
• Exchanged between the processor and the I/O module (data bus).
• Status reporting:
• Important to know the status of the I/O module;
• E.g.:
• Processor asks to read data from I/O module;
• But I/O module may not be ready;
• This happens because it may still be working on previous I/O command;
• This needs to be reported with a status signal;
Processor Communication
• Address recognition:
• Recall that each word of memory has an address;
• I/O module has one unique address for each peripheral it controls
Remember from the laboratory?
• Memory address for screen (FFFEh);
• Memory address for keyboard (FFFFh);
• Memory address for timer (FFF7h);
Device communication
I/O module must be able to perform device communication, involving:
• Commands;
• Status information;
• Data
If the I/O device operates at a rate higher than the memory access rate:
Error detection
I/O module is often responsible for error detection and reporting, e.g.:
• Data transferred to and from the module are buffered in data registers.
• Logic within the module interacts with the processor via control lines:
• Processor uses the control lines to issue commands to the I/O module;
• Taking most of the I/O processing burden away from the processor;
How can we manage the communication between the µP and the I/O
module?
• Any ideas?
Essentially, there are three techniques are possible for I/O operations:
Programmed I/O
Data are exchanged between the processor and the I/O module:
I/O Commands
I/O commands the processor can issue are of the following type (1/2):
• Has the most recent I/O operation completed? Did any errors occur?
I/O commands the processor can issue are of the following type (2/2):
In flowchart form:
Figure: Programmed I/O technique for input of a block of data (Source: [?])
Interrupt-Driven I/O
In flowchart form:
Interrupt Processing
7 Typically, the interrupt handler will begin by saving all registers on the stack;
How does the processor determine which device issued the interrupt?
If multiple interrupts have occurred, how does the processor decide which
one to process?
How does the processor determine which device issued the interrupt?
• Low number of interruption lines still means that we have to multiplex them.
• Software poll:
• Processors calls an interrupt routine that polls each I/O module.
How does the processor determine which device issued the interrupt?
• ACK goes through the I/O modules until it gets to the requesting module;
• Word is either:
• Address of the I/O module or;
• Address of an adequate interruption handling technique.
If multiple interrupts have occurred, how does the processor decide which
one to process?
• This time could be spent doing something more useful: real processing!
Despite the improvement, can you see any potential upgrade that can
be performed with interrupt I/O?
Despite the improvement, can you see any potential upgrade that can
be performed with interrupt I/O?
DMA module
• Uses the bus only when the processor does not need to or...
• ...Forces the processor to suspend bus operations temporarily;
Luis Tarrataca Chapter 7 - Input / Output 71 / 85
DMA Module
• end of transfer;
How can the DMA module use the bus? Any ideas?
Idea:
• DMA module transfers one word and returns control to the processor
Figure: DMA and interrupt breakpoints during an instruction cycle (Source: [?])
In this example:
In this example:
In this example:
• I/O modules are connected to the DMA module using an I/O bus;
In essence:
Your focus should always be on the building blocks for developing a solution
=)
References I
Stallings, W. (2015).
Pearson Education.