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The document discusses using Design Compiler to synthesize an adder circuit from Verilog code. It describes setting up the environment, reading in the file, synthesizing the design, and reporting on the resources and timing. It also covers changing the adder implementation and comparing different adder types.

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Lab3 New PDF

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陳美如
50 views17 pages
The document discusses using Design Compiler to synthesize an adder circuit from Verilog code. It describes setting up the environment, reading in the file, synthesizing the design, and reporting on the resources and timing. It also covers changing the adder implementation and comparing different adder types.

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The document discusses using Design Compiler to synthesize an adder circuit from Verilog code. It describes setting up the environment, reading in the file, synthesizing the design, and reporting on the resources and timing. It also covers changing the adder implementation and comparing different adder types.

Copyright:

© All Rights Reserved
Download as PDF, TXT or read online from Scribd
Download as pdf or txt
50 views17 pages

Lab3 New PDF

Uploaded by

陳美如
The document discusses using Design Compiler to synthesize an adder circuit from Verilog code. It describes setting up the environment, reading in the file, synthesizing the design, and reporting on the resources and timing. It also covers changing the adder implementation and comparing different adder types.

Copyright:

© All Rights Reserved
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You are on page 1/ 17

Lab3

Design Compiler - Adder


Dr. Yu Cheng Fan
National Taipei University of Technology, Taipei, Taiwan
Environment Setup
Copy File for Environment Setting
cd□~   Go to root

cp□/home/standard/Environment_Setup_File/synthesis_setup_for_18/synopsys_d
c.setup□.synopsys_dc.setup

□ ←Press Space 

Copy File for Synthesis
cp □‐r□/home/standard/electronic_circuit_102□.      

Don’t forgot this point

2
Open Design Vision

Use commend
cd electronic_circuit_102/lab3
Then commend dv

3
Read file
1

4
Verilog code
module lab1(a,b,c,sel,z);
input [7:0] a,b,c;
input sel;
output reg [8:0] z;

always @(*) 
begin
if (sel) z = a + b; Synthesize if..else
else z = a + c; adder logic circuits
end
endmodule

5
Synthesize Design
1

New Cell
6
Report - Resources

1
Press OK, Display Report

7
Report – Timing Path

1
2

8
Adder Architecture
1 2

Double Click 4
3

9
Report (1)
 Use “Design/Report Design Resource”
 Adder type(current implementation)=_______

 Use “Design/Report Area ＆ Timing/Report Timing”
 Area (total cell area)=______ μm2
 Timing (data arrival time)=______ ns

10
Set Timing Constraints
2
1
4
3
Choose
In/Output port

6
11
Report (2)
 After setting, “Design/Compile Design”  to synthesize 
design again.

 Use “Design/Report Design Resources” to see what type of 
adder is used?
 Adder type=________

 Use “Design/Report Area ＆ Timing/Report Timing”
 Area(total cell area)=______  μm2
 Timing(data arrival time)=______ ns
 Slack =_______  ns
12
Change Different DesignWare
 Change the type of adder, input commend 
“set_implementation cla r301”for .72.28
“set_implementation cla r300”for .72.42
 Recompile “Design/Compile Design”

13
Report (3)
 Use “Design/Report Design Resources” to see what 
type of adder is used?
 Adder type=______

 Use “Design/Report Area ＆ Timing/Report Timing”,
 Area:________ μm2
 Timing:______  (arrival) ns    
 Slack:________  (violated) ns

14
Comparison
 What the difference between the three types of adder?

Rpl: Ripple‐carry adder
Cla: Carry‐look ahead adder
Pparch: Parallel‐Prefix Adder Architecture

15
Different Conditions
 1. Repeat page 4‐page 10 (5 Times)
 2. In page 6, set different area, power, map conditions.
 3. Excel file (Adder type, Area, Power, Timing)

16
Dr. Yu Cheng Fan National Taipei University of Technology Taipei, Taiwan 17

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