CHAPTER 4

4. DESCRIPTION OF MICROCONTROLLER

Fig 4.1 Block Diagram of Microcontroller

EXTERNAL
INTRRUPTS ON-CHIP
ROM FOR TIMER0
PROGRAM ON-CHIP
INTERRUPT RAM
CODE TIMER1
CONTROL

COUNTER
INPUTS
CPU

BUS 4 I/O SERIAL

OSC
CONTROL PORTS PORT

P0 P1 P2 P3 TXD RXD

ADDRESS/DATA

INTERNAL LAYOUT OF MICROCONTROLLER

 Fig 4.2 Internal Layout of Microcontroller

4.1. DESCRIPTION OF 89C51 MICROCONTROLLER

Phillips 89C51 contains a non-volatile FLASH program memory that is parallel

programmable. Phillips 89C51, 8-bit Micro controller from MHS-51 Intel family, with
4K bytes of flash and 128 bytes of internal RAM had been used. It has a 40-pin
configuration and other components of interfaced to its ports. The Micro controller takes
input from the external sources and routes them to the appropriate devices as
programmed in it.

4.2. FEATURES

 89C51 Central Processing Unit

 On-chip FLASH Program Memory

 Speedup to 33 MHz

 Fully Static Operation

 RAM expandable externally up to 64 Kbytes

 Four interrupt priority levels

 Six interrupt sources

 Four 8-bit input output ports

 Full-duplex enhanced UART

• -Framing error detection

• -Automatic address recognition

 Three 16-bit timers/counters T0, T1and additional T2

 Power control modes

• -Clock can be stopped and resumed

• -Idle mode

• -Power down mode

 Programmable clock out

  Second DPTR register

 Asynchronous port reset

 Low EMI

 Wakeup from power down by an external interrupt

 Flash memory features

• FLASH EPROM internal program memory with chip erases.

• Up to 64K byte external program memory if the internal program

memory is disabled

• Programmable security bits.

• 10,000 minimum erase/program cycles for each byte

• 10 year minimum data retention

• Programming support available from many popular vendors.

CPU
The microcontroller consists of eight bit ALU with associated registers like register A,
register B, PSW (program status word), SP (stack pointer), and a 16-bit PC (program
counter) and a 16-bit DPTR (data pointer) register.

ALU
The ALU performs arithmetic and logic functions on 8-bit variables. The ALU can
perform addition, subtraction, multiplication and division and the logic unit can perform
logical operations. An important and unique feature of the microcontroller architecture is
that the ALU can also manipulate 1 bit as well as 8-bit data types. Individual bits may be
set, cleared, complemented, moved, tested and used in logic computation.

ACCUMULATOR
It is returned as register A or Acc. It is an 8-bit Register. Accumulator holds a source of
operand and stores the result of the arithmetic operations such as addition, subtraction,
 multiplication and division. The accumulator can be the source or destination register for
logical operations. The accumulator has several exclusive functions such as rotate,
parity computation; testing for 0, sign acceptor etc. and so on.

PROGRAM COUNTER
The program counter points to the address of the next instruction to be executed. As the
CPU fetches the opcode from the program ROM, the program counter is implemented to
point to the next instruction. The microcontroller can access program addresses 0000 to
FFFFH, a total of 64K bytes of code.
PSW (program status word) register:
The program status word (PSW) register is on 8-bit register. It is also referred to as the
flag register.

Table 4.1 Flags Status

7 6 5 4 3 2 1 0

CY AC ------ RS1 RS0 OV ------ P

CY Carry-flag.
AC Auxiliary carry-flag.
---- Available to the user for general-purpose.
RS1 register bank selector bit 1.
RS0 register bank selector bit 0.
OV overflow flag.
---- User definable bit.
P Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even
member of 1 bit in the accumulator.
 Fig 4.3 Pin Diagram of Philips 89C51 Microcontroller

4.3 PIN DESCRIPTION

 1–8: Port 1; Each of these pins can be used as either input or output according to
your needs. Also, pins 1 and 2 (P1.0 and P1.1) have special functions associated
with Timer.

 9: Reset Signal; high logical state on this input halts the MCU and clears all the
registers. Bringing this pin back to logical state zero starts the program a new as if
the power had just been turned on. In another words, positive voltage impulse on
this pin resets the MCU. Depending on the device's purpose and environs, this pin
is usually connected to the push-button, reset-upon-start circuit or a brown out
reset circuit (covered in the previous chapter). The image shows one simple
circuit for safe reset upon starting the controller. It is utilized in situations when
power fails to reach its optimal voltage.
 Fig 4.4 Description of Reset pin

 10-17: Port 3 as with Port 1, each of these pins can be used as universal input or
output. However, each pin of Port 3 has an alternative function:

 Pin 10: RXD - serial input for asynchronous communication or serial output for
synchronous communication.

 Pin 11: TXD - serial output for asynchronous communication or clock output for
synchronous communication

 Pin 12: INT0 - input for interrupt 0

 Pin 13: INT1 - input for interrupt 1

 Pin 14: T0 - clock input of counter 0

 Pin 15: T1 - clock input of counter 1

 Pin 16: WR - signal for writing to external (add-on) RAM memory

 Pin 17: RD - signal for reading from external RAM memory.

 18-19: X2 and X1; Input and output of internal oscillator. Quartz crystal
controlling the frequency commonly connects to these pins. Capacitances within
the oscillator mechanism (see the image) are not critical and are normally about
30pF. Instead of a quartz crystal, miniature ceramic resonators can be used for
dictating the pace. In that case, manufacturers recommend using somewhat higher
capacitances (about 47 puffs). New Mucus works at frequencies from 0Hz to
50MHz+.

Fig 4.5 Description of XTAL1 and XTAL2 pins

 20: GND; Ground

 21- 28: Port 2 if external memory is not present, pins of Port 2 act as universal
input/output. If external memory is present, this is the location of the higher
address byte, i.e. addresses A8 – A15. It is important to note that in cases when
not all the 8 bits are used for addressing the memory (i.e. memory is smaller than
64kB), the rest of the unused bits are not available as input/output.
  29: PSEN; MCU activates this bit (brings to low state) upon each reading of byte
(instruction) from program memory. If external ROM is used for storing the
program, PSEN is directly connected to its control pins.

 Of the external memory, MCU sends the lower byte of the address register
(addresses A0 – A7) to port P0 and activates the output ALE. External register
(74HCT373 or 74HCT375 circuits are common), memorizes the state of port P0
upon receiving a signal from ALE pin, and uses it as part of the address for
memory chip. During the second part of the mechanical MCU cycle, signal on
ALE is off, and port P0 is used as Data Bus. In this way, by adding only one
cheap integrated circuit, data from port can be multiplexed and the port
simultaneously used for transferring both addresses and data.

 31: EA; Bringing this pin to the logical state zero (mass) designates the ports P2
and P3 for transferring addresses regardless of the presence of the internal
memory. This means that even if there is a program loaded in the MCU it will not
be executed, but the one from the external ROM will be used instead. Conversely,
bringing the pin to the high logical state causes the controller to use both
memories, first the internal, and then the external (if present).

 32-39: Port 0 Similar to Port 2, pins of Port 0 can be used as universal

input/output, if external memory is not used. If external memory is used, P0
behaves as address output (A0 – A7) when ALE pin is at high logical level, or as
data output (Data Bus) when ALE pin is at low logical level.

 40: VCC; Power +5V.

4.4 Input – Output (I/O) Ports

Every MCU from 8051 families has 4 I/O ports of 8 bits each. This provides the user with
32 I/O lines for connecting MCU to the environs. Unlike the case with other controllers,
there is no specific SFR register for designating pins as input or output. Instead, the port
itself is in charge: 0=output, 1=input. If particular pin on the case is needed as output, the
appropriate bit of I/O port should be cleared. This will generate 0V on the specified
controller pin. Similarly, if particular pin on the case is needed as input, the appropriate
bit of I/O port should be set. This will designate the pin as input, generating +5V as a side
effect (as with every TTL input).

Port 0

Port 0 has two-fold role: if external memory is used, it contains the lower address byte
(addresses A0-A7); otherwise all bits of the port are either input or output. Another
feature of this port comes to play when it has been designated as output. Unlike other
ports, Port 0 lacks the "pull up" resistor (resistor with +5V on one end). This seemingly
insignificant change has the following consequences:When designated as input, pin of
Port 0 acts as high impedance offering the infinite input resistance with no "inner"
voltage.

When designated as output, pin acts as "open drain". Clearing a port bit grounds the
appropriate pin on the case (0V). Setting a port bit makes the pin act as high impedance.
Therefore, to get positive logic (5V) at output, external "pull up" resistor needs to be
added for connecting the pin to the positive pole.

Therefore, to get one (5V) on the output, external "pull up" resistor needs to be added for
connecting the pin to the positive pole.

Port 1

This is "true" I/O port, devoid of dual function characteristic for Port 0. Having the "pull
up" resistor, Port 1 is fully compatible with TTL circuits.

Port 2

When external memory is used, this port contains the higher address byte (addresses A8–
A15), similar to Port 0. Otherwise, it can be used as universal I/O port.

Port 3
Beside its role as universal I/O port, each pin of Port 3 has an alternate function. In order
to use one of these functions, the pin in question has to be designated as input, i.e. the
appropriate bit of register P3 needs to be set. From a hardware standpoint, Port 3 is
similar to Port 0.

As can be seen from the individual descriptions of the ports, they all share highly
similar structure. However, you need to consider which task should be assigned to which
port. For example: if utilizing port as output with high level (5V), avoid using Port 0, as
its pins cannot produce high logical level without an additional resistor connected to +5V.
If using other port to a same end, bear in mind that built-in resistors have relatively high
values, producing the currents limited to few hundreds of amperes as pin output.
 CHAPTER 5

5. MEMEORY ARCHITECTURE

5.1. Memory under the Magnifier

During the runtime, micro controller uses two different types of memory: one for holding
the program being executed (ROM memory), and the other for temporary storage of data
and auxiliary variables (RAM memory). Depending on the particular model from 8051
family, this is usually few kilobytes of ROM and 128/256 bytes of RAM. This amount is
built-in and is sufficient for common tasks performed "independently" by the MCU.
However, 8051 can address up to 64KB of external memory. These can be separate
memory blocks, (separate RAM chip and ROM chip) totaling 128KB of memory on
MCU, which is a real programming goody.

5.2 ROM memory

First models from 8051 families lacked the internal program memory, but it could be
added externally in a form of a separate chip. This Mucus can be recognized by their
mark, which begins with 803 (e.g. 8031 or 8032). New models have built-in ROM,
although there are substantial variations. With some models internal memory cannot be
programmed directly by the user. Instead, the user needs to precede the program to the
manufacturer, so that the MCU can be programmed (masked) appropriately in the process
of fabrication. Obviously, this option is cost-effective only for large series. Fortunately,
there are MCU models ideal for experimentation and small specialized series. Many
manufacturers deliver controllers that can be programmed directly by the user. These
come in a ceramic case with an opening (Erasable Programmable Read Only Memory,
EPROM version) or in a plastic case without an opening (Electrically Erasable
Programmable Read Only Memory, EEPROM version). This book deals with one of the
latter models that can be programmed via simple programmer, even if the chip has
already been mounted to the designated device.
5.3 RAM memory

Fig 5.1 Banks and Registers of RAM

RAM is used for storing temporary data and auxiliary results generated during the
runtime. Apart from that, RAM comprises a number of registers: hardware counters and
timers, I/O ports, buffer for serial connection, etc. With older versions, RAM spanned
256 locations, while new models feature additional 128 registers. First 256 memory
locations form the basis of RAM (addresses 0 – Fifth) of every 8051 MCU. Locations
that are available to the user span addresses from 0 to 7Fh, i.e. first 128 registers, and this
part of RAM is split into several blocks as can be seen in the image below.

 First block comprises 4 "banks" of 8 registers each, marked as R0 - R7. To

address these, the parent bank has to be selected.

 Second memory block (range 20h – 2Fh) is bit-addressable, meaning that every
belonging bit has its own address (0 to 7Fh). Since the block comprises 16 of
these registers, there is a total of 128 addressable bits. (Bit 0 of byte 20h has bit
address 0, while bit 7 of byte 2Fh has bit address 7Fh).

 Third is the group of available registers at addresses 2Fh – 7Fh (total of 80

locations) without special features or a preset purpose.

5.4. Extra Memory Block

To satisfy the programmers' ever-increasing demands for RAM, latest 8051 models were
added an extra memory block of 128 locations. But it is not all that simple... The problem
lies in the fact that the electronics, which addresses RAM, employs 1 byte (8 bits),
reaching only the first 256 locations. Therefore, a little trick had to be applied in order to
keep the existing 8-bit architecture for the sake of compatibility with older models. The
idea is to make the additional memory block share the addresses with the existent
locations intended for SFR registers (80h - Fifth). For distinguishing these two physically
separate memory areas, different methods of addressing are used: if SFR registers are in
question, direct addressing is used; for extra RAM locations, indirect addressing is used.

5.5 Memory Expanding

In case the built-in amount of memory (either RAM or ROM) is not sufficient for your
needs, there is always an option of adding two external 64KB memory chips. When
added, they are addressed and accessed via I/O ports P2 and P3. From user's point of
view it's all very simple, because if properly connected most of the job is carried out
automatically by MCU.

8051 MCU has two separate read signals, RD# (P3.7) and PSEN#. The first one is active
when reading byte from the external data memory (RAM), and the second one is active
when reading byte from the external program memory (ROM). Both signals are active on
low logical level. The following image shows a typical scheme for such expansion using
separate chips for RAM and ROM, known as Harvard architecture.
 Fig 5.2 Expansion of RAM and ROM

Memory can be also mapped as a single block, functioning as both data memory and
program memory simultaneously (only one memory chip is used).

This approach is known as Von Neumann architecture. To be able to read the same block
using RD# or PSEN#, these two signals were combined via logical AND. In this way,
output of AND circuit is low if any of the two inputs is low.

Using the Hardware architecture effectively doubles MCU memory, but that's not the
only advantage offered by the method. Keeping the program code separated from the data
makes the controller more reliable

5.6 SFR Registers (Special Function Registers)

SFR registers can be seen as a sort of control panel for managing and monitoring the
micro controller. Every register and each of the belonging bits has its name, specified
address in RAM and strictly defined role (e.g. controlling the timer, interrupt, serial
connection, etc). Although there are 128 available memory slots for allocating SFR
registers, the basic core shared by 8051 MCU has 22 registers. The rest has been left open
intentionally to allow future upgrades while retaining the compatibility with earlier
models. This fact makes possible to use programs developed for obsolete models long
ago.

ADDR.
(HEX.) MARK FULL NAME
80 P0 PORT 0
81 SP STACK POINTER
DPTR DATA POINTER
82 DPL DATA LOW POINTER
83 DPH DATA HIGH POINTER
87 PCON POWER CONTROL
88 TCON TIMER/COUNTER CONTROL
89 TMOD TIMER/COUNTER MODE CONTROL
8A TL0 TIMER/COUNTER0 LOW BYTE
8B TL1 TIMER/COUNTER1 LOW BYTE
8C TH0 TIMER/COUNTER0 HIGH BYTE
8D TH1 TIMER/COUNTER1 HIGH BYTE
90 P1 PORT 1
98 SCON SERIAL PORT CONTROL
99 SBUF SERIAL DATA PORT
 A0 P2 PORT 2
A8 IE INTERRUPT ENABLE
B0 P3 PORT 3
B8 IP INTERRUPT PRIORITY CONTROL
D0 PSW PROGRAM STATUS WORD
E0 ACC(A) ACCUMULATOR
F0 B B REGISTER
Table 5.1 Special Function registers

5.7. Timer 0 and Timer 1

The "timer” or "counter "function is selected by control bits C/T in the special function
register TMOD. These two timer/counters have for operating modes, which are selected
by bit-pairs (M1/M0) in TMOD. Modes 0, 1, and 2 are the same for both
timers/counters. Mode 3 is different.

5.7.1. TMOD (timer mode) registers

Table 5.2 Timer Modes Register

7 6 5 4 3 2 1 0

GATE C/T M1 M0 GATE C/T M1 M0

----------------- TIMER 1 ----------------------- --------------------TIMER 0 ----------------

GATE : When set, start and stop of timer by hardware

When reset, start and stop of timer by software

C/T : Cleared for timer operation

Set for counter operation
 Table 5.3 Modes of TMOD Register

M1 M0 MODE OPERATING MODE

0 0 0 13-bit timer mode

0 1 1 16-bit timer mode

1 0 2 8-bit auto reload mode

1 1 3 Split timer mode

5.7.2 TCON (timer control register)

Address =88H.
Bit addressable.

Table 5.4 Timer Control Register

7 6 5 4 3 2 1 0

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

TF: timer overflows flag. Set by hardware when the timer/counter overflows. It is
cleared by hardware, as the processor vectors to the interrupt service routine.

TR: timer run control bit. Set or cleared by software to turn timer or counter on/off.

IE: set by CPU when the external interrupt edge (H-to-L transition) is detected. It is
cleared by CPU when the interrupt is processed.

IT: set/cleared by software to specify falling edge/low-level triggered external interrupt.

 CHAPTER 6

6. SERIAL COMMUNICATION

When a microprocessor communicates with the outside world, it provides data in byte-
sized chunks. In some cases, such as printers, the information is simply grabbed from the
8-bit data bus and presented to the 8-bit data bus of the printer. This can work only if the
cable is not too long, since long cables diminish and ever distort signals. Furthermore,
and 8-bit data path is expensive. For these reasons, serial communication is used for
transferring data between two systems located at distances of hundreds of feet to millions
of miles apart.

The fact that in serial communication a single data line is used instead of the 8-bit data
line of parallel communication makes it not only much cheaper but also makes it possible
for two computers located in two different cities to communicate over the telephone.

Serial data communication uses two methods, a synchronous and synchronous. The
synchronous method transfers a block of data at a time while the synchronous transfers a
single byte at a time. It is mean possible to write software to use either of these methods,
but the programs can be tedious and long. For this reason, there are special IC chips
made by many manufacturers for serial data communications. These chips are commonly
referred to as UART (universal asynchronous receiver-transmitter) and USART
(universal synchronous -asynchronous receiver-transmitter). The8051 chips has built-in
UART, which is discussed

1 0 01 0 1
11001010

Sender Receiver
 1 0 01 0 1
11001010

Sender Receiver

Fig 6.1 Serial Communication

6.1. Asynchronous serial communication and data framing

The data coming in at the receiving end of the data line in a serial data transfer is all 0's
and 1's; it is difficult to make sense of the data unless the sender and receiver agree on a
set of rules, a protocol, on how the data is packed, how many bits constitute the character,
and when the data begins and ends.

6.1.1 Start and stop bits

Asynchronous serial data communication is widely used for character orientation

transmissions. In the asynchronous method, each character is placed in between start
and stop bits. This is the called framing. In data framing for asynchronous
communications, the data, such as ASCII characters, are packed in between a start
bit and a stop bits. The start bit is always one-bit but the stop bit can be one or two
bits. The start bit is always a 0 and the stop bit is 1.

6.1.2. Parity bit

In some systems in order to maintain data integrity, the parity bit of the character
byte is included in the data frame. This means that for each character we have a
single parity bit in addition to start and stop bits. The parity bit is odd or even. In
case of an odd parity bit the number of data bits of a book of including the parity bit,
is even.
6.1.3. Data transfer rate

The rate of data transfer in serial data communication is stated in bps (bits per
second). Another widely used terminology for bps is baud rate. Baud rate is
defined as the number of signal changes per second. As far as the conductor wire is
concerned, the baud rates as bps are the same.

0 1 0 0 0 0 0 1 Start
stop mark
Space bit
bit
d7 d0
Goes out last Goes out first

Fig 6.2 Data Framing

MAX
System Micro
232
Controller

Line Driver/Voltage Converter

RS232 Level TTL Level

 Fig 6.3 Data transfer between 89C51 and System

6.2. RS232 standards

To allow compatibility among the data communication equipment made by various

manufacturers; an interfacing standard called RS232, was set by the electronics industries
association (EIA) in 1960. RS 232 is the most widely used serial input-output interfacing
standard. In RS 232, a 1 is represented by -3 to -25V, while a 0 bit is + 3 to + 25V. To
connect any RS 232 to a µc system, voltage converters such as Max 232are used. Max
232 IC chips are commonly referred to as line drivers.

RS232 CONNECTORS
 1 13
1

14 RS232P (DB25)
1 25

RS232P (DB9) RS232S (DB9)

Fig 6.4 Pin Diagram of RS232 Connector

RS232 STANDARDS

RS232 PINS

Pin Description
1 Protective ground
2 Transmitted data (TxD)
3 Received data (RxD)
4 Request to send (RTS)
 5 Clear to send (CTS)
6 Data set ready (DSR)
7 Signal ground (GND)
8 Data carrier detect (DCD)
9/10 Reserved for data setting
11 Unassigned
12 Secondary data carrier
13 Secondary clear send
14 Secondary transmitted data
15 Transmit signal element timing
16 Secondary received data
17 Receive signal element timing
18 Unassigned
19 Secondary request to send
20 Data terminal ready (DTR)
21 Signal quality detector
22 Ring indicator
23 Data signal rate select
24 Transmit signal element timing
25 Unassigned

6.3. MAX 232

The RS 232 is not compatible with micro controllers, so a line driver converts the RS
232's signals to TTL voltage levels.

The MAX232 is a dual driver/receiver that includes a capacitive voltage generator to

supply TIA/EIA-232-F voltage levels from a single 5-V supply. Each receiver converts
TIA/EIA-232-F inputs to 5-V TTL/CMOS levels. These receivers have a typical
threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs.
Each driver converts TTL/CMOS input levels into TIA/EIA-232-F levels.

8051
P3.1 11
TxD

12
P3.0

RxD

Fig 6.5 Describing the Function of Max 232

6.4 REGITERS USED FOR COMMUNICATION

SBUF Register:
SBUF is an 8-bit register used solely for serial communication in the 8051. For byte of
data to be transferred via TxD line, it must be placed in SBUF register. SBUF also holds
the byte of data when it is received by the 8051’s RxD line.

The moment a byte is written into SBUF, it is framed with the start and stop bits and
transferred serially via TxD line. Similarly when bits r received serially via RxD, the
8051 defames it by eliminating a byte out of the received, and then placing it in the
SBUF.

SCON (Serial control register)

Bit addressable.
 Address location 98H

Table 6.1 Serial control register

7 6 5 4 3 2 1 0

SMO/FE SM1 SM0 REN TB8 RB8 TI RI

REN - set or cleared by software to enable or disable reception.

TB 8 -not widely used.
RB 8 - not widely used.
TI - transmits interrupt flag. Set by hardware at the beginning of the
stop bit in mode 1. It must be cleared by software.

RI - received interrupts flag. Set by hardware halfway through the stop

bit time in mode 1. It must be cleared by software.

Table 6.2 Modes of SCON

SM 0 SM1 Serial mode 0

0 0 Synchronous mode
0 1 8-bit data, 1 start bit, 1 stop bit, variable baud rate
1 0 9- bit data, 1 start bit, 1 stop bit, fixed baud rate
1 1 9- bit data, 1 start bit, 1 stop bit, variable baud rate

6.5 INTERRUPTS

A single microcontroller can serve several devices. In the interrupt method, whenever any
device needs its service, the device notifies the microcontroller by sending it an interrupt
signal. Upon receiving an interrupt signal, the microcontroller interrupts whatever it is
doing and serves the device. The program associated with the interrupt is called the
interrupt service routine (ISR). The advantageous of interrupts is that the microcontroller
can serve many devices based on the priority assigned to it.

Six interrupts in the 89C51:

1. Reset.
2. Two interrupts are set aside for the timers.
3. Two interrupts are set aside for hardware external hardware interrupts.
4. Serial Communications has a single interrupt (receive and transfer).

6.5.1 Interrupt enable (IE) register

Table 6.3 Interrupt Enable register:

7 6 5 4 3 2 1 0

EA ----- ET2 ES ET1 EX1 ET0 EX0

EA disable all interrupts. If EA = 0, now interrupt is acknowledged. If EA = 1, each

interrupt source is individually enabled or disabled by setting or clearing its enable a lap
bit.
---- Not implemented, reserved for future use.
ET2 enables or disables timer 2 overflow or capturer interrupt.
ES enables or disables the serial port interrupt.
ET1 enables or disables timer 1 overflow interrupt.
EX1 enables or disables external interrupt 1.
ET0 enables or disables timer 0 overflow interrupt.
EX0 enables or disables external interrupt 0.