Class E/F Amplifiers

Normalized Output Power

  It’s easy to show that for Class A/B/C amplifiers, the

efficiency and output power are given by:

  It’s useful to normalize the output power versus the

product of Vbk and Imax (Idc)

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class A/B/C

  As efficiency improves, the normalized output power drops

from ~10% down to 0%
EECS 242 Prof. Ali M. Niknejad (C) 2009
 Class A/B/C Properties

  Keep voltage waveform sinusoidal  amplitude is limited

to Vdd/2
  Only way to improve efficiency is to control current
  Require very large “on” current to deliver power

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class F

  Start with Class B current waveform  only odd harmonics

  Tune impedance at odd harmonics to be an open circuit to dissipate
no harmonic power but allow odd harmonics in voltage waveform
  Tune even harmonics to short circuit to avoid dissipating power

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class F Waveforms

  Maximally flat Class F waveforms.

  An ideal Class F amplifier has a square voltage waveform and
100% efficiency.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class F Efficiency

  In theory, if you can control an infinite number of harmonics,

efficiency approaches 100%

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class F Output Power

  Square wave has a peak fundamental 4/π larger than the peak
 1 dB output power enhancement
EECS 242 Prof. Ali M. Niknejad (C) 2009
 Class F Disadvantages

  Output capacitance of device not naturally absorbed into

network  need inductor to tune it out
  Difficult to control more than 5th harmonic … resonators
are lossy and additional losses present diminishing returns
on efficiency.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Switching Amplifiers

  Operate transistor in “triode” region where it acts like a

switch.
  For an ideal switch the power dissipated in the switch is zero,
right?
  Are all switching PA’s the same?
EECS 242 Prof. Ali M. Niknejad (C) 2009
 Linear Time-Varying Systems

  Even though transistor is non-linear, the operation of

the periodic switching action can be modeled as a
linear time-varying (periodic) system. The design of
the output network completely determines the
behavior of the circuit.
EECS 242 Prof. Ali M. Niknejad (C) 2009
 ce is on the voltage waveform for part of the cycle and on the current
42 the switch is closed the switch voltage
he remainder. Specifically, when Chapter
vs 3: Switching Amplifier Properties

I-V Solution for Swithing Amps

o, but when open the current is is forced to zero. If the set of times during
ch is conducting is denoted D and the set of non-conducting times denoted
onditions can be written as:

(θ ∈ D) ( vs = 0 ) (3.4)

(θ ∈ D) ( is = 0 ) (3.5)

these two constraints, the switch makes no demands on the waveforms,

the constrained portions ofFigure
the waveform are amplifier
3.2: Switching trivial to generate,
waveforms the
after applying switching constraints.
Non-zero values of current and voltage are not yet determined.
  For
non-zero portions trans-conductance
require additional effort. amplifiers, the current is known, so
the voltageconstraint
is determined
imposed onlyby theharmonics.
at the load network. Letting Zin(k) denote the impedance at the kth
ely obvious that the form of the non-zero portions of the waveform must be
  In a switching amplifier, when the switch is on, the voltage
harmonic:
mehow by the properties of the load network. The load network is LTI, and
is forced to zero, and the current through the switch can
ibed completely by its frequency-dependent input impedance, j ( αand
k – β kso
) the
take on any value. Likewise, when ( v ⁄
k ki )e the switch = Zin ( kis
) off, the (3.6)
influence it could have on the waveforms is to demanding that, at all
switch current is zero, but the voltage ∀k ∈ { 1, 2can take
, 3, 4, … } on any
he ratio betweenvalue
the voltage and current on its port be equal its port
Although this condition is easily written down, it is still not obvious how to apply it in
nce the waveforms only contain
order toharmonic
determine frequencies,
the waveforms.this
Thebecomes
difficulty alies in the fact that (3.6) is really an
EECS 242 Prof. Ali M. Niknejad (C) 2009
infinite number of independent frequency domain conditions which must be reconciled
with the very tight time-domain conditions demanded by the switch. Considerable effort
ntal period T. Similarly, the waveforms will be assumed to be periodic, having the
damental period. Figure 3.2: Switching amplifier waveforms after applying switching const
Impedance at Harmonics Non-zero values of current and voltage are not yet determine
ilizing this assumption, the switch voltage and current waveforms, vs and is
ely, may be expressed in terms ofconstraint
a Fourier series:
imposed only at the harmonics. Letting Zin(k) denote the impeda
∞
harmonic:
v s ( θ ) = V DC + v k cos ( kθ + α k ) (3.1)
j( αk – βk)
k=1
( v k ⁄ ik )e = Zin ( k )
∞
∀ k ∈ { 1, 2, 3, 4, … }
is ( θ ) = I DC + i k cos ( kθ + β k ) (3.2)
k=1 Although this condition is easily written down, it is still not obvious how
values of the parameters VDC, Iorder ik , α
DC,vk, to k, and βk, and
determine the where
waveforms. The difficulty lies in the fact that (3.6
the normalized
able θ is defined as: infinite shape,
number therefore,
of independent frequency domain conditions which must
  The waveform is completely determined
by the load
θ ≡ 2πf with
0 t network
= the--t- very impedance
2π (it’s
tight time-domain a linear
conditions
(3.3) system
demanded by the switch. Cons
T
viewed from this perspective)
has been exerted to solve for these waveforms even for specific cases such
Waveform Constraints of class-E solutions [4,31-42] each solving for a slightly different circuit top

determination the voltages and different approximations

currents for and
the a switching assumptions.
amplifier can be Typically the solutions are deriv
domain
to determining the voltages and using
currents network
on the switch theory, utilizing
itself. Once these different simplifying assumpti
EECS 242 Prof. Ali M. Niknejad (C) 2009
ms are known, the other circuit waveforms follow readily
topology, making using standard
generalization linear
or comparison difficult. To date, there has b
 a dual or inverse switching amplifier tuning. This can be done by simply inv
drive of the switch (so that the switch will be “on” at times where before it was

Inverseadmittance
Class of equalOperation
vise-versa) and by using a tuning network presenting, at each harmonic,
numerically to the original load network’s impedance. To see
clearly, consider (3.1)-(3.6) rewritten as follows:

  By duality, any PA can ∞

be transformed into it’s is ( θ ) = I DC + i k cos ( kθ + αk )

dual (where the role of k=1

∞
current/voltage are
v s ( θ ) = V DC + v k cos ( kθ + β k )
switched) by imposing k=1
the complementary (θ ∈ D) ( is = 0 )
admittance condition
(θ ∈ D) ( vs = 0 )
  For instance a Class D
voltage switching ( i k ⁄ v k )e
j ( α k – βk )
= Y in ( k )
amplifier can be ∀k ∈ { 1, 2, 3, 4, … }
transformed into a
current switching amp
EECS 242 Prof. Ali M. Niknejad (C) 2009
 Bias Scaling

  Scaling supply changes voltage/current waveforms by the

same scale factor.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Impedance Scaling

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Switch Losses

  When a switch is closed across a capacitor, an impulse

of current flows through the switch to discharge the
capacitor. The energy stored in the capacitor is
dissipated into heat through the switch. (ideal switch?)
  If you make a smaller switch, the on-resistance goes

down
EECS 242
so you have to live with finite capacitance.
Prof. Ali M. Niknejad (C) 2009
 ZVS

  A ZVS network will return the voltage to zero at the moment

of switch turn-on. To make the circuit more robust, the
derivative of the voltage can also be forced to zero (or n-
derivatives …) to obtain a maximally flat zero.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Switch Losses: ZCS Condition

  The dual of ZVS is ZCS.

  What happens if you open circuit an inductor with current
(flux)? The energy stored in the magnetic flux is dissipated
  In practice the voltage “kick” produced by the inductor will
break down the switch and conduct current.
  It’s also possible to design a load network that returns the
current to zero just before the switch opens.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Switching Inductors

  If the inductor is large enough, it’s switching behavior can be

idealized.
EECS 242 Prof. Ali M. Niknejad (C) 2009
 Class D

  Two switches used to realize square waveform.

  Series tank only allows fundamental current to flow into load.
  Switch capacitance limits efficiency in high frequency
applications.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class D-1

  The “Dual” Class D amplifier (interchange voltage/current 

square wave current, sinusoidal voltage, parallel LCR filter)
  Chokes act like current sources. ZVS by “design” but only if
there is no device capacitance to begin with.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class E

  Switch driven with 50% duty cycle. Device capacitance Cs

absorbed into network.
  The current i1 is sinusoidal and the current through the choke
is DC. The sum of these currents flows through the switch +
capacitor.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class E Currents

  When switch is closed, all the current flows through it. When
open, this same current must flow through the capacitor. The
voltage across the capacitor is given by the integral of the
current since

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class E Voltages

  We can impose voltage continuity, so θ=π. But we have two

degrees of freedom, so we can also set the derivative of the
voltage to zero (ZdVS). When both conditions are satisfied,
we have a class E amplifier.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class E Current/Voltage

ZVS & ZdVS

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class E Load & Swing

  The load is given from Fourier analysis of the current/

voltage.
  To realize a Class E amplifier requires an inductive load.
  One big disadvantage of the Class E amplifier is that the
voltage swing across the device is very large (nearly
4×VDD).

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Switching Amplifier Efficiency

  For ZVS, Psw is zero

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Switching Amplifier PAE

  This result includes the gain of the amplifier. To arrive at the

final result, we assume 100% drain efficiency and ZVS. Note
that Pin is a function of the transistor size.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Switch FOM

  It’s useful to relate the effiency to peak current/voltage swings

(stress) on the device. For a high efficiency PA we have

EECS 242 Prof. Ali M. Niknejad (C) 2009

 FOM (cont)

  Peak voltage versus DC

  Peak current versus DC
  RMS current versus DC
  Output power versus peak stress on transsitor
  Output power versus stored reactive power.
  The smaller this ratio, the more the design can tolerate output
capacitance, and hence a larger transistor with lower conductive losses.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 2 2
I RMS Ron VSW
D≈1– V
---------------------- + -------------------------------------- (4.16)
DC I DC 4πX CS V
Device
DC Size Limited I DC

becomes:
Maximum Drain Efficiency
2
IRMS R on
η D ≈ 1 – ---------------------- (4.17)
V DC I DC

und by utilizing (4.14):

2
P DC – Pdiss VDC I DC – I RMS R on
= ----------------------------- = ------------------------------------------------
- (4.18)
P in P in

  All terms except the third are invariant and only depend on the
tuning strategy.
  Minimize the third term by using the highest peak voltage
possible (minimize current through device).

EECS 242 Prof. Ali M. Niknejad (C) 2009

 2 2
I RMS Ron VSW
D≈1– V
---------------------- + -------------------------------------- (4.16)
DC I DC 4πX CS V DC
I DC

becomes: Capacitance Limited Drain Efficiency

2
IRMS R on
η D ≈ 1 – ---------------------- (4.17)
V DC I DC

und by utilizing (4.14):

  Increase device 2 size until the switch output capacitance equals
P DC – Pdiss VDC I DC – I RMS R on
the total output capacitance
= ----------------------------- = ------------------------------------------------
- (4.18)
P in P in
  All terms except the last are invariant (bias, impedance
scaling) and only depend on the switching network. Note the
third term depends on technology but is independent of
transistor size. Voltage waveform properties do not come into
play.
  To minimize the final term, maximize Cout. Final efficiency

only depends on technology RC time constant:

EECS 242 Prof. Ali M. Niknejad (C) 2009

 in efficiency, increasing the voltage andoptimized,
decreasing
I RMS 2 underVDC theIthe constraint
current in this that
case Cout has cannot
no be larger than CS
DC
η D ≈ 1 – ------------ ----------------------------- ( Ron C out ) ( 2πf 0 ) (4.36)
improves
I
on the efficiency. This is due to the fact that with increasing2 C , it is clearly best to choose Cout as
DC the 2πf transistorC V size is notout constant under
0 s DC

Reactive Energy Term

optimal asized
hange. In order to trade voltage for current, device is of
combination therefore
impedance
The further illuminate the meaning of the somewhat mysterious second term, consider
the one andwith biasoutput capacitance eq
ng must be used. During this process, the RMS current scales Iinversely 2 with Ithe
V
that VDCIDC is approximately the equal η to the ≈ 1output
–
RMSpower
------------ and DCthatDC the- 1( R
---------------------------- ⁄ ( 2πf
C 0 C S) () 2πf
is )
on out
  The second term needs scalefurther explanation:
ge level, whereas the circuit impedances D
proportionally toIDC the square of the 2 0
the magnitude ZC of the switch parallel capacitance’s impedance 2πf C
0 s at V DCthe fundamental
ge level. The   For a highly
capacitance
frequency:
efficient
CS therefore scalesamplifier,
inversely with the thenumerator
voltage level. is equal The to
The further illuminate the meaning of the somewhat mysterious
the output power, and
stor size – proportional to CS in this case – must thethendenominator
scale inversely has with thetheswitch square
capacitance admittance:
e voltage level, causing the on-resistance
thatI VDCIDC 2 isPapproximately the equal to the output power and th
η D ≈ 1 – to scale
- proportionally - ( RontoC out the)square
( 2πf 0 ) of the
RMS out
----------- --------------------- (4.37)
the Imagnitude2 ZC of the switch parallel capacitance’s impedanc
ge level. Thus for an increase in the voltageDC V DC ⁄ of
by a factor ZCk under the conditions of
frequency:
  This is a ratio of the output power to the switch’s stored
ant output power, there is a decrease in the ZRMS ≡ 1 current
⁄ ( 2πf by)a factor of k and an
C (4.38)
reactive power. We2 wish C to use a 0 tuning
2
S strategy
2 that
ase in the on-resistance by a factor of k . The product I RMS RonIRMS thereforePstays out
maximizes the reactive energyηof D ≈ the
1 – switch
-----------
I
- and minimizes - ( Ron C out ) ( 2πf 0 )
---------------------
2
ant. 78 Chapter DC 4: Predicting
V ⁄ Z Switching Amplifier
the RMS current through the switch. The voltage DC cannot
C
be traded
s before, the efficiency may befor currentaslike
expressed the previous
waveform figures of case.
merit:Z ≡ 1 ⁄ ( 2πf C )
C 0 S
Pout
2 2π ( Ron C out ) FC ≡ ----------------------(4.39)
η D ≈ 1 – ( FI FC ) -------------------------------- 2
1 ⁄ f0 V DC ⁄ ZC

e: The transistor property of interest in this case is the RonCout product, whic
EECS 242 Prof. Ali M. Niknejad (C) 2009
constant of the exponential discharge waveform occurring when the transisto
 Gain Limited PAE

  For Cs = Cout, where λ is a scaling parameter. Clearly an

optimal size exists since Ron ~ λ whereas Pin ~ 1/λ.
  The optimal PAE is given by:

Under assumption of
high drain efficiency

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Gain Limited PAE (cont)

  Considering the breakdown limitations:

  Use a tuning network with low peak to DC current/voltage.

  Note that the final term is a scaling invariant property of
transistor.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Capacitance Limited PAE

  If the optimal device is too large, it’s output cap will be

larger than Cs, and hence cannot be absorbed into the
network. Must limit device size to Cs.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Cap Limited PAE

  Make the peak voltage as large as possible and increase the

gain.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Summary

EECS 242 Prof. Ali M. Niknejad (C) 2009

 General Class E/F Design

  A switch with parallel

capacitance, an ideal choke,
and a possibly countable
infinite number of harmonic
impedances.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Switch/Cap Current

  The switch carries an impulsive

current component due to cap
discharge.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Cap Voltage

  The voltage across the

capacitor is calculated
from the current.
  The harmonic impedance
constraint implies the
following relations.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Constraint Equations

  There are |T| complex valued

equations and one real valued
equation and |T|+2 unknowns.
  These equations can be solved
for Q and ix
  The ZVS solution has an
additional constraint Q=0.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 ZVS

  It can be shown that ZVS

implies that:
  (R1,X1) is the fundamental load
impedance.
  The center and radius of the
circle is determined by the
overtone network.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 ZdVS

  The ZdVS conditions generate

additional constraints.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class E/F Amplifier Family

  Are there other interesting tuning networks besides the well

known Class E and F?

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Switching Amplifier Wish List

  ZVS Switching
  Inclusion of device output capacitance
  Simple circuit implementation
  Lower peak voltage (Fv)
  Lower RMS current (Fi)
  Capacitance Tolerance (Fc)

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class E versus F

  Consider a hybrid of Class E and F with desirable properties of

both. Construct such a hybrid by choosing harmonics to either
satisfy Class E or F conditions. Note that the fundamental
load is set by Class E ZVS conditions.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class E/F Family

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Example Class E/F Waveforms

EECS 242 Prof. Ali M. Niknejad (C) 2009

 More Waveforms

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Single Harmonic Class E/F

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Odd Harmonic Class E/F

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Even Harmonic Class E/F

EECS 242 Prof. Ali M. Niknejad (C) 2009

 N-Harmonic Class E/F

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Overall Comparison

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Direct Implementation

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Push-Pull Amplifiers

  Creation of virtual grounds at odd harmonics and open circuits

at even harmonics is very handy for designing class E/F
amplifiers.

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class E/F3 Push-Pull

  Short at third harmonic. Does not need to be high Q since

even harmonics don’t “see it”

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Even & Odd Harmonic Control

  Odd harmonics only see ZD/2

since YC is shorted to ground.
  Even harmonics see Yc to
ground

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Switching Amplifier Landscape

EECS 242 Prof. Ali M. Niknejad (C) 2009

 Class E/Fodd Amplifier

  All odd harmonics see small

impedance (ideally short) whereas
even harmonics do not see shunt
LC tank.

EECS 242 Prof. Ali M. Niknejad (C) 2009