Course Code Course Name. Credit csc403 Computer Organization and Architecture Course Objectives: 1. To have a thorough understanding of the basic structure and operation of a digital computer. 2, To discuss in detail the operation of the arithmetic unit including the algorithms & implementation of fixed-point and floating-point addition, subtraction, multiplication & division, 3. To study the different ways of communicating with I/O devices and standard /O interfaces. 4, To study the hierarchical memory system including cache memories and virtual memory. Course Outcomes: At the end of the course student should be able- To describe basic structure of the computer system. To demonstrate the arithmetic algorithms for solving ALU operations. To describe instruction level parallelism and hazards in typical processor pipelines, To describe superscalar architectures, multi-core architecture and their advantages To demonstrate the memory mapping techniques. 6. To Identify various types of buses, interrupts and 1/0 operations in a computer system Prerequisite: Digital Logic Design and Application Sr.No. [Module Detailed Content Hours Overview of Computer Architecture & Organization * Introduction * Basic organization of computer * Block level description of the functional units. Data Representation and Arithmetic Algorithms: + Integer Data computation: Addition, Subtraction. 1 Multiplication: unsigned multiplication, Booth’s 08 algorithm. * Division of integers: Restoring and non restoring division * Floating point representation. IEEE 754 floating point number representation. + Floating point arithmetic: Addition, Subtraction, Multiplication, Division * Von Neumann model, Harvard Architecture + Register Organization, Instruction formats, addressing modes, instruction cycle. Instruction interpretation and sequencing. > © ALU and Shifters 10 and * Basic pipelined datapath and control, Data Architecture dependences, data hazards, Branch hazards, delayed branches, branch prediction * Performance measures ~ CPI, speedup, efficiency, throughput and Amdahl’s law University of Mumbai, B. E. (Computer Engineering), Rev 2016 39© Hardwired control unit design methods: State table, delay clement, sequence counter with examples like control unit for multiplication and division * Microprogrammed control Unit: Microinstruction | 08 sequencing and execution. Micro operations, Wilkie’s microprogrammed Control Unit, Examples on microprograms * Classifications of primary and secondary memories. Types of RAM (SRAM, DRAM, SDRAM, DDR, SSD) and ROM, Characteristics of memory, Memory hierarchy: cost and performance measurement. Control Unit 4 Memory * Virtual Memory: Concept, Segmentation and 12 ‘Organization Paging, Address translation mechanism, * Interleaved and Associative memory. # Cache memory Concepts, Locality of reference, design problems based on mapping techniques. Cache Coherency, Write Policies * Common I/O device types and characteristics uo. «Types of data transfer techniques: Programmed I 5 | Organization Interrupt driven I/O and DMA. 06 and * Introduction to buses, Bus arbitration and multiple Peripherals bus hierarchy + Interrupt types, Interrupts handling * Introduction to parallel processing, Flynn's Classification s Advanced * Concepts of superscalar architecture, out-of-order | gg execution, speculative execution, multithreaded processor, VLIW, data flow computing. + Introduction to Multi-core processor architecture Text Book: 1. William Stallings, “Computer Organization and Architecture; Designing for Performance”, Pearson Publication, 10" Edition, 2013 2. John P. Hayes, “Computer Architecture and Organization”, McGraw-Hill, 1988 3. B. Govindarajulu, “Computer Architecture and Organization: Design Principles and Applications”, Second Edition, McGraw-Hill (India), Reference Books: Andrew S. Tanenbaum “Structured Computer Organization”, Pearson, Sixth Edition Morris Mano, “Computer System Architecture” Pearson Publication, 3" Edition, 2007 Kai Hwang, Fayé Alayé Briggs. “Computer architecture and parallel processing”, McGraw- Hill P. Pal Chaudhuri, “Computer Organization and Design” Prentice Hall India, 2004 5. Dr. M. Usha, T.S, Shrikant, “Computer System Architecture and Organization” Wiley India, 2014. bee s University of Mumbai, B. E. (Computer Engineering), Rev 2016 40Internal Assessment: Assessment consists of two class tests of 20 marks each. The first class test is to be conducted when approx. 40% syllabus is completed and second class test when additional 40% syllabus is completed. Duration of each test shall be one hour. End Semester Theory Examination: i 2. 3 Question paper will comprise of 6 questions, each carrying 20 marks. The students need to solve total 4 questions. Question No.1 will be compulsory and based on entire syllabus. Remaining question (Q.2 to Q.6) will be selected from all the modules, University of Mumbai, B. E. (Computer Engineering), Rev 2016 4l