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    Post-Layout Verification Via Simulation With Machta: Text: Chapter 13.10 Machta Manual

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    Gautam Sharma
    Post-layout verification via simulation with MachTA allows designers to: 1) Simulate post-layout netlists to verify circuit function and timing with parasitic resistances and capacitances included. 2) Execute test vector files to apply inputs and compare outputs to expected results. 3) View waveform results in the EZwave viewer to check circuit behavior.

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    Download as PDF, TXT or read online from Scribd

    Post-Layout Verification Via Simulation With Machta: Text: Chapter 13.10 Machta Manual

    Uploaded by

    Gautam Sharma
    88 views26 pages
    Post-layout verification via simulation with MachTA allows designers to: 1) Simulate post-layout netlists to verify circuit function and timing with parasitic resistances and capacitances included. 2) Execute test vector files to apply inputs and compare outputs to expected results. 3) View waveform results in the EZwave viewer to check circuit behavior.

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    MachTA

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    Post-layout verification via simulation with MachTA allows designers to: 1) Simulate post-layout netlists to verify circuit function and timing with parasitic resistances and capacitances included. 2) Execute test vector files to apply inputs and compare outputs to expected results. 3) View waveform results in the EZwave viewer to check circuit behavior.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    88 views26 pages

    Post-Layout Verification Via Simulation With Machta: Text: Chapter 13.10 Machta Manual

    Uploaded by

    Gautam Sharma
    Post-layout verification via simulation with MachTA allows designers to: 1) Simulate post-layout netlists to verify circuit function and timing with parasitic resistances and capacitances included. 2) Execute test vector files to apply inputs and compare outputs to expected results. 3) View waveform results in the EZwave viewer to check circuit behavior.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 26

    Post-Layout Verification

    via Simulation with MachTA

    Text: Chapter 13.10


    MachTA Manual
    ASIC Design Flow
    Simulation
    Behavioral
    Verify
    Model
    Behavior
    VHDL/Verilog
    Synthesis
    DFT/BIST Gate-Level Verify
    & ATPG Netlist Function

    Test vectors Full-custom IC

    Transistor-Level Verify Function


    Standard Cell IC Netlist & Timing
    & FPGA/CPLD

    Physical
    DRC & LVS Verify Function
    Layout
    Verification & Timing
    Map/Place/Route

    IC Mask Data
    Transistor-level simulation
     Eldo
     Analog simulator
     Integrated into IC-Flow tools (DA-IC, etc.)
     Uses SPICE netlists and format
     MachTA
     Analog simulator
     Accelerates simulation of large circuits
     Test vector mode for digital circuits
     To use either, first execute script ana
     Sets up links, variables, etc. on Auburn ntwk
    Eldo simulation from DA-IC
     Run simulations from within DA-IC
     Eldo, ADVance MS, Mach TA
     DA-IC invokes a “netlister” to create a circuit model from the
    schematic
     SPICE model for Eldo & Mach TA
     Eldo analyses, forces, probes, etc. same as SPICE
     View results in EZwave or Xelga
    Eldo input and output files

    -Netlist
    -Simulation commands
    -Stimulus
    SPICE “circuit” file generated by DA-IC SPICE netlist for modulo7 counter

    From ADK
    library

    Force values (created interactively)


    Force functions (1)
     DC value
     Vsigname A 0 DC 5
    Value (volts)
    V indicates Between circuit nodes
    voltage Force A and GND (node 0)
    name
    Force functions (2)
     Pulse/square wave
     Vsigname B 0 pulse 0 5 0 0.1N 0.1N 20N 40N
    Rise Fall Pulse Period
    Nodes Initial
    Pulsed time time width tp
    Voltage
    Voltage tr tf tw
    v1
    v2 Delay from start of period
    for waveform to begin - td
    tp
    v2

    v1

    td tr tw tf
    Force functions (3)
     Pattern wave (for
    logic 0 & 1 values)
    Vname B 0 pattern 5 0 5n 0.1n 0.1n 10n 011010 R
    Bit pattern
    Rise & Fall
    Between circuit Logic 1 & 0 Time between
    Nodes B & GND voltages Delay tochanges Duration of
    (node 0) Repeat
    waveform bit value
    the pattern
    begin (optional)

    1 1 1
    0 0 0

    delay pattern
    Force functions (4)
     Piecewise-linear wave (digital if only two voltages)
    Vsigname B 0 pwl (0n 0 5n 0 5.1n 5 10n 5 10.1n 0 R)
    T0 V0 T1 V1 T2 V2 T3 V3 T4 V4
    Nodes
    Repeat
    (optional)
    V2 V3

    V0 V1 V4
    0 5 5.1 10 10,1
    T0 T1 T2 T3 T4

    Other options: R=value (time at which to begin repeat – one of Tn values)


    default = 0 if no value specified
    TD=value (delay before waveform begins)
    Eldo simulation of modulo7 counter
    (transient analysis)
    Post-layout simulation with MachTA
     MachTA is an accelerated Spice simulator
     Digital & mixed-signal circuits
     Analyze timing effects pre- and post-layout
     SPICE netlists with parasitic R/C
     Execute test vector file to verify functionality
     Algorithms support large designs
     Partition design, simulate only partitions with changes
     Combine time-driven & event-driven operation
     Solves linearized models using proprietary high-performance,
    graph-theory based, matrix solution algorithm

    Mach PA (mpa) does current & power analysis


    Mach TA flow diagram
    SPICE
    netlist

    $ADK/technology/mta/tsmc035
    Prepare Calibre-extracted netlist for Mach
    TA (file.pex.netlist)
     In file.pex.netlist, insert model definitions and VDD/GND voltage source
    functions after comment header:
    * File: m7.pex.netlist
    * Created: Thu Nov 15 15:25:56 2007
    * Program "Calibre xRC"
    * Version "v2005.2_9.14"
    .model n nmos
    .model p pmos
    Vvdd VDD 0 5
    Vgnd GND 0 0
     Delete (or comment out with * in 1st column) .subcircuit statement and
    any continuation lines (for long statement):
    *.subckt modulo7 CLK Q[1] CLEARBAR I[1] Q[0] I[0] Q[2]
    *+ L_CBAR I[2] GND VDD
     Change .ends to .END near end of file
    Post-layout simulation with Mach TA
     Invoke Mach TA:
    ana - command file to initialize Anacad SW
    mta –ezw –t $ADK/technology/mta/tsmc035 count4.sp
    Transistor calibration files for this technology
    Generate waveform database & display in EZwave
    Netlist, modified as
    on previous slide

    Other options:
    -do file (execute commands from file.do – instead of design.spdo
    -donot (run without simulating – compile only)
    -b (run in batch mode – no GUI – output to console)
    Mach TA main window
    Mach TA simulation commands
    Sample Mach TA “dofile”
    (transient analysis)
    plot v(clk) v(q[2]) v(q[1]) v(q[0]) Signals to observe in EZwave
    measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5v
    l load
    l reset
    h count
    l clk Measure time from rising edge of clk (TRIGger)
    run 5 ns to 1st rising edge of q[0] (TARGet) - voltages
    h reset
    h clk
    Drive signals low/high (Lsim format)
    run 5 ns
    l clk
    run 5 ns Simulate for 5 ns
    h clk
    run 5 ns

    Command to execute: dofile file.do


    EZwave waveform viewer
    (results for previous dofile)

    Double-click
    signal name
    to display.
    Alternative Mach TA “dofile”
    (same result as previous example)
    plot v(clk) v(q[2]) v(q[1]) v(q[0])
    measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0])
    VAL=2.5v
    vpulse Vclk clk 0 pulse(0 3.3 10n .05n .05n 10n 20n)
    l load v-levels delay rise fall width period
    l reset
    Nodes to which
    h count source connected
    run 5 ns Periodic pulses
    h reset Voltage source name
    run 200 ns
    Mach TA – test vector file
     Verify design functionality/behavior
     apply test vectors
     capture outputs
     compare outputs to expected result
     vectors/outputs from behavioral simulation
     Command to execute a test vector file:
    run –tvend tvfile.tv

    test vector file (next slide)


    Test vector file format
    # Test vector file for modulo7 counter
    CODEFILE
    UNITS ps
    RISE_TIME 50 signal order within vectors
    FALL_TIME 50 Header
    INPUTS clk,reset,load,count,i[2],i[1],i[0];
    OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max);
    CODING(ROM)
    RADIX <11113>3; Vector format
    @0 <01105>X; Sample 5 fs before next vector
    @2000 <00105>0;
    @7000 <01105>0;
    @10000 <11105>5;
    @20000 <01015>5; Vectors: @time <input_vector>expected_output
    @30000 <11015>6;
    @40000 <01015>6;
    @50000 <11015>0;
    @60000 <01015>0;
    …..
    END

    Test vectors derived from behavioral simulation results


    Behavioral simulation listing Corresponding Mach TA test vector file
    Alternate test vector file
    (clock generated separately by voltage source)

    vpulse vclk clk 0


    pulse(0 3.3 10n .5n .5n 10n 20n)

    Can mix other simulation


    commands with test vector
    application.
    Mach TA structure & schematic viewer
    Summary
     Simulation at each stage of ASIC design
     behavioral model
     synthesized netlist
     pre-layout schematic/netlist
     post-layout netlist
     ADVance MS combines 3 technologies to cover the above
     digital (VHDL, Verilog)
     analog/mixed-signal (VHDL-AMS, Verilog-A)
     transistor level (Eldo, Mach TA)
     ASIC Design Kit (ADK) supports all tools in the design flow,
    including simulation

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