18CSS201J - ANALOG AND

DIGITAL ELECTRONICS

Record

Register no :

Name of the student :

Semester :

Department :
 SRM INSTITUTE OF SCIENCE AND TECHNOLOGY
S.R.M. NAGAR, KATTANKULATHUR -603 203
KANCHEEPURAM DISTRICT

BONAFIDE CERTIFICATE

Register No_______________

Certified to be the bonafide record of work done

by___________________________________________of CSE , B.Tech Degree

course in the Practical 18CSS201J –ANALOG AND DIGITAL ELECTRONICS in

SRM INSTITUTE OF SCIENCE AND TECHNOLOGY, Kattankulathur during the

academic year 20__-20__

Lab Incharge

Date: Year Co-ordinator

Submitted for University Examination held

in _____________________, SRM INSTITUTE OF SCIENCE AND

TECHNOLOGY, Kattankulathur.

Date: Examiner-1 Examiner-2

 INDEX SHEET

Exp. Date of Name of the Experiment Page Marks Staff

No Experiment No (20) Signature

Total Mark :
Average :
Staff Signature :
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No:1a Date:

Design and Implementation of Half Wave and Full Wave Rectifiers

using simulation package and demonstrate its working.
AIM
To design and analysis of half wave rectifier for the varying R and C
components.

APPARATUS REQUIRED
S.no Apparatus Type Range Quantity
1) Diode 1N4001 1
2) Resistor 470Ω 1
3) Capacitor 470µF 1
4) Ac voltage source 4Vpk,60Hz 1

THEORY
The process of converting an alternating current into direct current is known
as rectification. The unidirectional conduction property of semiconductor diodes
(junction diodes) is used for rectification. Rectifiers are of two types: (a) Half wave
rectifier and (b) Full wave rectifier. In a half-wave rectifier circuit, during the
positive half-cycle of the input, the diode is forward biased and conducts. Current
flows through the load and a voltage is developed across it. During the negative half-
cycle, it is reverse bias and does not conduct. Therefore, in the negative half cycle
of the supply, no current flows in the load resistor as no voltage appears across it.
Thus the dc voltage across the load is sinusoidal for the first half cycle only and a
pure a.c. input signal is converted into a unidirectional pulsating output signal.

FORMULA:
Vrms=Vm/2

Vdc =Vm/𝜋

ɣ = √(Vrms/Vdc)2-1
 η= Pdc/Pac * 100%

Pdc= (Vdc)2 / RL

Pac= (Vrms)2 / RL

PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button
on the bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select Master database, select group as diode and select 1N4001 from
component.
5. Select the Resistor and capacitor from master database and select group as
basic and family as resistor and capacitor respectively, select the resistor and
capacitor from components.
6. Place all the components, connect the components via wire to get the circuit
diagram as below.

CIRCUIT DIAGRAM
7.Double click the output wire and change the net properties as below.

8.Select the option Simulate → Analysis and simulation → Transient.

9.In analysis parameter tab, set the following values found in the below figure.
10.Go to the Output tab and select V(Out) variable and press add button to push the
selected variable for analysis. Refer figure below.
11.Press Run to see the simulation results in the Grapher View.

12.Result of transient analysis of half wave rectifier with filter.

13.Remove the Capacitor from the circuit for rectifier without filter.

14.Run the simulation again to get the result of transient analysis of half wave
rectifier without filter.

15.You can also view the resultant graph for Halfwave rectifier with and without
filter through the Multisim oscilloscope.

Multisim
Oscilloscope
WAVEFORMS:
16. Note down the Vm value from the above oscilloscope Image for with and without
filter.

17. Replace the RL Values, note down Vm, Do the necessary calculation and fill the
tabulation as below.

TABULATION
Experiment No:1b Date:

Design and Implementation of Half Wave and Full Wave Rectifiers

using simulation package and demonstrate its working.
AIM
To design and analysis of full wave rectifier for the varying R and C
component.

APPARATUS REQUIRED
S.No Apparatus Type Range Quantity
1) Diode 1N4001 4
2) Resistor 1kΩ 1
3) Capacitor 100µF 1
4) AC voltage source 4Vpk,60 Hz 1

THEORY
Another type of circuit that produces the same output as a full-wave rectifier
is that of the Bridge Rectifier. This type of single-phase rectifier uses 4 individual
rectifying diodes connected in a "bridged" configuration to produce the desired
output but does not require a special centre tapped transformer, thereby reducing its
size and cost. The single secondary winding is connected to one side of the diode
bridge network and the load to the other side. The 4 diodes labeled D arranged in
"series pairs" with only two diodes conducting current during each half cycle. During
the positive half cycle of the supply, diodes D1 and D2 conduct in se D3 and D4 are
reverse biased and the current flows through the load as shown below . During the
negative half cycle of the supply, diodes D3 and D4 conduct in series, but diodes D1
and D2 switch of as they are now reverse biased. The current flowing through the
load is the same direction as before.
FORMULA:
Vrms =Vr(P-P)/2√3

Vdc = Vm-Vr(P-P)

ɣ =Vrms/Vdc

η= Pdc/Pac * 100%

Pdc= (Vdc)2 / RL

Pac= (Vrms)2 / RL

PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button
on the bottom right corner of the window opened.
3. Select the components by pressing Ctrl+W.
4. Select Master database, select group as diode and select 1N4001 from
component.
5. Select the Resistor and capacitor from master database and select group as
basic and family as resistor and capacitor respectively, select the resistor and
capacitor from components.
6. Place all the components, connect the components via wire to get the circuit
diagram as below.

CIRCUIT DIAGRAM
7. Select the option Simulate → Analysis and simulation → interactive
simulation.
8. In analysis parameter tab, set the default values found in the below figure and
hit Run then view the output using oscilloscope.
9. Note down the Vm , Vr(P-P)/ value from the above oscilloscope.

10. Replace the RL Values, note down Vm , Vr(P-P)/, Do the necessary calculation and
fill the tabulation as below.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

11. Remove the Capacitor from the circuit for rectifier without filter.

12.Repeat Step 9 and 10 to complete the tabulation.

TABULATION

RESULT
Thus, the characteristics of Half Wave, Full Wave were studied.

Experiment No:2 Date:

Design and implement a Schmitt trigger using Op-Amp using a

simulation package and demonstrate its working.
AIM
Design and implement a Schmitt trigger using Op-Amp using a simulation
package and demonstrate its working.

APPARATUS REQUIRED
S.NO APPARATUS TYPE RANGE QUANTITY
1) OP-AMP 741 1
2) Resistor 3kΩ,10kΩ,100kΩ 3
3) Function generator 1Hz 1
4) DC power 12V,12V,2.2V 3
5) oscilloscope 1

THEORY
 A Schmitt trigger circuit is also called a regenerative comparator circuit. The
circuit is designed with a positive feedback and hence will have a regenerative action
which will make the output switch levels. Also, the use of positive voltage feedback
instead of a negative feedback, aids the feedback voltage to the input voltage, instead
of opposing it. The use of a regenerative circuit is to remove the difficulties in a zero-
crossing detector circuit due to low frequency signals and input noise voltages.

Shown below is the circuit diagram of a Schmitt trigger. It is basically an inverting

comparator circuit with a positive feedback. The purpose of the Schmitt trigger is to
convert any regular or irregular shaped input waveform into a square wave output
voltage or pulse. Thus, it can also be called a squaring circuit.

PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button
on the bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select Master database, select group as Analog and select OP-AMP 741 from
component.
5. Select the Resistor and voltage from master database and select group as basic
and source as resistor and voltage respectively from components.
6. Place the function generator (refer figure below) and select Sinusoid Signal
with the frequency of 1Hz by double clicking the function generator.
 7. Place Oscilloscope in the circuit (Refer the Image above).
8. Place all the components, connect the components via wire to get the circuit
diagram as below.

CIRCUIT DIAGRAM
 9. Run the simulation to view the Oscilloscope results.

10.Note down the result and note down the Peak to Peak Voltage, Frequency of the
square wave generated and tabulate the result below.

TABULATION
I/P I/P SIGNAL OUTPUT VOLTAGE OUTPUT
VOLTAGE FREQUENCY FREQUENCY
10 1Hz

RESULT
Thus the Schmitt trigger was designed and the output voltage was tabulated.

Experiment No: 3 Date:

 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Design and implement a rectangular waveform generator (Op-Amp
relaxation oscillator) using a simulation package and demonstrate
the working of it.
AIM
To design and implement a rectangular waveform generator (Op-Amp
relaxation oscillator) using a simulation package and demonstrate the working of it.

APPARATUS REQUIRED
S.No Apparatus Type Range Quantity
1) OP-AMP 741 1
2) Resistor 50kΩ,35kΩ,30kΩ 3
3) Capacitor .01µF 1
4) Voltage source 12V 2
5) oscilloscope 1

THEORY
Rectangular Waves are generated when the Op-Amp is forced to operate in
the saturation region. That is, the output of the op-amp is forced to swing
respectively between +Vsat And -Vsat resulting in the generation of square wave.
The square wave generator is also called a free-running or astable Multivibrator
Assuming the voltage across capacitor C is zero at the instant the d.c Supply voltage
at +Vcc and VEE are applied. Initially the capacitance C acts, as a short circuit. The
gain of the Op-Amp is very large hence V1 drives the output of the Op-Amp to its
saturation.

PROCEDURE
 1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button
on the bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select Master database, select group as Analog and select OP-AMP 741 from
component.
5. Select the Resistor and capacitor from master database and select group as
basic and family as resistor and capacitor respectively, select the resistor and
capacitor from components
6. Select the voltage source from the source group and set as 12V.
7. Place Oscilloscope in the circuit.
8. Place all the components, connect the components via wire to get the circuit
diagram as below.

CIRCUIT DIAGRAM

9. Run the simulation.

10.Note down the result and note down the Peak to Peak Voltage, Frequency of the
wave generated and tabulate the result below.

TABULATION
FREQUENCY AMPLITUDE(V) TIME(ms)

RESULT
Thus, the rectangular wave generator was designed, and the corresponding
values are tabulated.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No:4 Date:

Design and implementation of transistor as a switch

AIM:
1. To observe the action of a Transistor as an electronic switch.
2. To measure the voltage across the transistor when it is ON and when it
is OFF.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) Transistor BC107BP 1

2) Resistor 1kΩ,10kΩ 1(each)

3) Multimeter 1

4) DC power 5V 2(each)

5) Switch 1

6) Probe 1

THEORY
The computers of today do not process numbers in the base 10
(i.e., 0, 1, 2, 3, ...,9). Computers instead use binary logic of base 2 (0 and 1) to perform their
functions. One fundamental circuit is the transistor switch, also known as an inverter. Here, a
transistor connected in a common-emitter fashion inverts a signal. That is, if a high-input
signal is applied, a low-output signal is created. If a low-input signal is applied, then a high-
output signal is created.

In a transistor switch circuit, a voltage level applied to the base terminal will control the
potential at the collector. In this fashion, the transistor can be used to turn on or off circuitry
connected to the collector. This common-emitter circuit is being switched from cutoff to
saturation. In this experiment, a transistor will be connected to demonstrate this switching
ability.
PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select Master database, select group as Transistor and select BC107BP from
component.
5. Select the Resistor and voltage from master database and select group as basic and
source as resistor and voltage respectively from components.
6. Select the Switch from master database and select group as basic to get components.
7. Place all the components, connect the components via wire to get the circuit diagram
as below.
8. Select the probe from master database and select group as Indicators, select the family
as probe to get component. Place it as per circuit diagram.
9. Place multimeter from instruments to know the voltage when the switch is ON and
OFF.

CIRCUIT DIAGRAM:

10. Run the simulation to view the multimeter voltage results voltage when the switch is
ON and OFF.
11. Tabulate the results below.
TABULATION
Switch Status of the Probe Multimeter voltage

ON

OFF

RESULT
Thus, the transistor as a switch was designed and the output voltage and status of the
Probe was tabulated.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No:5 Date:

Design CMOS Inverter and measure its propagation delay for

both the rising edge and the falling edge
AIM:
To Design CMOS Inverter and measure its propagation delay for both the rising edge
and the falling edge.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) Transistor Pmos 1

2) Transistor Nmos 1

3) Pulse Voltage 1

4) Oscilloscope 1

THEORY
The inverter is universally accepted as the most basic logic gate doing a Boolean
operation on a single input variable. Fig.1 depicts the symbol, truth table and a general structure
of a CMOS inverter. As shown, the simple structure consists of a combination of an pMOS
transistor at the top and a nMOS transistor at the bottom.

Fig.1: Symbol, circuit structure and truth table of a CMOS inverter

CMOS is also sometimes referred to as complementary-symmetry metal–oxide–
semiconductor. The words "complementary-symmetry" refer to the fact that the typical digital
design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal
oxide semiconductor field effect transistors (MOSFETs) for logic functions. Two important
characteristics of CMOS devices are high noise immunity and low static power consumption.
Significant power is only drawn while the transistors in the CMOS device are switching
between on and off states. Consequently, CMOS devices do not produce as much waste heat
as other forms of logic, for example transistor-transistor logic (TTL) or NMOS logic, which
uses all n-channel devices without p-channel devices.

PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select Master database, select group as Transistor, family as Transistors Virtual select
MOS_N_4T from component.
5. Select Master database, select group as Transistor, family as Transistors Virtual select
MOS_P_4T from component.
6. Select Master database, select group as Source, family as Signal Voltage Sources, select
Pulse Voltage from component.
7. Double click the pulse voltage and make the settings as below.
 8. Place all the components, connect the components via wire to get the circuit diagram
as below.
9. Place Oscilloscope from instruments to see the results.

CIRCUIT DIAGRAM:
10. Run the simulation to view the Oscilloscope.
11. If you look at the input and output curve, output is inverted w.r.t input.

12. Go to View and select grapher view to measure the Propagation delay.
 13. Tabulate the results below.

TABULATION
Input Voltage(V) Output Voltage(V) Propagation Delay

3.3

RESULT

Thus, the Design of CMOS Inverter and measure its propagation delay for both the
rising edge and the falling edge was tabulated.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No:6 Date:

6.a. Design and implementation of Binary to gray code converters

using logic gates
AIM:
1. To design and implementation of Binary to gray code converters using Multisim.
2. Hardware Implementation of the same with NI Analog Discovery 2.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7486 1

2) LED 4

3) Switch 4

4) DC Power Source 1

5) NI Analog Discovery 2

6) Wires As Required

THEORY
The logical circuit which converts binary code to equivalent gray code is known as binary to
gray code converter. The gray code is a non-weighted code. The successive gray code differs
in one bit position only that means it is a unit distance code. It is also referred as cyclic code.
It is not suitable for arithmetic operations. It is the most popular of the unit distance codes. It
is also a reflective code. An n-bit Gray code can be obtained by reflecting an n-1 bit code about
an axis after 2n-1 rows, and putting the MSB of 0 above the axis and the MSB of 1 below the
axis.
PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select Master database, select group as TTL, select Family as 74STD,Select 7486N
from component.

5. Multi-section component being placed, a dialog box appears as shown in the figure
below:

6. Click A, you will get one Xor gate. It will be labelled as U1A.
7. Again you will get Multi-section option in that you select B from label U1.

8. Like wise try to get another Xor gate.

9. Select the Switch from master database and select group as basic to get components.
10. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -DC Power.
11. Double the DC Power to change Voltage as 5V.
12. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -Ground.
13. Select the LED from master database, Group-Basic, Family-3D_Virtual, Component -
Led1_Red.
14. Place all the components, connect the components via wire to get the circuit diagram
as below.
CIRCUIT DIAGRAM:

15. Run the simulation change the value of the switches to verify the truth table.

Truth Table
BINARY GRAY CODE
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
 G3 = ∑(8,9,10,11,12,13,14,15) G2 = ∑(4,5,6,7,8,9,10,11)

G1= ∑(2,3,4,5,10.,11,12,13) G0 = ∑(1,2,3,5,6,9,10,13,14)

Binary to Gray code converter Using XOR Gates Only

6.b.Design and implementation of Gray to Binary code converters
using logic gates
AIM:
1. To design and implementation of Gray to Binary code converters using Multisim.
2. Hardware Implementation of the same with NI Analog Discovery 2.

PROCEDURE:
Follow the same procedure as for Binary to gray to complete the circuit diagram as below.

CIRCUIT DIAGRAM:
Truth Table
GRAY CODE BINARY CODE
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0
6.C. Hardware Implementation of Code Converters Using
NI Analog Discovery 2

Introduction to NI Analog Discovery 2(AD 2):

Gives students access to a 100 MS/s oscilloscope, a logic analyzer, and six other instruments
in a pocket-sized lab device.

The Analog Discovery 2 transforms any PC into an electrical engineering workstation. This
USB-powered device enables students to build and test analog and digital circuits in any
environment with the functionality of traditional benchtop instruments. In addition to the 100
MS/s two-channel oscilloscope, the Analog Discovery 2 provides a two-channel waveform
generator, 16-channel logic analyzer, 16-channel digital pattern generator, spectrum analyzer,
network analyzer, voltmeter, and ±5 VDC adjustable power supplies.
AIM:
Hardware Implementation of the same with NI Analog Discovery 2.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7486 1

2) NI Analog Discovery 2

3) Wires As Required

PROCEDURE:
1. Build the Binary to Gray and Vice Versa Circuit in the breadboard.
2. Use the below pin diagram for circuit connection in breadboard.
3. Use the above pin connection from AD2.
4. Red wire belongs to power. Take a wire connect to red wire and wire it to pin 14.
5. Black wire belongs to ground. Take a wire connect to Black wire and wire it to pin 7.
6. Use Pin 0- Pin 3 of AD2 as Input.
7. Connect Pin 0- Pin 3 of AD2 to B0,B1,B2,B3.
8. Use Pin 4- Pin 7 of AD2 as Output.
9. Connect Pin 4- Pin 7 of AD2 to G0,G1,G2,G3.
10. Search the application in PC for Waveform 2015.
11. In the above window click the Supplies Instrument.

12. Use only positive supply. Change the voltage as 5.

13. Click Master Enable button to enable the Instrument.
 14. In the Welcome tab, select Static IO Instrument to open.

15. Configure Digital I/O signal into a switch by selecting 0, Switch, Push/Pull (1/0) as
seen in Figure below for DIO 0-DIO3

16. Run both Static IO and Power Supplies Instrument.

17. Verify the truth table by changing the switch position.

RESULT
Thus, design and implementation of Binary to gray code converters and Vice Versa
using logic gates using Multisim and NI Analog Discovery 2.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No:7 Date:

7.a. Design and implementation of Magnitude Comparator

combinational circuits using simulation package

AIM:
1. To design and implementation of Magnitude Comparator using Multisim.
2. Hardware Implementation of the same with NI Analog Discovery 2.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7485 1

2) LED 4

3) Switch 4

4) DC Power Source 1

5) NI Analog Discovery 2 1

6) Wires As Required

7) Breadboard 1

THEORY
Magnitude Comparator is a logical circuit, which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high
speed 4-bit Magnitude comparator, which compares two 4-bit words. The A = B
Input must be held high for proper compare operation.
PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select Master database, select group as TTL, select Family as 74STD, Select 7485N
from component.
5. Select the Master database, select group as Basic, select Family as Switch, Select
DSWPK_8 from component.
6. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -DC Power.
7. Double the DC Power to change Voltage as 5V.
8. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -Ground.
9. Select the LED from master database, Group-Basic, Family-3D_Virtual, Component -
Led1_Red.
10. Place all the components, connect the components via wire to get the circuit diagram
as below.
11. Run the simulation change the value of the switches to verify the truth table.

CIRCUIT DIAGRAM:
Truth Table:

7.B. Hardware Implementation Using NI Analog Discovery 2

AIM:
Hardware Implementation of the same with NI Analog Discovery 2.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7485 1

2) NI Analog Discovery 2 1

3) Wires As Required

4) Breadboard 1
CIRCUIT CONNECTION:

PROCEDURE:
1. Fix the IC 7485 in the breadboard.
2. Red wire belongs to power. Take a wire connect to red wire and wire it to pin 16.
3. Black wire belongs to ground. Take a wire connect to Black wire and wire it to pin 8.
4. Short pins 4,2 of the IC and wire it to ground.
5. Interconnect pin 3 and 16.
6. Use Pin 0 - Pin 7 of AD2 as Input.
7. Connect Pin 0 - Pin 7 of AD2 to IC Pin 15,13,12,10,1,14,11,9 (A3, A2, A1, A0, B3,
B2, B1, B0) respectively.
8. Use Pin 13- Pin 15 of AD2 as Output.
9. Connect Pin13- Pin15 of AD2 to IC pin 5,6,7 respectively.
10. Search the application in PC for Waveform 2015.
11. In the above window click the Supplies Instrument.

12. Use only positive supply. Change the voltage as 5.

13. Click Master Enable button to enable the Instrument.
14. In the Welcome tab, select Static IO Instrument to open.
 15. Configure Digital I/O signal into a switch by selecting 0-7 Switch to Push/Pull (1/0)
as seen in Figure below for DIO 0-DIO7

16. Run both Static IO and Power Supplies Instrument.

17. Verify the truth table by changing the switch position.

RESULT
Thus, design and implementation of Magnitude Comparator using Multisim and NI
Analog Discovery 2 is done.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No:8 Date:

8.a. Design and implementation of Synchronous sequential

circuits using Simulation Package

AIM:
1. To design and implementation of D Flip Flop using Multisim.
2. Hardware Implementation of the same with NI Analog Discovery 2.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7474 1

2) LED 4

3) Switch 4

4) DC Power Source 1

5) Digital Clock 1

THEORY
A D-type flip-flop is a clocked flip-flop which has two stable states. A D-type flip-
flop operates with a delay in input by one clock cycle. Thus, by cascading many D-type flip-
flops delay circuits can be created, which are used in many applications such as in digital
television systems.

A D-type flip-flop is also known as a D flip-flop or delay flip-flop. A D-type flip-flop

consists of four inputs:

• Data input
• Clock input
• Set input
• Reset input
It also has two outputs, with one being logically inverse of other. The data input is either
logic 0 or 1, meaning low or high voltage. The clock input helps in synchronizing the circuit
to an external signal. The set input and reset input are mostly held low. A D-type flip-flop can
have two possible values. When input D = 0, the flip-flop undergoes a reset, which means the
output would be set to 0. When input D = 1, the flip-flop does a set, which makes the output
1. There are several applications in which a D-type flip-flop is used, such as in frequency
dividers and data latches.
PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select Master database, select group as TTL, select Family as 74STD, Select 7474N
from component.
5. Select the Master database, select group as Basic, select Family as Switch, Select
DIPSW1 from component.
6. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -DC Power.
7. Double the DC Power to change Voltage as 5V.
8. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -Ground.
9. Select the LED from master database, Group-Basic, Family-3D_Virtual, Component -
Led1_Red.
10. Select the Digital Clock from master database, Group-Source, Family-Digital _Sources,
Component -Digital _Clock.
11. Place all the components, connect the components via wire to get the circuit diagram
as below.
12. Preset and clear pin of the IC 7474 is given +5V.
13. Run the simulation change the value of the switches to verify the truth table.

PIN DIAGRAM:
CIRCUIT DIAGRAM:

Truth Table:
8.b. Hardware Implementation Using NI Analog Discovery 2
AIM:
Hardware Implementation of the same with NI Analog Discovery 2.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7474N 1

2) NI Analog Discovery 2 1

3) Wires As Required

4) Breadboard 1

PROCEDURE:
1. Fix the IC 7474 in the breadboard.
2. Red wire of AD2 belongs to power. Take a wire connect to red wire and wire it to pin
14.
3. Black wire of AD2 belongs to ground. Take a wire connect to Black wire and wire it to
pin 7.
4. Use Pin 0 of AD2 as Input. Connect to IC7474 Pin 2.
5. Use Pin 1 of AD2 as Clock. Connect to IC7474 Pin 3.
6. Use Pin 3 of AD2 as Output. Connect to IC7474 Pin 5.
7. Search the application in PC for Waveform 2015.
8. In the above window click the Supplies Instrument.

9. Use only positive supply. Change the voltage as 5.

10. Click Master Enable button to enable the Instrument.
11. In the Welcome tab, select Static IO Instrument to open.
 12. Configure Digital I/O signal into a switch by selecting 0 Switch to Push/Pull (1/0) as
seen in Figure below for DIO 0-DIO7

13. Click open the pattern instrument.

14. Click this green plus to add the signal.
15. Select signal and select DIO1.

16. Select the black arrow under type column and select clock.
17. Run Pattern, Static IO and Power Supplies Instrument.
18. Verify the truth table by changing the switch position and note the results from Static
IO instrument.

RESULT
Thus, the implementation of D flip flop using Multisim and NI Analog Discovery 2 is
done.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No: 9 Date:

9. Implementation of SISO, SIPO, PISO and PIPO shift

registers using Flip- flops

SISO

AIM:
1. To design and implementation of Shift Register using Multisim.
2. Hardware Implementation of the same with NI Analog Discovery 2.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7474 4

2) LED 4

3) Switch 4

4) DC Power Source 1

5) Digital Clock 1

THEORY
Shift registers are a type of sequential logic circuit, mainly for storage of digital data.
They are a group of flip-flops connected in a chain so that the output from one flip-flop
becomes the input of the next flip-flop. All the flip-flops are driven by a common clock, and
all are set or reset simultaneously.

The serial in/serial out shift register accepts data serially – that is, one bit at a time on
a single line. It produces the stored information on its output also in serial form. The serial
in/parallel out shift register accepts data serially – that is, one bit at a time on a single line. It
produces the stored information on its output in parallel form. The parallel in/serial out shift
register accepts data in parallel. It produces the stored information on its output also in serial
form. The parallel in/parallel out shift register accepts data in parallel. It produces the stored
information on its output in parallel form.
PIN DIAGRAM:

PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select Master database, select group as TTL, select Family as 74STD, Select 7474N
from component.
5. Place 4 such ICs in the workspace.
6. Select the Master database, select group as Basic, select Family as Switch, Select
DIPSW1 from component.
7. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -DC Power.
8. Double the DC Power to change Voltage as 5V.
9. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -Ground.
10. Select the Probe from master database, Group-Indicator, Family-Probe, Component -
Probe_ Dig_ green.
11. Select the Digital Clock from master database, Group-Source, Family-Digital _Sources,
Component -Digital _Clock.
12. Double click clock source and change to 50Hz.
13. Preset and clear pin of the IC 7474 is given +5V.
14. Place all the components, connect the components via wire to get the circuit diagram
as below.
CIRCUIT DIAGRAM:

15. Run the simulation change the value of the switch you can see the probe lights glows
one by one.
16. Use Logic analyzer instrument in Multisim to view all the signal.

16.Connect output from each of the flip flop to Logic analyzer Pin 1 to 4.
17. Double click the instrument to open.
18.Click the set button.

19. Set the clock rate to 50hz and clock source as Internal. Unchange all the other parameters.
20.Change the switch position in the Multisim while running the simulation.
21.stop the simulation and open the Grapher view to analyze your signals.
OUTPUT:

Hardware Implementation Using NI Analog Discovery 2(SISO)

AIM:
Hardware Implementation of the same with NI Analog Discovery 2.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7474N 4

2) NI Analog Discovery 2 1

3) Wires As Required

4) Breadboard 1
CIRCUIT DIAGRAM:

PROCEDURE:
1. Fix the IC 7474 in the breadboard.
2. Red wire of AD2 belongs to power. Take a wire connect to red wire, take it to all the
IC pin 14.
3. Black wire of AD2 belongs to ground. Take a wire connect to Black wire take it to all
the IC pin 7.
4. Give the connections in the bread board as per the circuit diagram above.
5. Use Pin 0 of AD2 as Input. Connect to IC7474 Pin 2.
6. Use Pin 1 of AD2 as Clock. Connect to IC7474 Pin 3.
7. Take the output of the flip flop connect it to AD2 DIO Pin 2.
8. Search the application in PC for Waveform 2015.
9. In the above window click the Supplies Instrument.

10. Use only positive supply. Change the voltage as 5.

11. Click Master Enable button to enable the Instrument.
12. In the Welcome tab, select Static IO Instrument to open.
13. Configure Digital I/O signal into a switch as Switch to Push/Pull (1/0) as seen in
Figure below for DIO 0

14. Click open the pattern instrument.

15. Click this green plus to add the signal.
16. Select signal and select DIO1.

17. Click the black arrow under type column and select clock.
18. Double click the parameter column and change the value to 1hz, otherwise output will
respond very fast to view.
19. Run Pattern, Static IO and Power Supplies Instrument to see the output.
 SIPO
MULTISIM

ANALOG DISCOVERY 2
CIRCUIT DIAGRAM

PROCEDURE:
1. Fix the IC 7474 in the breadboard.
2. Red wire of AD2 belongs to power. Take a wire connect to red wire, take it to all the
IC pin 14.
3. Black wire of AD2 belongs to ground. Take a wire connect to Black wire take it to all
the IC pin 7.
4. Give the connections in the bread board as per the circuit diagram above.
5. Use Pin 0 of AD2 as Input. Connect to IC7474 Pin 2.
6. Use Pin 1 of AD2 as Clock. Connect to IC7474 Pin 3.
7. Take the output of each flip flop connect it to AD2 DIO Pin 2-Pin 5.
8. Search the application in PC for Waveform 2015.
9. In the above window click the Supplies Instrument.

10. Use only positive supply. Change the voltage as 5.

11. Click Master Enable button to enable the Instrument.
12. In the Welcome tab, select Static IO Instrument to open.
 13. Configure Digital I/O signal into a switch as Switch to Push/Pull (1/0) as seen in
Figure below for DIO 0

14. Click open the pattern instrument.

15. Click this green plus to add the signal.
16. Select signal and select DIO1.

17. Click the black arrow under type column and select clock.
18. Double click the parameter column and change the value to 1hz, otherwise output will
respond very fast to view.
19. Run Pattern, Static IO and Power Supplies Instrument to see the output.

PISO
MULTISIM
ANALOG DISCOVERY 2
CIRCUIT DIAGRAM

TRUTH TABLE

CLK DA DB DC DD Q out

1 1 0 1 1 1

2 0 1 0 1 1

3 0 0 1 0 0

4 0 0 0 1 1

PIPO
MULTISIM
ANALOG DISCOVERY 2
CIRCUIT DIAGRAM

TRUTH TABLE

RESULT
Thus, the design and implementation of shift registers using Multisim and NI Analog
Discovery 2 is done.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No:10 Date:

HDL program for combinational circuits

AIM:
To obtain the VHDL program of Binary to gray code converters using Multisim.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7486 1

2) Probe 1

3) Switch 1

4) DC Power Source 1

PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -Vcc.
5. Double the DC Power to change Voltage as 5V.
6. Select the Probe from master database, Group-Indicators, Family-Probe, Component -
Probe_BLUE.
7. Select the Switch from master database, Group-Basic, Family-Switch, Component -
DSWPK_4.
8. Place all the components.
9. Go to the option Place in main tab and select the option New PLD Subcircuit
10.Select Next

11.Select Next
 12.Select the option uncheck all.

13.Select SW0, SW1, SW2, SW3 and LED0, LED1, LED2, LED3.

14.Select Finish. You will get subcircuit named BCD to Gray.

15.Double click the subcircuit to open.

16.Select the option ,open subsheet.

17.Edit the workspace as below.

18.Select three XOR gate and place in the workspace and complete the connection as

above.
 19. Complete the circuit as below in the main blank design workspace

20.Run the simulation change the value of the switches to verify the truth table.

21.To view the VHDL Program. Go to the main tab,click on the transfer and select export
to PLD,you will view the figure below.
22. Select, Generate and save VHDL files option.

23.Browse the file location to store the VHDL file then click finish.

24.Open the file with notepad, from the corresponding location.

VHDL Program:
---------------------------------------------------
-- Sheet: Programmable Logic Device 1
-- RefDes: PLD1
-- Part Number: XC3S500E
-- Generated By: Multisim
--
-- Author: DELL LAPTOP
-- Date: Saturday, September 14 13:19:25, 2019
---------------------------------------------------

---------------------------------------------------
-- Use: This file defines the top-level of the design
-- Use with the exported package file
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;

library work;
use work.Design1_pkg.ALL;

entity ProgrammableLogicDevice1 is
port (

SW0 : in std_logic;
SW1 : in std_logic;
SW2 : in std_logic;
SW3 : in std_logic;
LED0 : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
sys_clk_pin : in std_logic
);
end ProgrammableLogicDevice1;

architecture behavioral of ProgrammableLogicDevice1 is

component AUTO_IBUF
port(
I : in std_logic;
O : out std_logic
);
end component;

component AUTO_OBUF
port(
 I : in std_logic;
O : out std_logic
);
end component;

component XOR2_NI
port (
B : in STD_LOGIC := 'X';
A : in STD_LOGIC := 'X';
Y : out STD_LOGIC := 'U'
);
end component;
signal \1\ : std_logic;
signal \7\ : std_logic;
signal \6\ : std_logic;
signal \5\ : std_logic;
signal \4\ : std_logic;
signal \3\ : std_logic;
signal \2\ : std_logic;
begin
SW0_AUTOBUF : AUTO_IBUF
port map( I => SW0, O => \1\ );
SW1_AUTOBUF : AUTO_IBUF
port map( I => SW1, O => \2\ );
SW2_AUTOBUF : AUTO_IBUF
port map( I => SW2, O => \4\ );
SW3_AUTOBUF : AUTO_IBUF
port map( I => SW3, O => \5\ );
LED0_AUTOBUF : AUTO_OBUF
port map( I => \1\, O => LED0 );
LED1_AUTOBUF : AUTO_OBUF
port map( I => \3\, O => LED1 );
LED2_AUTOBUF : AUTO_OBUF
port map( I => \6\, O => LED2 );
LED3_AUTOBUF : AUTO_OBUF
port map( I => \7\, O => LED3 );
U1 : XOR2_NI
port map( A => \1\, B => \2\, Y => \3\ );
U2 : XOR2_NI
port map( A => \2\, B => \4\, Y => \6\ );
U3 : XOR2_NI
port map( A => \4\, B => \5\, Y => \7\ );
end behavioral;

RESULT
Thus, obtained VHDL program for Binary to gray code converter.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No:11 Date:

HDL implementation of D-Flip-Flop

AIM:
To obtain the VHDL program of D Flip Flop using Multisim.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7474 1

2) Probe 1

3) Switch 1

4) DC Power Source 1

PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select the Probe from master database, Group-Indicators, Family-Probe, Component -
Probe_BLUE.
5. Select the Switch from master database, Group-Basic, Family-Switch, Component -
DSWPK_4.
6. Select the Probe from master database, Group-Source, Family-Digital_Source,
Component - Digital_Clock.
7. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -Vcc.
8. Place all the components.
9. Go to the option Place in main tab and select the option New PLD Subcircuit
10.Select Next

11.Select Next

12.Select the option uncheck all.

13.Select SW0, SW1 and LED0.

14.Select Finish. You will get subcircuit named D flip flop.

15.Double click the subcircuit to open.

 16.Select the option, open subsheet.

17. Select D flip flop from component list and edit the workspace as below.

18.Edit the main workspace as below.

19.Run the simulation change the value of the switches to verify the truth table.

20.To view the VHDL Program. Go to the main tab,click on the transfer and select export
to PLD,you will view the figure below.
21. Select, Generate and save VHDL files option.

23.Browse the file location to store the VHDL file then click finish.

24.Open the file with notepad, from the corresponding location.

VHDL Program:
---------------------------------------------------

-- Sheet: D Flip Flop

-- RefDes: PLD1

-- Part Number: XC3S500E

-- Generated By: Multisim

--

-- Author: DELL LAPTOP

-- Date: Sunday, September 15 18:51:20, 2019

---------------------------------------------------

---------------------------------------------------

-- Use: This file defines the top-level of the design

-- Use with the exported package file

---------------------------------------------------

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.numeric_std.ALL;

library work;

use work.ff_pkg.ALL;

entity DFlipFlop is

port (

SW0 : in std_logic;

SW1 : in std_logic;

LED0 : out std_logic;

sys_clk_pin : in std_logic

);

end DFlipFlop;

architecture behavioral of DFlipFlop is

component AUTO_IBUF

port(
 I : in std_logic;

O : out std_logic

);

end component;

component AUTO_OBUF

port(

I : in std_logic;

O : out std_logic

);

end component;

component FF_D_CO_NI

Port ( D : in STD_LOGIC;

CLK : in STD_LOGIC;

Q : out STD_LOGIC;

Qneg : out STD_LOGIC);

end component;

signal \1\ : std_logic;

signal \3\ : std_logic;

signal \2\ : std_logic;

begin

SW0_AUTOBUF : AUTO_IBUF

port map( I => SW0, O => \1\ );

SW1_AUTOBUF : AUTO_IBUF

port map( I => SW1, O => \2\ );

LED0_AUTOBUF : AUTO_OBUF

port map( I => \3\, O => LED0 );

U2 : FF_D_CO_NI

port map( D => \1\, Q => \3\, CLK => \2\, Qneg => open );

end behavioral;

RESULT
Thus, obtained VHDL program for D flip flop.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No:12a Date:

HDL for SISO

AIM:
To obtain the VHDL program for SISO.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7474 1

2) Probe 1

3) Switch 1

4) DC Power Source 1

PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select the Probe from master database, Group-Indicators, Family-Probe, Component -
Probe_BLUE.
5. Select the Switch from master database, Group-Basic, Family-Switch, Component -
DSWPK_1.
6. Select the Probe from master database, Group-Source, Family-Digital_Source,
Component - Digital_Clock.
7. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -Vcc.
8. Place all the components.
9. Go to the option Place in main tab and select the option New PLD Subcircuit
10.Select Next

11.Select Next

12.Select the option uncheck all.

13.Select SW0, SW1 and LED0, LED1, LED2, LED3.

14.Select Finish. You will get subcircuit named SISO register.

15.Double click the subcircuit to open.

16.Select the option, open subsheet.

17. Select D flip flop from component list and edit the workspace as below.

18.Edit the main workspace as below.

19.Run the simulation, change the value of the switch S1. If the switch is ON you can see
the LEDs from 0 to 3 glows sequentially one after other.Same way if the switch is OFF
the LEDs will put off sequentially one after other.Serially the data shifts from one flip
flop to other for each clock pulse.

20.To view the VHDL Program. Go to the main tab,click on the transfer and select export
to PLD,you will view the figure below.

21. Select, Generate and save VHDL files option.

23.Browse the file location to store the VHDL file then click finish.

24.Open the file with notepad, from the corresponding location.

VHDL Program:
---------------------------------------------------
-- Sheet: register
-- RefDes: PLD1
-- Part Number: XC3S500E
-- Generated By: Multisim
--
-- Author: DELL LAPTOP
-- Date: Saturday, September 21 19:12:45, 2019
---------------------------------------------------

---------------------------------------------------
-- Use: This file defines the top-level of the design
-- Use with the exported package file
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;

library work;
use work.Design1_pkg.ALL;

entity aregisterz is
port (

SW0 : in std_logic;
SW1 : in std_logic;
LED0 : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
sys_clk_pin : in std_logic
);
end aregisterz;

architecture behavioral of aregisterz is

component AUTO_IBUF
port(
I : in std_logic;
O : out std_logic
);
end component;

component AUTO_OBUF
port(
 I : in std_logic;
O : out std_logic
);
end component;

component FF_D_CO_NI
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC;
Qneg : out STD_LOGIC);
end component;
signal \1\ : std_logic;
signal \2\ : std_logic;
signal \3\ : std_logic;
signal \5\ : std_logic;
signal \6\ : std_logic;
signal \4\ : std_logic;
begin
SW0_AUTOBUF : AUTO_IBUF
port map( I => SW0, O => \2\ );
SW1_AUTOBUF : AUTO_IBUF
port map( I => SW1, O => \3\ );
LED0_AUTOBUF : AUTO_OBUF
port map( I => \1\, O => LED0 );
LED1_AUTOBUF : AUTO_OBUF
port map( I => \4\, O => LED1 );
LED2_AUTOBUF : AUTO_OBUF
port map( I => \5\, O => LED2 );
LED3_AUTOBUF : AUTO_OBUF
port map( I => \6\, O => LED3 );
U1 : FF_D_CO_NI
port map( D => \2\, Q => \1\, CLK => \3\, Qneg => open );
U2 : FF_D_CO_NI
port map( D => \1\, Q => \4\, CLK => \3\, Qneg => open );
U3 : FF_D_CO_NI
port map( D => \4\, Q => \5\, CLK => \3\, Qneg => open );
U4 : FF_D_CO_NI
port map( D => \5\, Q => \6\, CLK => \3\, Qneg => open );
end behavioral;

RESULT
Thus, obtained VHDL program for SISO.
Experiment No:12b Date:

HDL for Johnson Counter

AIM:
To obtain the VHDL program for Johnson Counter.

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) IC IC 7474 1

2) Probe 1

3) Switch 1

4) DC Power Source 1

PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl+W.
4. Select the Probe from master database, Group-Indicators, Family-Probe, Component -
Probe_BLUE.
5. Select the Switch from master database, Group-Basic, Family-Switch, Component -
DSWPK_1.
6. Select the Probe from master database, Group-Source, Family-Digital_Source,
Component - Digital_Clock.
7. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component -Vcc.
8. Place all the components.
9. Go to the option Place in main tab and select the option New PLD Subcircuit
10.Select Next

11.Select Next

12.Select the option uncheck all.

13.Select SW0, SW1 and LED0, LED1, LED2, LED3.

14.Select Finish. You will get sub circuit named johnson counter.

15.Double click the sub circuit to open.

16.Select the option, open sub sheet.

17. Select D flip flop from component list and edit the workspace as below.

18.Edit the main workspace as below.

19.See to that switch S1 to be in ON state always.

20. Run the simulation change the value of the switches to verify the truth table for johnson
counter.

21.To view the VHDL Program. Go to the main tab,click on the transfer and select export
to PLD,you will view the figure below.

21. Select, Generate and save VHDL files option.

23.Browse the file location to store the VHDL file then click finish.

24.Open the file with notepad, from the corresponding location.

VHDL Program:
---------------------------------------------------
-- Sheet: Johnson counter
-- RefDes: PLD1
-- Part Number: XC3S500E
-- Generated By: Multisim
--
-- Author: DELL LAPTOP
-- Date: Saturday, September 21 19:44:58, 2019
---------------------------------------------------

---------------------------------------------------
-- Use: This file defines the top-level of the design
-- Use with the exported package file
---------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;

library work;
use work.Design2_pkg.ALL;

entity aregisterz is
port (

SW0 : in std_logic;
SW1 : in std_logic;
LED0 : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
sys_clk_pin : in std_logic
);
end aregisterz;

architecture behavioral of aregisterz is

component AUTO_IBUF
port(
I : in std_logic;
O : out std_logic
);
end component;

component AUTO_OBUF
port(
I : in std_logic;
 O : out std_logic
);
end component;

component FF_D_CO_NI
Port ( D : in STD_LOGIC;
CLK : in STD_LOGIC;
Q : out STD_LOGIC;
Qneg : out STD_LOGIC);
end component;

component XOR2_NI
port (
B : in STD_LOGIC := 'X';
A : in STD_LOGIC := 'X';
Y : out STD_LOGIC := 'U'
);
end component;
signal \1\ : std_logic;
signal \7\ : std_logic;
signal \2\ : std_logic;
signal \3\ : std_logic;
signal \5\ : std_logic;
signal \6\ : std_logic;
signal \4\ : std_logic;
begin
SW0_AUTOBUF : AUTO_IBUF
port map( I => SW0, O => \7\ );
SW1_AUTOBUF : AUTO_IBUF
port map( I => SW1, O => \3\ );
LED0_AUTOBUF : AUTO_OBUF
port map( I => \1\, O => LED0 );
LED1_AUTOBUF : AUTO_OBUF
port map( I => \4\, O => LED1 );
LED2_AUTOBUF : AUTO_OBUF
port map( I => \5\, O => LED2 );
LED3_AUTOBUF : AUTO_OBUF
port map( I => \6\, O => LED3 );
U1 : FF_D_CO_NI
port map( D => \2\, Q => \1\, CLK => \3\, Qneg => open );
U2 : FF_D_CO_NI
port map( D => \1\, Q => \4\, CLK => \3\, Qneg => open );
U3 : FF_D_CO_NI
port map( D => \4\, Q => \5\, CLK => \3\, Qneg => open );
U4 : FF_D_CO_NI
port map( D => \5\, Q => \6\, CLK => \3\, Qneg => open );
U5 : XOR2_NI
port map( A => \6\, B => \7\, Y => \2\ );
end behavioral;
RESULT
Thus, obtained VHDL program for Johnson counter.
 DEPT. Of Computer Science Engineering

SRM IST, Kattankulathur – 603 203

Sub Code & Name: 18CSS201J - ANALOG AND DIGITAL ELECTRONICS

Title of Experiment

Name of the candidate

Register Number

Date of Experiment

Mark Split Up

S.No Description Maximum Mark Mark Obtained

1 Oral Viva 5
2 Execution 10
3 Model Calculation / Result 5
Analysis
Total 20

Staff Signature with date

Experiment No:13 Date:

Design and Implement an A/D converter

AIM:
To Design and Implement an A/D converter using Multisim

APPARATUS REQUIRED

S.No Apparatus Type Range Quantity

1) ADC 1

2) DC Source 10v 1

3) Potentiometer 1k 1

4) Pulse Voltage Source 1

5) Probe 8

6) Hex display 2

7) Voltmeter 1

PROCEDURE
1. Open Multisim.
2. Select file → New → Blank and recent → select Blank and click create button on the
bottom right corner of the window opened.
3. Select the components by pressing ctrl + W.
4. Select the Probe from master database, Group-Indicators, Family-Probe, Component -
Probe_ BLUE.
5. Select the DC Power Source from master database, Group-Source, Family-Power
Source, Component - Vcc.
6. Select the ADC from master database, Group-Mixed, Family-ADC_DAC, Component
-ADC.
7. Select the Potentiometer from master database, Group-Basic, Family-Potentiometer,
Component -1k.
8. Select the Pulse Voltage Source from master database, Group-Source, Family-signal_
voltage_ sources, Component - pulse_ voltage.
9. Select the Hex display from master database, Group-Indicators, Family-Hex_ Displays,
Component -DCD_ Hex.
10. Select the Voltmeter from master database, Group-Indicators, Family-Voltmeter,
Component - VOLTMETER_H.
11. Set Pulse voltage source as in the figure below.

12. Place all the components. Give the connection as per the figure below.

13. Note down the value from the voltmeter for analog value, digital value from probes and
hex display for the corresponding change in potentiometer value.
14. Complete the tabulation below. One example is given in the tabulation below.
TABULATION:

Potentiometer Analog(v) Digital Hex display

(%)
(Output of (Value of probe)
Voltmeter)
(D0 D1 D2 D3 D4
D5 D6 D7)

20%=200Ω 1 00110001 8C

Result:

Thus the design and implementation of ADC is done with Multisim.